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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 11/15] riscv: Make start.S available for all targets
Date: Mon, 10 Sep 2018 21:37:36 -0700	[thread overview]
Message-ID: <1536640660-3376-12-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1536640660-3376-1-git-send-email-bmeng.cn@gmail.com>

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/Makefile               | 2 +-
 arch/riscv/cpu/Makefile           | 2 ++
 arch/riscv/cpu/ax25/Makefile      | 2 --
 arch/riscv/cpu/{ax25 => }/start.S | 0
 arch/riscv/cpu/u-boot.lds         | 2 +-
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/riscv/cpu/{ax25 => }/start.S (100%)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index af432e1..8fb6a88 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,7 +3,7 @@
 # Copyright (C) 2017 Andes Technology Corporation.
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-head-y := arch/riscv/cpu/$(CPU)/start.o
+head-y := arch/riscv/cpu/start.o
 
 libs-y += arch/riscv/cpu/
 libs-y += arch/riscv/cpu/$(CPU)/
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 63de163..2cc6757 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -2,4 +2,6 @@
 #
 # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 
+extra-y = start.o
+
 obj-y += cpu.o
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
index c3f164c..2ab0342 100644
--- a/arch/riscv/cpu/ax25/Makefile
+++ b/arch/riscv/cpu/ax25/Makefile
@@ -3,6 +3,4 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-extra-y	= start.o
-
 obj-y	:= cpu.o
diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/start.S
similarity index 100%
rename from arch/riscv/cpu/ax25/start.S
rename to arch/riscv/cpu/start.S
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index f414473..11bc4a7 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -11,7 +11,7 @@ SECTIONS
 {
 	. = ALIGN(4);
 	.text : {
-		arch/riscv/cpu/ax25/start.o	(.text)
+		arch/riscv/cpu/start.o	(.text)
 	}
 
 	/* This needs to come before *(.text*) */
-- 
2.7.4

  parent reply	other threads:[~2018-09-11  4:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-11  4:37 [U-Boot] [PATCH v2 00/15] riscv: Add QEMU virt board support Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 02/15] riscv: Remove setup.h Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 04/15] riscv: Remove mach type Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 05/15] riscv: Move the linker script to the CPU root directory Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 06/15] riscv: Fix coding style issues in the linker script Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 08/15] riscv: Add a helper routine to print CPU information Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel Bin Meng
2018-09-11  4:37 ` Bin Meng [this message]
2018-09-11  4:37 ` [U-Boot] [PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 14/15] riscv: Add QEMU virt board support Bin Meng
2018-09-11  4:37 ` [U-Boot] [PATCH v2 15/15] riscv: Move do_reset() to a common place Bin Meng

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