[PATCH 0/6] Initial Vega20 support for KFD

[PATCH 0/6] Initial Vega20 support for KFD

[Felix Kuehling]

This patch series is based on amd-staging-drm-next + the patch series
"KFD upstreaming September 2018".

Emily Deng (1):
  drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of
    Vega10

Shaoyun Liu (5):
  drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
  drm/amdkfd: Make the number of SDMA queues variable
  drm/amd: Interface change to support 64 bit page_table_base
  drm/amdgpu: Add vega20 support on kfd probe
  drm/amdkfd: Vega20 bring up on amdkfd side

 drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 23 +++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c         | 50 +++++++++++++++-------
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h         |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c             | 12 ++++--
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c              |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_device.c            | 33 ++++++++++++++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 18 +++++---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  1 -
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c       |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c      |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c   |  3 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c       |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c    |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |  3 +-
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c          |  1 +
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h    | 10 ++---
 20 files changed, 136 insertions(+), 54 deletions(-)

-- 
2.7.4

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[PATCH 1/6] drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine

[Felix Kuehling]

From: Shaoyun Liu <Shaoyun.Liu@amd.com>

Change doorbell assignments to allow routing doorbells for 8 user
mode SDMA queues per engine.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h             | 14 ++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c      | 38 +++++++++++++++----------
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h |  6 ++--
 3 files changed, 33 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e992e0f..afa9e77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -409,16 +409,16 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
 	AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
 
 	/*
-	 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
+	 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
 	 * Graphics voltage island aperture 1
-	 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
+	 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
 	 */
 
-	/* sDMA engines */
-	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,
-	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
-	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,
-	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
+	/* sDMA engines  reserved from 0xe0 -oxef  */
+	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,
+	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,
+	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
+	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
 
 	/* Interrupt handler */
 	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d7f08e3..bf0b012 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -126,7 +126,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 {
-	int i;
+	int i, n;
 	int last_valid_bit;
 	if (adev->kfd) {
 		struct kgd2kfd_shared_resources gpu_resources = {
@@ -165,7 +165,15 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 				&gpu_resources.doorbell_physical_address,
 				&gpu_resources.doorbell_aperture_size,
 				&gpu_resources.doorbell_start_offset);
-		if (adev->asic_type >= CHIP_VEGA10) {
+
+		if (adev->asic_type < CHIP_VEGA10) {
+			kgd2kfd->device_init(adev->kfd, &gpu_resources);
+			return;
+		}
+
+		n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
+
+		for (i = 0; i < n; i += 2) {
 			/* On SOC15 the BIF is involved in routing
 			 * doorbells using the low 12 bits of the
 			 * address. Communicate the assignments to
@@ -173,20 +181,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 			 * process in case of 64-bit doorbells so we
 			 * can use each doorbell assignment twice.
 			 */
-			gpu_resources.sdma_doorbell[0][0] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE0;
-			gpu_resources.sdma_doorbell[0][1] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
-			gpu_resources.sdma_doorbell[1][0] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE1;
-			gpu_resources.sdma_doorbell[1][1] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
-			/* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
-			 * SDMA, IH and VCN. So don't use them for the CP.
-			 */
-			gpu_resources.reserved_doorbell_mask = 0x1f0;
-			gpu_resources.reserved_doorbell_val  = 0x0f0;
+			gpu_resources.sdma_doorbell[0][i] =
+				AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
+			gpu_resources.sdma_doorbell[0][i+1] =
+				AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
+			gpu_resources.sdma_doorbell[1][i] =
+				AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
+			gpu_resources.sdma_doorbell[1][i+1] =
+				AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
 		}
+		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
+		 * SDMA, IH and VCN. So don't use them for the CP.
+		 */
+		gpu_resources.reserved_doorbell_mask = 0x1e0;
+		gpu_resources.reserved_doorbell_val  = 0x0e0;
 
 		kgd2kfd->device_init(adev->kfd, &gpu_resources);
 	}
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 4ef0a50..0545888 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -146,10 +146,10 @@ struct kgd2kfd_shared_resources {
 	 * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
 	 *
 	 * KFD currently uses 1024 (= 0x3ff) doorbells per process. If
-	 * doorbells 0x0f0-0x0f7 and 0x2f-0x2f7 are reserved, that means
-	 * mask would be set to 0x1f8 and val set to 0x0f0.
+	 * doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
+	 * mask would be set to 0x1e0 and val set to 0x0e0.
 	 */
-	unsigned int sdma_doorbell[2][2];
+	unsigned int sdma_doorbell[2][8];
 	unsigned int reserved_doorbell_mask;
 	unsigned int reserved_doorbell_val;
 
-- 
2.7.4

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[PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10

[Felix Kuehling]

From: Emily Deng <Emily.Deng@amd.com>

Correct the format

For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  9 +++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++++++++++++++++++--------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 12 +++++++++---
 3 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index afa9e77..e60de88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
 	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
 	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
 
+	/* For vega10 sriov, the sdma doorbell must be fixed as follow
+	 * to keep the same setting with host driver, or it will
+	 * happen conflicts
+	 */
+	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
+	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
+	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
+	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
+
 	/* Interrupt handler */
 	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
 	AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index bf0b012..7a165a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 			 * process in case of 64-bit doorbells so we
 			 * can use each doorbell assignment twice.
 			 */
-			gpu_resources.sdma_doorbell[0][i] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
-			gpu_resources.sdma_doorbell[0][i+1] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
-			gpu_resources.sdma_doorbell[1][i] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
-			gpu_resources.sdma_doorbell[1][i+1] =
-				AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
+			if (adev->asic_type == CHIP_VEGA10) {
+				gpu_resources.sdma_doorbell[0][i] =
+					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
+				gpu_resources.sdma_doorbell[0][i+1] =
+					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
+				gpu_resources.sdma_doorbell[1][i] =
+					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
+				gpu_resources.sdma_doorbell[1][i+1] =
+					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
+			} else {
+				gpu_resources.sdma_doorbell[0][i] =
+					AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
+				gpu_resources.sdma_doorbell[0][i+1] =
+					AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
+				gpu_resources.sdma_doorbell[1][i] =
+					AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
+				gpu_resources.sdma_doorbell[1][i+1] =
+					AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
+			}
 		}
 		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
 		 * SDMA, IH and VCN. So don't use them for the CP.
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index df13840..6265361 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
 		DRM_INFO("use_doorbell being set to: [%s]\n",
 				ring->use_doorbell?"true":"false");
 
-		ring->doorbell_index = (i == 0) ?
-			(AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
-			: (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
+		if (adev->asic_type == CHIP_VEGA10)
+			ring->doorbell_index = (i == 0) ?
+				(AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
+				: (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
+		else
+			ring->doorbell_index = (i == 0) ?
+				(AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
+				: (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
+
 
 		sprintf(ring->name, "sdma%d", i);
 		r = amdgpu_ring_init(adev, ring, 1024,
-- 
2.7.4

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[PATCH 3/6] drm/amdkfd: Make the number of SDMA queues variable

[Felix Kuehling]

From: Shaoyun Liu <Shaoyun.Liu@amd.com>

Vega20 supports 8 SDMA queues per engine

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c               | 13 ++++++++++++-
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c |  6 ++++--
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h |  1 -
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h                 |  1 +
 4 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 2e844d3..1327816 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -53,6 +53,7 @@ static const struct kfd_device_info kaveri_device_info = {
 	.needs_iommu_device = true,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info carrizo_device_info = {
@@ -69,6 +70,7 @@ static const struct kfd_device_info carrizo_device_info = {
 	.needs_iommu_device = true,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info raven_device_info = {
@@ -84,6 +86,7 @@ static const struct kfd_device_info raven_device_info = {
 	.needs_iommu_device = true,
 	.needs_pci_atomics = true,
 	.num_sdma_engines = 1,
+	.num_sdma_queues_per_engine = 2,
 };
 #endif
 
@@ -101,6 +104,7 @@ static const struct kfd_device_info hawaii_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info tonga_device_info = {
@@ -116,6 +120,7 @@ static const struct kfd_device_info tonga_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = true,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info fiji_device_info = {
@@ -131,6 +136,7 @@ static const struct kfd_device_info fiji_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = true,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info fiji_vf_device_info = {
@@ -146,6 +152,7 @@ static const struct kfd_device_info fiji_vf_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 
@@ -162,6 +169,7 @@ static const struct kfd_device_info polaris10_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = true,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info polaris10_vf_device_info = {
@@ -177,6 +185,7 @@ static const struct kfd_device_info polaris10_vf_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info polaris11_device_info = {
@@ -192,6 +201,7 @@ static const struct kfd_device_info polaris11_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = true,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info vega10_device_info = {
@@ -207,6 +217,7 @@ static const struct kfd_device_info vega10_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
 static const struct kfd_device_info vega10_vf_device_info = {
@@ -222,9 +233,9 @@ static const struct kfd_device_info vega10_vf_device_info = {
 	.needs_iommu_device = false,
 	.needs_pci_atomics = false,
 	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 2,
 };
 
-
 struct kfd_deviceid {
 	unsigned short did;
 	const struct kfd_device_info *device_info;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 4088889..77d56ef 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -109,7 +109,7 @@ static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
 {
 	return dqm->dev->device_info->num_sdma_engines
-			* KFD_SDMA_QUEUES_PER_ENGINE;
+			* dqm->dev->device_info->num_sdma_queues_per_engine;
 }
 
 void program_sh_mem_settings(struct device_queue_manager *dqm,
@@ -1843,7 +1843,9 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
 	}
 
 	for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
-		for (queue = 0; queue < KFD_SDMA_QUEUES_PER_ENGINE; queue++) {
+		for (queue = 0;
+		     queue < dqm->dev->device_info->num_sdma_queues_per_engine;
+		     queue++) {
 			r = dqm->dev->kfd2kgd->hqd_sdma_dump(
 				dqm->dev->kgd, pipe, queue, &dump, &n_regs);
 			if (r)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index e7bd19d..70e38a2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -33,7 +33,6 @@
 
 #define KFD_UNMAP_LATENCY_MS			(4000)
 #define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (2 * KFD_UNMAP_LATENCY_MS + 1000)
-#define KFD_SDMA_QUEUES_PER_ENGINE		(2)
 
 struct device_process_node {
 	struct qcm_process_device *qpd;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 5709f0c..cf34887 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -176,6 +176,7 @@ struct kfd_device_info {
 	bool needs_iommu_device;
 	bool needs_pci_atomics;
 	unsigned int num_sdma_engines;
+	unsigned int num_sdma_queues_per_engine;
 };
 
 struct kfd_mem_obj {
-- 
2.7.4

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[PATCH 4/6] drm/amd: Interface change to support 64 bit page_table_base

[Felix Kuehling]

From: Shaoyun Liu <Shaoyun.Liu@amd.com>

amdgpu_gpuvm_get_process_page_dir should return the page table address
in the format expected by the pm4_map_process packet for all ASIC
generations.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h            |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c     |  7 ++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c     |  7 ++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c     |  7 +++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c      |  8 ++++++--
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 11 ++++++-----
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c      |  3 +--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h                 |  2 +-
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h       |  4 ++--
 9 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index db93c92..a4e38b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -173,7 +173,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 				struct amdgpu_vm *vm);
 void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
-uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct kgd_dev *kgd, uint64_t va, uint64_t size,
 		void *vm, struct kgd_mem **mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index b2e45c8..244d983 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -142,7 +142,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 static void set_scratch_backing_va(struct kgd_dev *kgd,
 					uint64_t va, uint32_t vmid);
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-		uint32_t page_table_base);
+		uint64_t page_table_base);
 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
@@ -874,7 +874,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 }
 
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-			uint32_t page_table_base)
+			uint64_t page_table_base)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
 
@@ -882,7 +882,8 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 		pr_err("trying to set page table base for wrong VMID\n");
 		return;
 	}
-	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
+	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
+		lower_32_bits(page_table_base));
 }
 
 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index dd94b70..9f14991 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -98,7 +98,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 static void set_scratch_backing_va(struct kgd_dev *kgd,
 					uint64_t va, uint32_t vmid);
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-		uint32_t page_table_base);
+		uint64_t page_table_base);
 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 
@@ -833,7 +833,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 }
 
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-		uint32_t page_table_base)
+		uint64_t page_table_base)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
 
@@ -841,7 +841,8 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 		pr_err("trying to set page table base for wrong VMID\n");
 		return;
 	}
-	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
+	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
+			lower_32_bits(page_table_base));
 }
 
 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 3dc987c..6dcbd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -138,7 +138,7 @@ static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 		uint8_t vmid);
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-		uint32_t page_table_base);
+		uint64_t page_table_base);
 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 static void set_scratch_backing_va(struct kgd_dev *kgd,
 					uint64_t va, uint32_t vmid);
@@ -1012,11 +1012,10 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 }
 
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-		uint32_t page_table_base)
+		uint64_t page_table_base)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	uint64_t base = (uint64_t)page_table_base << PAGE_SHIFT |
-		AMDGPU_PTE_VALID;
+	uint64_t base = page_table_base | AMDGPU_PTE_VALID;
 
 	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 		pr_err("trying to set page table base for wrong VMID %u\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index e7ceae0..8138b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1133,11 +1133,15 @@ void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
 	amdgpu_vm_release_compute(adev, avm);
 }
 
-uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
 {
 	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	struct amdgpu_bo *pd = avm->root.base.bo;
+	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 
-	return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
+	if (adev->asic_type < CHIP_VEGA10)
+		return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
+	return avm->pd_phys_addr;
 }
 
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 77d56ef..afa2167 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -656,7 +656,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
 	struct queue *q;
 	struct mqd_manager *mqd_mgr;
 	struct kfd_process_device *pdd;
-	uint32_t pd_base;
+	uint64_t pd_base;
 	int retval = 0;
 
 	pdd = qpd_to_pdd(qpd);
@@ -676,7 +676,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
 
 	/* Update PD Base in QPD */
 	qpd->page_table_base = pd_base;
-	pr_debug("Updated PD address to 0x%08x\n", pd_base);
+	pr_debug("Updated PD address to 0x%llx\n", pd_base);
 
 	if (!list_empty(&qpd->queues_list)) {
 		dqm->dev->kfd2kgd->set_vm_context_page_table_base(
@@ -717,7 +717,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
 {
 	struct queue *q;
 	struct kfd_process_device *pdd;
-	uint32_t pd_base;
+	uint64_t pd_base;
 	int retval = 0;
 
 	pdd = qpd_to_pdd(qpd);
@@ -737,7 +737,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
 
 	/* Update PD Base in QPD */
 	qpd->page_table_base = pd_base;
-	pr_debug("Updated PD address to 0x%08x\n", pd_base);
+	pr_debug("Updated PD address to 0x%llx\n", pd_base);
 
 	/* activate all active queues on the qpd */
 	list_for_each_entry(q, &qpd->queues_list, list) {
@@ -761,7 +761,7 @@ static int register_process(struct device_queue_manager *dqm,
 {
 	struct device_process_node *n;
 	struct kfd_process_device *pdd;
-	uint32_t pd_base;
+	uint64_t pd_base;
 	int retval;
 
 	n = kzalloc(sizeof(*n), GFP_KERNEL);
@@ -779,6 +779,7 @@ static int register_process(struct device_queue_manager *dqm,
 
 	/* Update PD Base in QPD */
 	qpd->page_table_base = pd_base;
+	pr_debug("Updated PD address to 0x%llx\n", pd_base);
 
 	retval = dqm->asic_ops.update_qpd(dqm, qpd);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
index 684a3bf..33830b1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
@@ -71,8 +71,7 @@ static int pm_map_process_v9(struct packet_manager *pm,
 		uint32_t *buffer, struct qcm_process_device *qpd)
 {
 	struct pm4_mes_map_process *packet;
-	uint64_t vm_page_table_base_addr =
-		(uint64_t)(qpd->page_table_base) << 12;
+	uint64_t vm_page_table_base_addr = qpd->page_table_base;
 
 	packet = (struct pm4_mes_map_process *)buffer;
 	memset(buffer, 0, sizeof(struct pm4_mes_map_process));
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index cf34887..917392c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -504,11 +504,11 @@ struct qcm_process_device {
 	 * All the memory management data should be here too
 	 */
 	uint64_t gds_context_area;
+	uint64_t page_table_base;
 	uint32_t sh_mem_config;
 	uint32_t sh_mem_bases;
 	uint32_t sh_mem_ape1_base;
 	uint32_t sh_mem_ape1_limit;
-	uint32_t page_table_base;
 	uint32_t gds_size;
 	uint32_t num_gws;
 	uint32_t num_oac;
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 0545888..1849e58 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -407,9 +407,9 @@ struct kfd2kgd_calls {
 			struct dma_fence **ef);
 	void (*destroy_process_vm)(struct kgd_dev *kgd, void *vm);
 	void (*release_process_vm)(struct kgd_dev *kgd, void *vm);
-	uint32_t (*get_process_page_dir)(void *vm);
+	uint64_t (*get_process_page_dir)(void *vm);
 	void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
-			uint32_t vmid, uint32_t page_table_base);
+			uint32_t vmid, uint64_t page_table_base);
 	int (*alloc_memory_of_gpu)(struct kgd_dev *kgd, uint64_t va,
 			uint64_t size, void *vm,
 			struct kgd_mem **mem, uint64_t *offset,
-- 
2.7.4

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[PATCH 5/6] drm/amdgpu: Add vega20 support on kfd probe

[Felix Kuehling]

From: Shaoyun Liu <Shaoyun.Liu@amd.com>

Add Vega20 support in amdgpu_amdkfd_device_probe.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 7a165a9..c733a8f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -79,6 +79,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
 		break;
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
 		break;
-- 
2.7.4

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[PATCH 6/6] drm/amdkfd: Vega20 bring up on amdkfd side

[Felix Kuehling]

From: Shaoyun Liu <Shaoyun.Liu@amd.com>

Add Vega20 device IDs, device info and enable it in KFD.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c              |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_device.c            | 22 ++++++++++++++++++++++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c       |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c      |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c       |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c    |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c          |  1 +
 8 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index ee49960..e3ef7d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -642,6 +642,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 		num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
 		break;
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 		pcache_info = vega10_cache_info;
 		num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
 		break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 1327816..89eec81 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -236,6 +236,22 @@ static const struct kfd_device_info vega10_vf_device_info = {
 	.num_sdma_queues_per_engine = 2,
 };
 
+static const struct kfd_device_info vega20_device_info = {
+	.asic_family = CHIP_VEGA20,
+	.max_pasid_bits = 16,
+	.max_no_of_hqd	= 24,
+	.doorbell_size	= 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.supports_cwsr = true,
+	.needs_iommu_device = false,
+	.needs_pci_atomics = true,
+	.num_sdma_engines = 2,
+	.num_sdma_queues_per_engine = 8,
+};
+
 struct kfd_deviceid {
 	unsigned short did;
 	const struct kfd_device_info *device_info;
@@ -323,6 +339,12 @@ static const struct kfd_deviceid supported_devices[] = {
 	{ 0x6868, &vega10_device_info },	/* Vega10 */
 	{ 0x686C, &vega10_vf_device_info },	/* Vega10  vf*/
 	{ 0x687F, &vega10_device_info },	/* Vega10 */
+	{ 0x66a0, &vega20_device_info },	/* Vega20 */
+	{ 0x66a1, &vega20_device_info },	/* Vega20 */
+	{ 0x66a2, &vega20_device_info },	/* Vega20 */
+	{ 0x66a3, &vega20_device_info },	/* Vega20 */
+	{ 0x66a7, &vega20_device_info },	/* Vega20 */
+	{ 0x66af, &vega20_device_info }		/* Vega20 */
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index afa2167..d6af31c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1733,6 +1733,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
 		break;
 
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		device_queue_manager_init_v9(&dqm->asic_ops);
 		break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 97d5423..3d66cec 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -400,6 +400,7 @@ int kfd_init_apertures(struct kfd_process *process)
 				kfd_init_apertures_vi(pdd, id);
 				break;
 			case CHIP_VEGA10:
+			case CHIP_VEGA20:
 			case CHIP_RAVEN:
 				kfd_init_apertures_v9(pdd, id);
 				break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 9f84b4d..6c31f73 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -322,6 +322,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
 		break;
 
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		kernel_queue_init_v9(&kq->ops_asic_specific);
 		break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index 3bc25ab..e33019a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -39,6 +39,7 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
 	case CHIP_POLARIS11:
 		return mqd_manager_init_vi_tonga(type, dev);
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		return mqd_manager_init_v9(type, dev);
 	default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 1092631..c6080ed3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -229,6 +229,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 		pm->pmf = &kfd_vi_pm_funcs;
 		break;
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		pm->pmf = &kfd_v9_pm_funcs;
 		break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 02b12e4..a21d9e6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1274,6 +1274,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
 		break;
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 	case CHIP_RAVEN:
 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
-- 
2.7.4

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Re: [PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10

[Alex Deucher]

On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling <Felix.Kuehling@amd.com> wrote:
>
> From: Emily Deng <Emily.Deng@amd.com>
>
> Correct the format
>
> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
> same setting with host driver, or it will happen conflicts.
>
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  9 +++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++++++++++++++++++--------
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 12 +++++++++---
>  3 files changed, 37 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index afa9e77..e60de88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
>         AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
>         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
>
> +       /* For vega10 sriov, the sdma doorbell must be fixed as follow
> +        * to keep the same setting with host driver, or it will
> +        * happen conflicts
> +        */
> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
> +
>         /* Interrupt handler */
>         AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
>         AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index bf0b012..7a165a9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
>                          * process in case of 64-bit doorbells so we
>                          * can use each doorbell assignment twice.
>                          */
> -                       gpu_resources.sdma_doorbell[0][i] =
> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> -                       gpu_resources.sdma_doorbell[0][i+1] =
> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> -                       gpu_resources.sdma_doorbell[1][i] =
> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> -                       gpu_resources.sdma_doorbell[1][i+1] =
> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> +                       if (adev->asic_type == CHIP_VEGA10) {
> +                               gpu_resources.sdma_doorbell[0][i] =
> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[0][i+1] =
> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[1][i] =
> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[1][i+1] =
> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> +                       } else {
> +                               gpu_resources.sdma_doorbell[0][i] =
> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[0][i+1] =
> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[1][i] =
> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> +                               gpu_resources.sdma_doorbell[1][i+1] =
> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> +                       }

It would probably make more sense to reverse the conditions here so we
retain the old behavior for all previous non-vega20 asics rather than
just vega10.  E.g.,

if (vega20) {
// use new doorbell mapping
} else {
// use the old doorbell mapping
}

Same thing below.

Alex

>                 }
>                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
>                  * SDMA, IH and VCN. So don't use them for the CP.
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index df13840..6265361 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
>                 DRM_INFO("use_doorbell being set to: [%s]\n",
>                                 ring->use_doorbell?"true":"false");
>
> -               ring->doorbell_index = (i == 0) ?
> -                       (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> -                       : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> +               if (adev->asic_type == CHIP_VEGA10)
> +                       ring->doorbell_index = (i == 0) ?
> +                               (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> +                               : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> +               else
> +                       ring->doorbell_index = (i == 0) ?
> +                               (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> +                               : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> +
>
>                 sprintf(ring->name, "sdma%d", i);
>                 r = amdgpu_ring_init(adev, ring, 1024,
> --
> 2.7.4
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10

[Felix Kuehling]

On 2018-09-12 09:55 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling <Felix.Kuehling@amd.com> wrote:
>> From: Emily Deng <Emily.Deng@amd.com>
>>
>> Correct the format
>>
>> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
>> same setting with host driver, or it will happen conflicts.
>>
>> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
>> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  9 +++++++++
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++++++++++++++++++--------
>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 12 +++++++++---
>>  3 files changed, 37 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index afa9e77..e60de88 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
>>         AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
>>         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
>>
>> +       /* For vega10 sriov, the sdma doorbell must be fixed as follow
>> +        * to keep the same setting with host driver, or it will
>> +        * happen conflicts
>> +        */
>> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
>> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
>> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
>> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
>> +
>>         /* Interrupt handler */
>>         AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
>>         AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index bf0b012..7a165a9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
>>                          * process in case of 64-bit doorbells so we
>>                          * can use each doorbell assignment twice.
>>                          */
>> -                       gpu_resources.sdma_doorbell[0][i] =
>> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
>> -                       gpu_resources.sdma_doorbell[0][i+1] =
>> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
>> -                       gpu_resources.sdma_doorbell[1][i] =
>> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
>> -                       gpu_resources.sdma_doorbell[1][i+1] =
>> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
>> +                       if (adev->asic_type == CHIP_VEGA10) {
>> +                               gpu_resources.sdma_doorbell[0][i] =
>> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[0][i+1] =
>> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[1][i] =
>> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[1][i+1] =
>> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
>> +                       } else {
>> +                               gpu_resources.sdma_doorbell[0][i] =
>> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[0][i+1] =
>> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[1][i] =
>> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
>> +                               gpu_resources.sdma_doorbell[1][i+1] =
>> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
>> +                       }
> It would probably make more sense to reverse the conditions here so we
> retain the old behavior for all previous non-vega20 asics rather than
> just vega10.  E.g.,
>
> if (vega20) {
> // use new doorbell mapping
> } else {
> // use the old doorbell mapping
> }
>
> Same thing below.

This code is only applicable to GFXv9 and later GPUs with 64-bit
doorbells. It does not apply to GFXv8 and older GPUs anyway. The new
enum names AMDGPU_VEGA10_DOORBELL64_... also imply that we preserve the
old behaviour on Vega10 only. I think the assumption is that future GPUs
will also need bigger doorbell assignments.

Do any of the other GFXv9 GPUs support SRIOV? (Vega12, Raven, etc.)

Regards,
  Felix

>
> Alex
>
>>                 }
>>                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
>>                  * SDMA, IH and VCN. So don't use them for the CP.
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index df13840..6265361 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
>>                 DRM_INFO("use_doorbell being set to: [%s]\n",
>>                                 ring->use_doorbell?"true":"false");
>>
>> -               ring->doorbell_index = (i == 0) ?
>> -                       (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
>> -                       : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
>> +               if (adev->asic_type == CHIP_VEGA10)
>> +                       ring->doorbell_index = (i == 0) ?
>> +                               (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
>> +                               : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
>> +               else
>> +                       ring->doorbell_index = (i == 0) ?
>> +                               (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
>> +                               : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
>> +
>>
>>                 sprintf(ring->name, "sdma%d", i);
>>                 r = amdgpu_ring_init(adev, ring, 1024,
>> --
>> 2.7.4
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10

[Alex Deucher]

On Wed, Sep 12, 2018 at 10:06 PM Felix Kuehling <felix.kuehling@amd.com> wrote:
>
> On 2018-09-12 09:55 PM, Alex Deucher wrote:
> > On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> >> From: Emily Deng <Emily.Deng@amd.com>
> >>
> >> Correct the format
> >>
> >> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
> >> same setting with host driver, or it will happen conflicts.
> >>
> >> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> >> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> >> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> >> ---
> >>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  9 +++++++++
> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++++++++++++++++++--------
> >>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 12 +++++++++---
> >>  3 files changed, 37 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index afa9e77..e60de88 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
> >>         AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
> >>         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
> >>
> >> +       /* For vega10 sriov, the sdma doorbell must be fixed as follow
> >> +        * to keep the same setting with host driver, or it will
> >> +        * happen conflicts
> >> +        */
> >> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
> >> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
> >> +       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
> >> +       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
> >> +
> >>         /* Interrupt handler */
> >>         AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
> >>         AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> index bf0b012..7a165a9 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> >> @@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> >>                          * process in case of 64-bit doorbells so we
> >>                          * can use each doorbell assignment twice.
> >>                          */
> >> -                       gpu_resources.sdma_doorbell[0][i] =
> >> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> >> -                       gpu_resources.sdma_doorbell[0][i+1] =
> >> -                               AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> >> -                       gpu_resources.sdma_doorbell[1][i] =
> >> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> >> -                       gpu_resources.sdma_doorbell[1][i+1] =
> >> -                               AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> >> +                       if (adev->asic_type == CHIP_VEGA10) {
> >> +                               gpu_resources.sdma_doorbell[0][i] =
> >> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[0][i+1] =
> >> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[1][i] =
> >> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[1][i+1] =
> >> +                                       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> >> +                       } else {
> >> +                               gpu_resources.sdma_doorbell[0][i] =
> >> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[0][i+1] =
> >> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[1][i] =
> >> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> >> +                               gpu_resources.sdma_doorbell[1][i+1] =
> >> +                                       AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
> >> +                       }
> > It would probably make more sense to reverse the conditions here so we
> > retain the old behavior for all previous non-vega20 asics rather than
> > just vega10.  E.g.,
> >
> > if (vega20) {
> > // use new doorbell mapping
> > } else {
> > // use the old doorbell mapping
> > }
> >
> > Same thing below.
>
> This code is only applicable to GFXv9 and later GPUs with 64-bit
> doorbells. It does not apply to GFXv8 and older GPUs anyway. The new
> enum names AMDGPU_VEGA10_DOORBELL64_... also imply that we preserve the
> old behaviour on Vega10 only. I think the assumption is that future GPUs
> will also need bigger doorbell assignments.
>
> Do any of the other GFXv9 GPUs support SRIOV? (Vega12, Raven, etc.)

Not at the moment, but if we do end up doing so, we'll need to
remember to change the code.  Not a big deal either way, just thought
it was worth mentioning.

Alex

>
> Regards,
>   Felix
>
> >
> > Alex
> >
> >>                 }
> >>                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
> >>                  * SDMA, IH and VCN. So don't use them for the CP.
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> index df13840..6265361 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> @@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
> >>                 DRM_INFO("use_doorbell being set to: [%s]\n",
> >>                                 ring->use_doorbell?"true":"false");
> >>
> >> -               ring->doorbell_index = (i == 0) ?
> >> -                       (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> >> -                       : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> >> +               if (adev->asic_type == CHIP_VEGA10)
> >> +                       ring->doorbell_index = (i == 0) ?
> >> +                               (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> >> +                               : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> >> +               else
> >> +                       ring->doorbell_index = (i == 0) ?
> >> +                               (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
> >> +                               : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
> >> +
> >>
> >>                 sprintf(ring->name, "sdma%d", i);
> >>                 r = amdgpu_ring_init(adev, ring, 1024,
> >> --
> >> 2.7.4
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 0/6] Initial Vega20 support for KFD

[Alex Deucher]

On Wed, Sep 12, 2018 at 9:44 PM Felix Kuehling <Felix.Kuehling@amd.com> wrote:
>
> This patch series is based on amd-staging-drm-next + the patch series
> "KFD upstreaming September 2018".
>
> Emily Deng (1):
>   drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of
>     Vega10
>
> Shaoyun Liu (5):
>   drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
>   drm/amdkfd: Make the number of SDMA queues variable
>   drm/amd: Interface change to support 64 bit page_table_base
>   drm/amdgpu: Add vega20 support on kfd probe
>   drm/amdkfd: Vega20 bring up on amdkfd side
>

Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>

>  drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 23 +++++++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c         | 50 +++++++++++++++-------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h         |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  7 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  |  7 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c  |  7 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |  8 +++-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c             | 12 ++++--
>  drivers/gpu/drm/amd/amdkfd/kfd_crat.c              |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_device.c            | 33 ++++++++++++++
>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 18 +++++---
>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  1 -
>  drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c       |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c      |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c   |  3 +-
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c       |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c    |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |  3 +-
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.c          |  1 +
>  drivers/gpu/drm/amd/include/kgd_kfd_interface.h    | 10 ++---
>  20 files changed, 136 insertions(+), 54 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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