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* [PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h
@ 2018-09-17 12:28 Hawking Zhang
       [not found] ` <1537187320-15058-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 3+ messages in thread
From: Hawking Zhang @ 2018-09-17 12:28 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang

atomfirmware has structure changes in varm_info. Updated it
to the latest one.

Change-Id: Ie5d60413e5db1dfb4aaf23dc94bc5fd4ed0a01cd
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c |  2 +-
 drivers/gpu/drm/amd/include/atomfirmware.h       | 20 +++++++++++---------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 2369158..5461d0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -174,7 +174,7 @@ static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
 		case ATOM_DGPU_VRAM_TYPE_GDDR5:
 			vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 			break;
-		case ATOM_DGPU_VRAM_TYPE_HBM:
+		case ATOM_DGPU_VRAM_TYPE_HBM2:
 			vram_type = AMDGPU_VRAM_TYPE_HBM;
 			break;
 		default:
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 6109a45..8ae7adb 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -179,7 +179,7 @@ enum atom_voltage_type
 
 enum atom_dgpu_vram_type{
   ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
-  ATOM_DGPU_VRAM_TYPE_HBM   = 0x60,
+  ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
 };
 
 enum atom_dp_vs_preemph_def{
@@ -1699,10 +1699,10 @@ struct atom_vram_module_v9
 {
   // Design Specific Values
   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
-  uint32_t  channel_enable;                // for 32 channel ASIC usage
-  uint32_t  umcch_addrcfg;
-  uint32_t  umcch_addrsel;
-  uint32_t  umcch_colsel;
+  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
+  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
+  uint16_t  reserved[3];
+  uint16_t  mem_voltage;                   // mem_voltage
   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
   uint8_t   ext_memory_id;                 // Current memory module ID
   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
@@ -1712,20 +1712,22 @@ struct atom_vram_module_v9
   uint8_t   tunningset_id;                 // MC phy registers set per. 
   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
-  uint16_t  vram_rsd2;                     // reserved
+  uint8_t   hbm_ven_rev_id;				   // hbm_ven_rev_id
+  uint8_t   vram_rsd2;					   // reserved
   char    dram_pnstring[20];               // part number end with '0'. 
 };
 
-
 struct atom_vram_info_header_v2_3
 {
-  struct   atom_common_table_header  table_header;
+  struct   atom_common_table_header table_header;
   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
   uint16_t dram_data_remap_tbloffset;                    // reserved for now
-  uint16_t vram_rsd2[3];
+  uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
+  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
+  uint16_t vram_rsd2;
   uint8_t  vram_module_num;                              // indicate number of VRAM module
   uint8_t  vram_rsd1[2];
   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/amdgpu: fix unknown vram mem type for vega20
       [not found] ` <1537187320-15058-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-17 12:28   ` Hawking Zhang
  2018-09-18  3:22   ` [PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h Huang Rui
  1 sibling, 0 replies; 3+ messages in thread
From: Hawking Zhang @ 2018-09-17 12:28 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang

vega20 should use umc_info v3_3 instead of v3_1. There are
serveral versions of umc_info for vega series. Compared to
various versions of these structures, vram_info strucure is
unified for vega series. The patch switch to query mem_type
from vram_info structure for all the vega series dGPU.

Change-Id: If8d22b687ec5d0f4445527e69841df83479cc485
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 5461d0d..b61e1dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -117,6 +117,10 @@ union igp_info {
 union umc_info {
 	struct atom_umc_info_v3_1 v31;
 };
+
+union vram_info {
+	struct atom_vram_info_header_v2_3 v23;
+};
 /*
  * Return vram width from integrated system info table, if available,
  * or 0 if not.
@@ -195,7 +199,7 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
 	int index;
 	u16 data_offset, size;
 	union igp_info *igp_info;
-	union umc_info *umc_info;
+	union vram_info *vram_info;
 	u8 frev, crev;
 	u8 mem_type;
 
@@ -204,7 +208,7 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
 						    integratedsysteminfo);
 	else
 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
-						    umc_info);
+						    vram_info);
 	if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 					  index, &size,
 					  &frev, &crev, &data_offset)) {
@@ -219,11 +223,11 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
 				return 0;
 			}
 		} else {
-			umc_info = (union umc_info *)
+			vram_info = (union vram_info *)
 				(mode_info->atom_context->bios + data_offset);
 			switch (crev) {
-			case 1:
-				mem_type = umc_info->v31.vram_type;
+			case 3:
+				mem_type = vram_info->v23.vram_module[0].memory_type;
 				return convert_atom_mem_type_to_vram_type(adev, mem_type);
 			default:
 				return 0;
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h
       [not found] ` <1537187320-15058-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
  2018-09-17 12:28   ` [PATCH 2/2] drm/amdgpu: fix unknown vram mem type for vega20 Hawking Zhang
@ 2018-09-18  3:22   ` Huang Rui
  1 sibling, 0 replies; 3+ messages in thread
From: Huang Rui @ 2018-09-18  3:22 UTC (permalink / raw)
  To: Hawking Zhang; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

On Mon, Sep 17, 2018 at 08:28:39PM +0800, Hawking Zhang wrote:
> atomfirmware has structure changes in varm_info. Updated it
> to the latest one.
> 
> Change-Id: Ie5d60413e5db1dfb4aaf23dc94bc5fd4ed0a01cd
> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Series are Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c |  2 +-
>  drivers/gpu/drm/amd/include/atomfirmware.h       | 20 +++++++++++---------
>  2 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> index 2369158..5461d0d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> @@ -174,7 +174,7 @@ static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
>  		case ATOM_DGPU_VRAM_TYPE_GDDR5:
>  			vram_type = AMDGPU_VRAM_TYPE_GDDR5;
>  			break;
> -		case ATOM_DGPU_VRAM_TYPE_HBM:
> +		case ATOM_DGPU_VRAM_TYPE_HBM2:
>  			vram_type = AMDGPU_VRAM_TYPE_HBM;
>  			break;
>  		default:
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 6109a45..8ae7adb 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -179,7 +179,7 @@ enum atom_voltage_type
>  
>  enum atom_dgpu_vram_type{
>    ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
> -  ATOM_DGPU_VRAM_TYPE_HBM   = 0x60,
> +  ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
>  };
>  
>  enum atom_dp_vs_preemph_def{
> @@ -1699,10 +1699,10 @@ struct atom_vram_module_v9
>  {
>    // Design Specific Values
>    uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
> -  uint32_t  channel_enable;                // for 32 channel ASIC usage
> -  uint32_t  umcch_addrcfg;
> -  uint32_t  umcch_addrsel;
> -  uint32_t  umcch_colsel;
> +  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
> +  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
> +  uint16_t  reserved[3];
> +  uint16_t  mem_voltage;                   // mem_voltage
>    uint16_t  vram_module_size;              // Size of atom_vram_module_v9
>    uint8_t   ext_memory_id;                 // Current memory module ID
>    uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
> @@ -1712,20 +1712,22 @@ struct atom_vram_module_v9
>    uint8_t   tunningset_id;                 // MC phy registers set per. 
>    uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
>    uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
> -  uint16_t  vram_rsd2;                     // reserved
> +  uint8_t   hbm_ven_rev_id;				   // hbm_ven_rev_id
> +  uint8_t   vram_rsd2;					   // reserved
>    char    dram_pnstring[20];               // part number end with '0'. 
>  };
>  
> -
>  struct atom_vram_info_header_v2_3
>  {
> -  struct   atom_common_table_header  table_header;
> +  struct   atom_common_table_header table_header;
>    uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
>    uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
>    uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
>    uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
>    uint16_t dram_data_remap_tbloffset;                    // reserved for now
> -  uint16_t vram_rsd2[3];
> +  uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
> +  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
> +  uint16_t vram_rsd2;
>    uint8_t  vram_module_num;                              // indicate number of VRAM module
>    uint8_t  vram_rsd1[2];
>    uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
> -- 
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-09-18  3:22 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2018-09-17 12:28 [PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h Hawking Zhang
     [not found] ` <1537187320-15058-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-09-17 12:28   ` [PATCH 2/2] drm/amdgpu: fix unknown vram mem type for vega20 Hawking Zhang
2018-09-18  3:22   ` [PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h Huang Rui

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