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From: James Zhu <jzhums-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: james.zhu-5C7GfCeVMHo@public.gmane.org
Subject: [PATCH 1/8] drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test
Date: Tue, 25 Sep 2018 15:55:16 -0400	[thread overview]
Message-ID: <1537905323-27071-1-git-send-email-James.Zhu@amd.com> (raw)

Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers
can't be directly accessed under DPG(Dynamic Power Gate) mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index a73674f..27262a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -264,7 +264,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 	unsigned i;
 	int r;
 
-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
 	r = amdgpu_ring_alloc(ring, 3);
 	if (r) {
 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -272,11 +272,11 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 		return r;
 	}
 	amdgpu_ring_write(ring,
-		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));
 	amdgpu_ring_write(ring, 0xDEADBEEF);
 	amdgpu_ring_commit(ring);
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 		if (tmp == 0xDEADBEEF)
 			break;
 		DRM_UDELAY(1);
@@ -616,7 +616,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 	unsigned i;
 	int r;
 
-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
 	r = amdgpu_ring_alloc(ring, 3);
 
 	if (r) {
@@ -626,12 +626,12 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 	}
 
 	amdgpu_ring_write(ring,
-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
+		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));
 	amdgpu_ring_write(ring, 0xDEADBEEF);
 	amdgpu_ring_commit(ring);
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 		if (tmp == 0xDEADBEEF)
 			break;
 		DRM_UDELAY(1);
@@ -665,7 +665,7 @@ static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 
 	ib = &job->ibs[0];
 
-	ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, PACKETJ_TYPE0);
+	ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);
 	ib->ptr[1] = 0xDEADBEEF;
 	for (i = 2; i < 16; i += 2) {
 		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
@@ -714,7 +714,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 		r = 0;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
+		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 		if (tmp == 0xDEADBEEF)
 			break;
 		DRM_UDELAY(1);
-- 
2.7.4

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             reply	other threads:[~2018-09-25 19:55 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-25 19:55 James Zhu [this message]
     [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 19:55   ` [PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode James Zhu
2018-09-25 19:55   ` [PATCH 3/8] drm/amdgpu:Add DPG support flag James Zhu
     [not found]     ` <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:06       ` Alex Deucher
2018-09-26  8:02       ` Christian König
     [not found]         ` <44a25354-4329-c942-8f86-0528a0b2ce84-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-09-26 12:55           ` James Zhu
2018-09-25 19:55   ` [PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro James Zhu
2018-09-25 19:55   ` [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 James Zhu
     [not found]     ` <1537905323-27071-5-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:09       ` Alex Deucher
2018-09-25 19:55   ` [PATCH 6/8] drm/amdgpu:Add DPG pause state James Zhu
2018-09-25 19:55   ` [PATCH 7/8] drm/amdgpu:Add DPG pause mode support James Zhu
     [not found]     ` <1537905323-27071-7-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:12       ` Alex Deucher
2018-09-25 19:55   ` [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO James Zhu
     [not found]     ` <1537905323-27071-8-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:15       ` Alex Deucher
     [not found]         ` <CADnq5_O22AkJy3tT1ba5pUEPo5LsQuh992V7kizFgh6noS93uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-25 23:02           ` James Zhu

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