* [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl
@ 2018-09-26 12:50 Rex Zhu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
SDMA IP can be power up/down via smu message
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 53d3337..aff7c14 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1214,6 +1214,21 @@ static void pp_dpm_powergate_acp(void *handle, bool gate)
hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
}
+static void pp_dpm_powergate_sdma(void *handle, bool gate)
+{
+ struct pp_hwmgr *hwmgr = handle;
+
+ if (!hwmgr)
+ return;
+
+ if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return;
+ }
+
+ hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
+}
+
static int pp_set_powergating_by_smu(void *handle,
uint32_t block_type, bool gate)
{
@@ -1236,6 +1251,9 @@ static int pp_set_powergating_by_smu(void *handle,
case AMD_IP_BLOCK_TYPE_ACP:
pp_dpm_powergate_acp(handle, gate);
break;
+ case AMD_IP_BLOCK_TYPE_SDMA:
+ pp_dpm_powergate_sdma(handle, gate);
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 5d1dae2..b7a9d0c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1153,6 +1153,14 @@ static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
}
+static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
+{
+ if (gate)
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);
+ else
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);
+}
+
static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
{
if (bgate) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index a6d9212..d1183b1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -328,6 +328,7 @@ struct pp_hwmgr_func {
int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
+ int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
};
struct pp_table_func {
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/7] drm/amdgpu: Move out power up/down sdma out of smu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 12:50 ` Rex Zhu
[not found] ` <1537966249-30259-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 3/7] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu Rex Zhu
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 15 ---------------
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 12e577c..c20d413 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1364,6 +1364,9 @@ static int sdma_v4_0_hw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+
sdma_v4_0_init_golden_registers(adev);
r = sdma_v4_0_start(adev);
@@ -1381,6 +1384,9 @@ static int sdma_v4_0_hw_fini(void *handle)
sdma_v4_0_ctx_switch_enable(adev, false);
sdma_v4_0_enable(adev, false);
+ if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index b7a9d0c..dd18cb7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1216,6 +1216,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
.smus_notify_pwe = smu10_smus_notify_pwe,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
+ .powergate_sdma = smu10_powergate_sdma,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index 6f961de..d78d864 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -186,19 +186,6 @@ static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
return 0;
}
-/* sdma is disabled by default in vbios, need to re-enable in driver */
-static void smu10_smc_enable_sdma(struct pp_hwmgr *hwmgr)
-{
- smu10_send_msg_to_smc(hwmgr,
- PPSMC_MSG_PowerUpSdma);
-}
-
-static void smu10_smc_disable_sdma(struct pp_hwmgr *hwmgr)
-{
- smu10_send_msg_to_smc(hwmgr,
- PPSMC_MSG_PowerDownSdma);
-}
-
/* vcn is disabled by default in vbios, need to re-enable in driver */
static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
{
@@ -218,7 +205,6 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
(struct smu10_smumgr *)(hwmgr->smu_backend);
if (priv) {
- smu10_smc_disable_sdma(hwmgr);
smu10_smc_disable_vcn(hwmgr);
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
@@ -243,7 +229,6 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr)
if (smu10_verify_smc_interface(hwmgr))
return -EINVAL;
- smu10_smc_enable_sdma(hwmgr);
smu10_smc_enable_vcn(hwmgr);
return 0;
}
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/7] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 2/7] drm/amdgpu: Move out power up/down sdma out of smu Rex Zhu
@ 2018-09-26 12:50 ` Rex Zhu
[not found] ` <1537966249-30259-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu Rex Zhu
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
the vcn power will be controlled by VCN.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index d78d864..d0eb8ab 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -186,26 +186,12 @@ static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
return 0;
}
-/* vcn is disabled by default in vbios, need to re-enable in driver */
-static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
-{
- smu10_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_PowerUpVcn, 0);
-}
-
-static void smu10_smc_disable_vcn(struct pp_hwmgr *hwmgr)
-{
- smu10_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_PowerDownVcn, 0);
-}
-
static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
{
struct smu10_smumgr *priv =
(struct smu10_smumgr *)(hwmgr->smu_backend);
if (priv) {
- smu10_smc_disable_vcn(hwmgr);
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
&priv->smu_tables.entry[SMU10_WMTABLE].table);
@@ -229,7 +215,7 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr)
if (smu10_verify_smc_interface(hwmgr))
return -EINVAL;
- smu10_smc_enable_vcn(hwmgr);
+
return 0;
}
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 2/7] drm/amdgpu: Move out power up/down sdma out of smu Rex Zhu
2018-09-26 12:50 ` [PATCH 3/7] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu Rex Zhu
@ 2018-09-26 12:50 ` Rex Zhu
[not found] ` <1537966249-30259-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 5/7] drm/amd/pp: Remove useless code in smu Rex Zhu
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
HW CG feature will be enabled after hw ip initialized
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index ec14798..b6b62a7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
hwmgr->avfs_supported = false;
}
- /* To initialize all clock gating before RLC loaded and running.*/
- amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
- AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
- amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
- AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
- amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
- AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
- amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
- AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
-
/* Setup SoftRegsStart here for register lookup in case
* DummyBackEnd is used and ProcessFirmwareHeader is not executed
*/
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/7] drm/amd/pp: Remove useless code in smu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-09-26 12:50 ` [PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu Rex Zhu
@ 2018-09-26 12:50 ` Rex Zhu
[not found] ` <1537966249-30259-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 6/7] drm/amd/pp: Export load_firmware interface Rex Zhu
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 5 -----
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 -----
4 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 7500a3e..7844256 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -89,7 +89,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
hwmgr_init_default_caps(hwmgr);
hwmgr_set_user_specify_caps(hwmgr);
hwmgr->fan_ctrl_is_in_default_mode = true;
- hwmgr->reload_fw = 1;
hwmgr_init_workload_prority(hwmgr);
switch (hwmgr->chip_family) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d1183b1..b691fca 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -733,7 +733,6 @@ struct pp_hwmgr {
void *smu_backend;
const struct pp_smumgr_func *smumgr_funcs;
bool is_kicker;
- bool reload_fw;
enum PP_DAL_POWERLEVEL dal_power_level;
struct phm_dynamic_state_info dyn_state;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 186dafc..10eb967 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -381,11 +381,6 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
uint32_t fw_to_load;
int r = 0;
- if (!hwmgr->reload_fw) {
- pr_info("skip reloading...\n");
- return 0;
- }
-
if (smu_data->soft_regs_start)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index a74c5be..7a4c425 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -659,11 +659,6 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
uint32_t smc_address;
- if (!hwmgr->reload_fw) {
- pr_info("skip reloading...\n");
- return 0;
- }
-
smu8_smu_populate_firmware_entries(hwmgr);
smu8_smu_construct_toc(hwmgr);
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/7] drm/amd/pp: Export load_firmware interface
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-09-26 12:50 ` [PATCH 5/7] drm/amd/pp: Remove useless code in smu Rex Zhu
@ 2018-09-26 12:50 ` Rex Zhu
[not found] ` <1537966249-30259-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 7/7] drm/amdgpu: Change the gfx/sdma init/fini sequence Rex Zhu
2018-09-26 14:13 ` [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl Alex Deucher
6 siblings, 1 reply; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Export this interface for the AMDGPU_FW_LOAD_SMU type.
gfx/sdma can request smu to load firmware.
Split the smu7/8_start_smu function into two functions
1. start_smu, used for load smu firmware in smu7/8 and
check smu firmware version.
2. request_smu_load_fw, used for load other ip's firmware
on smu7/8 and add firmware loading staus check.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++--
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 4 +-
.../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 25 ++++-----
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 +-
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 59 +++++-----------------
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 3 +-
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 46 ++++++++---------
.../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 12 ++++-
.../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 +-
10 files changed, 79 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2aeef2b..f020f6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4216,10 +4216,17 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
/* legacy rlc firmware loading */
r = gfx_v8_0_rlc_load_microcode(adev);
- if (r)
- return r;
+ } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU && adev->powerplay.pp_funcs->load_firmware) {
+ amdgpu_ucode_init_bo(adev);
+ r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ } else {
+ r = -EINVAL;
}
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
gfx_v8_0_rlc_start(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index aff7c14..3bc825c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -124,9 +124,6 @@ static int pp_hw_init(void *handle)
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_init_bo(adev);
-
ret = hwmgr_hw_init(hwmgr);
if (ret)
@@ -275,7 +272,16 @@ static int pp_set_clockgating_state(void *handle,
static int pp_dpm_load_fw(void *handle)
{
- return 0;
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
+
+ if (!hwmgr || !hwmgr->smumgr_funcs)
+ return -EINVAL;
+
+ if (hwmgr->smumgr_funcs->request_smu_load_fw)
+ ret = hwmgr->smumgr_funcs->request_smu_load_fw(hwmgr);
+
+ return ret;
}
static int pp_dpm_fw_loading_complete(void *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index b6b62a7..ffd7d78 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -310,8 +310,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
offsetof(SMU73_Firmware_Header, SoftRegisters),
&(priv->smu7_data.soft_regs_start), 0x40000);
- result = smu7_request_smu_load_fw(hwmgr);
-
return result;
}
@@ -2643,7 +2641,7 @@ static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
.smu_fini = &smu7_smu_fini,
.start_smu = &fiji_start_smu,
.check_fw_load_finish = &smu7_check_fw_load_finish,
- .request_smu_load_fw = &smu7_reload_firmware,
+ .request_smu_load_fw = &smu7_request_smu_load_fw,
.request_smu_load_specific_fw = NULL,
.send_msg_to_smc = &smu7_send_msg_to_smc,
.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 73aa368..68a4836 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -232,27 +232,24 @@ static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{
- int result;
-
- result = iceland_smu_upload_firmware_image(hwmgr);
- if (result)
- return result;
- result = iceland_smu_start_smc(hwmgr);
- if (result)
- return result;
+ struct iceland_smumgr *priv = hwmgr->smu_backend;
+ int result = 0;
if (!smu7_is_smc_ram_running(hwmgr)) {
- pr_info("smu not running, upload firmware again \n");
result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
- result = iceland_smu_start_smc(hwmgr);
- if (result)
- return result;
+ iceland_smu_start_smc(hwmgr);
}
+ /* Setup SoftRegsStart here for register lookup in case
+ * DummyBackEnd is used and ProcessFirmwareHeader is not executed
+ */
- result = smu7_request_smu_load_fw(hwmgr);
+ smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, SoftRegisters),
+ &(priv->smu7_data.soft_regs_start), 0x40000);
return result;
}
@@ -2662,7 +2659,7 @@ static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
.smu_fini = &smu7_smu_fini,
.start_smu = &iceland_start_smu,
.check_fw_load_finish = &smu7_check_fw_load_finish,
- .request_smu_load_fw = &smu7_reload_firmware,
+ .request_smu_load_fw = &smu7_request_smu_load_fw,
.request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
.send_msg_to_smc = &smu7_send_msg_to_smc,
.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 872d382..2ad6ad9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -313,8 +313,6 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
&(smu_data->smu7_data.soft_regs_start), 0x40000);
- result = smu7_request_smu_load_fw(hwmgr);
-
return result;
}
@@ -2478,7 +2476,7 @@ static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
.smu_fini = smu7_smu_fini,
.start_smu = polaris10_start_smu,
.check_fw_load_finish = smu7_check_fw_load_finish,
- .request_smu_load_fw = smu7_reload_firmware,
+ .request_smu_load_fw = smu7_request_smu_load_fw,
.request_smu_load_specific_fw = NULL,
.send_msg_to_smc = smu7_send_msg_to_smc,
.send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 10eb967..edfb061 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_
return 0;
}
-/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
-
-static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
-{
- uint32_t result = 0;
-
- switch (fw_type) {
- case UCODE_ID_SDMA0:
- result = UCODE_ID_SDMA0_MASK;
- break;
- case UCODE_ID_SDMA1:
- result = UCODE_ID_SDMA1_MASK;
- break;
- case UCODE_ID_CP_CE:
- result = UCODE_ID_CP_CE_MASK;
- break;
- case UCODE_ID_CP_PFP:
- result = UCODE_ID_CP_PFP_MASK;
- break;
- case UCODE_ID_CP_ME:
- result = UCODE_ID_CP_ME_MASK;
- break;
- case UCODE_ID_CP_MEC:
- case UCODE_ID_CP_MEC_JT1:
- case UCODE_ID_CP_MEC_JT2:
- result = UCODE_ID_CP_MEC_MASK;
- break;
- case UCODE_ID_RLC_G:
- result = UCODE_ID_RLC_G_MASK;
- break;
- default:
- pr_info("UCode type is out of range! \n");
- result = 0;
- }
-
- return result;
-}
-
static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
uint32_t fw_type,
struct SMU_Entry *entry)
@@ -381,6 +343,11 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
uint32_t fw_to_load;
int r = 0;
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
+ pr_err("smu not running \n");
+ return -EINVAL;
+ }
+
if (smu_data->soft_regs_start)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
@@ -462,10 +429,13 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
- if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
- pr_err("Fail to Request SMU Load uCode");
+ smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load);
- return r;
+ r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
+ if (!r)
+ return 0;
+
+ pr_err("SMU load firmware failed\n");
failed:
kfree(smu_data->toc);
@@ -477,20 +447,15 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
{
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
uint32_t ret;
ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus),
- fw_mask, fw_mask);
+ fw_type, fw_type);
return ret;
}
-int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
-{
- return hwmgr->smumgr_funcs->start_smu(hwmgr);
-}
static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
{
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
index 01f0538f..10c8ceb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
@@ -73,9 +73,8 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t value, uint32_t limit);
-int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
-int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
+int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
int smu7_init(struct pp_hwmgr *hwmgr);
int smu7_smu_fini(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index 7a4c425..90f5f30 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -658,6 +658,8 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
uint32_t smc_address;
+ uint32_t fw_to_check = 0;
+ int ret;
smu8_smu_populate_firmware_entries(hwmgr);
@@ -684,28 +686,9 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
smu8_smu->toc_entry_power_profiling_index);
- return smu8_send_msg_to_smc_with_parameter(hwmgr,
+ smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob,
smu8_smu->toc_entry_initialize_index);
-}
-
-static int smu8_start_smu(struct pp_hwmgr *hwmgr)
-{
- int ret = 0;
- uint32_t fw_to_check = 0;
- struct amdgpu_device *adev = hwmgr->adev;
-
- uint32_t index = SMN_MP1_SRAM_START_ADDR +
- SMU8_FIRMWARE_HEADER_LOCATION +
- offsetof(struct SMU8_Firmware_Header, Version);
-
-
- if (hwmgr == NULL || hwmgr->device == NULL)
- return -EINVAL;
-
- cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
- hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
- adev->pm.fw_version = hwmgr->smu_version >> 8;
fw_to_check = UCODE_ID_RLC_G_MASK |
UCODE_ID_SDMA0_MASK |
@@ -719,8 +702,6 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
if (hwmgr->chip_id == CHIP_STONEY)
fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
- smu8_request_smu_load_fw(hwmgr);
-
ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
if (ret) {
pr_err("SMU firmware load failed\n");
@@ -734,6 +715,25 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
return ret;
}
+static int smu8_start_smu(struct pp_hwmgr *hwmgr)
+{
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ uint32_t index = SMN_MP1_SRAM_START_ADDR +
+ SMU8_FIRMWARE_HEADER_LOCATION +
+ offsetof(struct SMU8_Firmware_Header, Version);
+
+
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
+ hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
+ adev->pm.fw_version = hwmgr->smu_version >> 8;
+
+ return 0;
+}
+
static int smu8_smu_init(struct pp_hwmgr *hwmgr)
{
int ret = 0;
@@ -876,7 +876,7 @@ static bool smu8_is_dpm_running(struct pp_hwmgr *hwmgr)
.smu_fini = smu8_smu_fini,
.start_smu = smu8_start_smu,
.check_fw_load_finish = smu8_check_fw_load_finish,
- .request_smu_load_fw = NULL,
+ .request_smu_load_fw = smu8_request_smu_load_fw,
.request_smu_load_specific_fw = NULL,
.get_argument = smu8_get_argument,
.send_msg_to_smc = smu8_send_msg_to_smc,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index ae8378e..d8f1ca2 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -192,7 +192,8 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
static int tonga_start_smu(struct pp_hwmgr *hwmgr)
{
- int result;
+ struct tonga_smumgr *priv = hwmgr->smu_backend;
+ int result = 0;
/* Only start SMC if SMC RAM is not running */
if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
@@ -209,7 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
}
}
- result = smu7_request_smu_load_fw(hwmgr);
+ /* Setup SoftRegsStart here for register lookup in case
+ * DummyBackEnd is used and ProcessFirmwareHeader is not executed
+ */
+
+ smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, SoftRegisters),
+ &(priv->smu7_data.soft_regs_start), 0x40000);
return result;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
index 3d415fa..71e376f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
@@ -218,8 +218,6 @@ static int vegam_start_smu(struct pp_hwmgr *hwmgr)
&(smu_data->smu7_data.soft_regs_start),
0x40000);
- result = smu7_request_smu_load_fw(hwmgr);
-
return result;
}
@@ -2280,7 +2278,7 @@ static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
.smu_fini = smu7_smu_fini,
.start_smu = vegam_start_smu,
.check_fw_load_finish = smu7_check_fw_load_finish,
- .request_smu_load_fw = smu7_reload_firmware,
+ .request_smu_load_fw = smu7_request_smu_load_fw,
.request_smu_load_specific_fw = NULL,
.send_msg_to_smc = smu7_send_msg_to_smc,
.send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/7] drm/amdgpu: Change the gfx/sdma init/fini sequence
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-09-26 12:50 ` [PATCH 6/7] drm/amd/pp: Export load_firmware interface Rex Zhu
@ 2018-09-26 12:50 ` Rex Zhu
2018-09-26 14:13 ` [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl Alex Deucher
6 siblings, 0 replies; 16+ messages in thread
From: Rex Zhu @ 2018-09-26 12:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
initialize gfx/sdma before dpm features enabled.
and disable dpm features before gfx/sdma fini.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 17 +++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 13 +++++++------
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vi.c | 24 ++++++++++++------------
4 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 78ab939..f41f5f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2002,6 +2002,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
else
@@ -2014,8 +2016,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
- amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
@@ -2023,6 +2023,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
else
@@ -2035,8 +2037,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
- amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
@@ -2044,6 +2044,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -2053,8 +2055,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
- amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+
amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
@@ -2063,6 +2064,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -2072,8 +2075,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
- amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c364ef9..f8408f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2057,13 +2057,13 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
/* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
@@ -2071,13 +2071,14 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
+
/* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
@@ -2085,11 +2086,11 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
break;
default:
BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 138c481..a741913 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -529,6 +529,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
else
amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
@@ -539,8 +541,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
@@ -551,6 +551,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -560,8 +562,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 88b57a5..2727119 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1596,16 +1596,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
break;
case CHIP_FIJI:
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -1615,8 +1617,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
@@ -1626,6 +1626,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -1635,8 +1637,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
@@ -1649,6 +1649,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -1658,8 +1660,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
break;
@@ -1667,6 +1667,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -1676,8 +1678,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
#if defined(CONFIG_DRM_AMD_ACP)
@@ -1688,6 +1688,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -1697,8 +1699,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
#if defined(CONFIG_DRM_AMD_ACP)
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 5/7] drm/amd/pp: Remove useless code in smu
[not found] ` <1537966249-30259-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 14:07 ` Alex Deucher
0 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:07 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Please describe why the code is useless and can be removed.
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 -
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 5 -----
> drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 -----
> 4 files changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 7500a3e..7844256 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -89,7 +89,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> hwmgr_init_default_caps(hwmgr);
> hwmgr_set_user_specify_caps(hwmgr);
> hwmgr->fan_ctrl_is_in_default_mode = true;
> - hwmgr->reload_fw = 1;
> hwmgr_init_workload_prority(hwmgr);
>
> switch (hwmgr->chip_family) {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index d1183b1..b691fca 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -733,7 +733,6 @@ struct pp_hwmgr {
> void *smu_backend;
> const struct pp_smumgr_func *smumgr_funcs;
> bool is_kicker;
> - bool reload_fw;
>
> enum PP_DAL_POWERLEVEL dal_power_level;
> struct phm_dynamic_state_info dyn_state;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 186dafc..10eb967 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -381,11 +381,6 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> uint32_t fw_to_load;
> int r = 0;
>
> - if (!hwmgr->reload_fw) {
> - pr_info("skip reloading...\n");
> - return 0;
> - }
> -
> if (smu_data->soft_regs_start)
> cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> index a74c5be..7a4c425 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> @@ -659,11 +659,6 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
> uint32_t smc_address;
>
> - if (!hwmgr->reload_fw) {
> - pr_info("skip reloading...\n");
> - return 0;
> - }
> -
> smu8_smu_populate_firmware_entries(hwmgr);
>
> smu8_smu_construct_toc(hwmgr);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2018-09-26 12:50 ` [PATCH 7/7] drm/amdgpu: Change the gfx/sdma init/fini sequence Rex Zhu
@ 2018-09-26 14:13 ` Alex Deucher
6 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:13 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:51 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> SDMA IP can be power up/down via smu message
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 8 ++++++++
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> 3 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 53d3337..aff7c14 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1214,6 +1214,21 @@ static void pp_dpm_powergate_acp(void *handle, bool gate)
> hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
> }
>
> +static void pp_dpm_powergate_sdma(void *handle, bool gate)
> +{
> + struct pp_hwmgr *hwmgr = handle;
> +
> + if (!hwmgr)
> + return;
> +
> + if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
> + pr_info("%s was not implemented.\n", __func__);
> + return;
> + }
> +
> + hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
> +}
> +
> static int pp_set_powergating_by_smu(void *handle,
> uint32_t block_type, bool gate)
> {
> @@ -1236,6 +1251,9 @@ static int pp_set_powergating_by_smu(void *handle,
> case AMD_IP_BLOCK_TYPE_ACP:
> pp_dpm_powergate_acp(handle, gate);
> break;
> + case AMD_IP_BLOCK_TYPE_SDMA:
> + pp_dpm_powergate_sdma(handle, gate);
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 5d1dae2..b7a9d0c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1153,6 +1153,14 @@ static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
> return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
> }
>
> +static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
> +{
> + if (gate)
> + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);
> + else
> + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);
> +}
> +
> static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
> {
> if (bgate) {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index a6d9212..d1183b1 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -328,6 +328,7 @@ struct pp_hwmgr_func {
> int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
> int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
> int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
> + int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
> };
>
> struct pp_table_func {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/7] drm/amdgpu: Move out power up/down sdma out of smu
[not found] ` <1537966249-30259-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 14:13 ` Alex Deucher
0 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:13 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> smu only expose interface to other ip blocks.
> in order to reduce dependence between smu and other ip blocks
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 15 ---------------
> 3 files changed, 7 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 12e577c..c20d413 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1364,6 +1364,9 @@ static int sdma_v4_0_hw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
> + amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
> +
> sdma_v4_0_init_golden_registers(adev);
>
> r = sdma_v4_0_start(adev);
> @@ -1381,6 +1384,9 @@ static int sdma_v4_0_hw_fini(void *handle)
> sdma_v4_0_ctx_switch_enable(adev, false);
> sdma_v4_0_enable(adev, false);
>
> + if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
> + amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index b7a9d0c..dd18cb7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1216,6 +1216,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
> .smus_notify_pwe = smu10_smus_notify_pwe,
> .display_clock_voltage_request = smu10_display_clock_voltage_request,
> .powergate_gfx = smu10_gfx_off_control,
> + .powergate_sdma = smu10_powergate_sdma,
> };
>
> int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> index 6f961de..d78d864 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> @@ -186,19 +186,6 @@ static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -/* sdma is disabled by default in vbios, need to re-enable in driver */
> -static void smu10_smc_enable_sdma(struct pp_hwmgr *hwmgr)
> -{
> - smu10_send_msg_to_smc(hwmgr,
> - PPSMC_MSG_PowerUpSdma);
> -}
> -
> -static void smu10_smc_disable_sdma(struct pp_hwmgr *hwmgr)
> -{
> - smu10_send_msg_to_smc(hwmgr,
> - PPSMC_MSG_PowerDownSdma);
> -}
> -
> /* vcn is disabled by default in vbios, need to re-enable in driver */
> static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
> {
> @@ -218,7 +205,6 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
> (struct smu10_smumgr *)(hwmgr->smu_backend);
>
> if (priv) {
> - smu10_smc_disable_sdma(hwmgr);
> smu10_smc_disable_vcn(hwmgr);
> amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
> &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
> @@ -243,7 +229,6 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr)
>
> if (smu10_verify_smc_interface(hwmgr))
> return -EINVAL;
> - smu10_smc_enable_sdma(hwmgr);
> smu10_smc_enable_vcn(hwmgr);
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/7] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu
[not found] ` <1537966249-30259-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 14:13 ` Alex Deucher
0 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:13 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> the vcn power will be controlled by VCN.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 16 +---------------
> 1 file changed, 1 insertion(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> index d78d864..d0eb8ab 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> @@ -186,26 +186,12 @@ static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> -/* vcn is disabled by default in vbios, need to re-enable in driver */
> -static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
> -{
> - smu10_send_msg_to_smc_with_parameter(hwmgr,
> - PPSMC_MSG_PowerUpVcn, 0);
> -}
> -
> -static void smu10_smc_disable_vcn(struct pp_hwmgr *hwmgr)
> -{
> - smu10_send_msg_to_smc_with_parameter(hwmgr,
> - PPSMC_MSG_PowerDownVcn, 0);
> -}
> -
> static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
> {
> struct smu10_smumgr *priv =
> (struct smu10_smumgr *)(hwmgr->smu_backend);
>
> if (priv) {
> - smu10_smc_disable_vcn(hwmgr);
> amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
> &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
> &priv->smu_tables.entry[SMU10_WMTABLE].table);
> @@ -229,7 +215,7 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr)
>
> if (smu10_verify_smc_interface(hwmgr))
> return -EINVAL;
> - smu10_smc_enable_vcn(hwmgr);
> +
> return 0;
> }
>
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu
[not found] ` <1537966249-30259-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 14:14 ` Alex Deucher
0 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:14 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> HW CG feature will be enabled after hw ip initialized
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index ec14798..b6b62a7 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
> hwmgr->avfs_supported = false;
> }
>
> - /* To initialize all clock gating before RLC loaded and running.*/
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
> -
> /* Setup SoftRegsStart here for register lookup in case
> * DummyBackEnd is used and ProcessFirmwareHeader is not executed
> */
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
[not found] ` <1537966249-30259-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 14:15 ` Alex Deucher
[not found] ` <CADnq5_PoCAk_k8EnFhWSvQER6ennOcDH6_N-uEe35xHTCnbNjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 14:15 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
>
> Export this interface for the AMDGPU_FW_LOAD_SMU type.
> gfx/sdma can request smu to load firmware.
>
> Split the smu7/8_start_smu function into two functions
> 1. start_smu, used for load smu firmware in smu7/8 and
> check smu firmware version.
> 2. request_smu_load_fw, used for load other ip's firmware
> on smu7/8 and add firmware loading staus check.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Don't we need to convert sdma to use this interface as well?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++-
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++--
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 4 +-
> .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 25 ++++-----
> .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 +-
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 59 +++++-----------------
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 3 +-
> drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 46 ++++++++---------
> .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 12 ++++-
> .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 +-
> 10 files changed, 79 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 2aeef2b..f020f6f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4216,10 +4216,17 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> /* legacy rlc firmware loading */
> r = gfx_v8_0_rlc_load_microcode(adev);
> - if (r)
> - return r;
> + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU && adev->powerplay.pp_funcs->load_firmware) {
> + amdgpu_ucode_init_bo(adev);
> + r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
> + } else {
> + r = -EINVAL;
> }
>
> + if (r) {
> + pr_err("firmware loading failed\n");
> + return r;
> + }
> gfx_v8_0_rlc_start(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index aff7c14..3bc825c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle)
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> - amdgpu_ucode_init_bo(adev);
> -
> ret = hwmgr_hw_init(hwmgr);
>
> if (ret)
> @@ -275,7 +272,16 @@ static int pp_set_clockgating_state(void *handle,
>
> static int pp_dpm_load_fw(void *handle)
> {
> - return 0;
> + struct pp_hwmgr *hwmgr = handle;
> + int ret = 0;
> +
> + if (!hwmgr || !hwmgr->smumgr_funcs)
> + return -EINVAL;
> +
> + if (hwmgr->smumgr_funcs->request_smu_load_fw)
> + ret = hwmgr->smumgr_funcs->request_smu_load_fw(hwmgr);
> +
> + return ret;
> }
>
> static int pp_dpm_fw_loading_complete(void *handle)
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index b6b62a7..ffd7d78 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -310,8 +310,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
> offsetof(SMU73_Firmware_Header, SoftRegisters),
> &(priv->smu7_data.soft_regs_start), 0x40000);
>
> - result = smu7_request_smu_load_fw(hwmgr);
> -
> return result;
> }
>
> @@ -2643,7 +2641,7 @@ static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
> .smu_fini = &smu7_smu_fini,
> .start_smu = &fiji_start_smu,
> .check_fw_load_finish = &smu7_check_fw_load_finish,
> - .request_smu_load_fw = &smu7_reload_firmware,
> + .request_smu_load_fw = &smu7_request_smu_load_fw,
> .request_smu_load_specific_fw = NULL,
> .send_msg_to_smc = &smu7_send_msg_to_smc,
> .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index 73aa368..68a4836 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -232,27 +232,24 @@ static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
>
> static int iceland_start_smu(struct pp_hwmgr *hwmgr)
> {
> - int result;
> -
> - result = iceland_smu_upload_firmware_image(hwmgr);
> - if (result)
> - return result;
> - result = iceland_smu_start_smc(hwmgr);
> - if (result)
> - return result;
> + struct iceland_smumgr *priv = hwmgr->smu_backend;
> + int result = 0;
>
> if (!smu7_is_smc_ram_running(hwmgr)) {
> - pr_info("smu not running, upload firmware again \n");
> result = iceland_smu_upload_firmware_image(hwmgr);
> if (result)
> return result;
>
> - result = iceland_smu_start_smc(hwmgr);
> - if (result)
> - return result;
> + iceland_smu_start_smc(hwmgr);
> }
> + /* Setup SoftRegsStart here for register lookup in case
> + * DummyBackEnd is used and ProcessFirmwareHeader is not executed
> + */
>
> - result = smu7_request_smu_load_fw(hwmgr);
> + smu7_read_smc_sram_dword(hwmgr,
> + SMU71_FIRMWARE_HEADER_LOCATION +
> + offsetof(SMU71_Firmware_Header, SoftRegisters),
> + &(priv->smu7_data.soft_regs_start), 0x40000);
>
> return result;
> }
> @@ -2662,7 +2659,7 @@ static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
> .smu_fini = &smu7_smu_fini,
> .start_smu = &iceland_start_smu,
> .check_fw_load_finish = &smu7_check_fw_load_finish,
> - .request_smu_load_fw = &smu7_reload_firmware,
> + .request_smu_load_fw = &smu7_request_smu_load_fw,
> .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
> .send_msg_to_smc = &smu7_send_msg_to_smc,
> .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index 872d382..2ad6ad9 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -313,8 +313,6 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
> smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
> &(smu_data->smu7_data.soft_regs_start), 0x40000);
>
> - result = smu7_request_smu_load_fw(hwmgr);
> -
> return result;
> }
>
> @@ -2478,7 +2476,7 @@ static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
> .smu_fini = smu7_smu_fini,
> .start_smu = polaris10_start_smu,
> .check_fw_load_finish = smu7_check_fw_load_finish,
> - .request_smu_load_fw = smu7_reload_firmware,
> + .request_smu_load_fw = smu7_request_smu_load_fw,
> .request_smu_load_specific_fw = NULL,
> .send_msg_to_smc = smu7_send_msg_to_smc,
> .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 10eb967..edfb061 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_
> return 0;
> }
>
> -/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
> -
> -static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
> -{
> - uint32_t result = 0;
> -
> - switch (fw_type) {
> - case UCODE_ID_SDMA0:
> - result = UCODE_ID_SDMA0_MASK;
> - break;
> - case UCODE_ID_SDMA1:
> - result = UCODE_ID_SDMA1_MASK;
> - break;
> - case UCODE_ID_CP_CE:
> - result = UCODE_ID_CP_CE_MASK;
> - break;
> - case UCODE_ID_CP_PFP:
> - result = UCODE_ID_CP_PFP_MASK;
> - break;
> - case UCODE_ID_CP_ME:
> - result = UCODE_ID_CP_ME_MASK;
> - break;
> - case UCODE_ID_CP_MEC:
> - case UCODE_ID_CP_MEC_JT1:
> - case UCODE_ID_CP_MEC_JT2:
> - result = UCODE_ID_CP_MEC_MASK;
> - break;
> - case UCODE_ID_RLC_G:
> - result = UCODE_ID_RLC_G_MASK;
> - break;
> - default:
> - pr_info("UCode type is out of range! \n");
> - result = 0;
> - }
> -
> - return result;
> -}
> -
> static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
> uint32_t fw_type,
> struct SMU_Entry *entry)
> @@ -381,6 +343,11 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> uint32_t fw_to_load;
> int r = 0;
>
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> + pr_err("smu not running \n");
> + return -EINVAL;
> + }
> +
> if (smu_data->soft_regs_start)
> cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
> @@ -462,10 +429,13 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
> smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
>
> - if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
> - pr_err("Fail to Request SMU Load uCode");
> + smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load);
>
> - return r;
> + r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
> + if (!r)
> + return 0;
> +
> + pr_err("SMU load firmware failed\n");
>
> failed:
> kfree(smu_data->toc);
> @@ -477,20 +447,15 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
> {
> struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> - uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
> uint32_t ret;
>
> ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
> smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
> SMU_SoftRegisters, UcodeLoadStatus),
> - fw_mask, fw_mask);
> + fw_type, fw_type);
> return ret;
> }
>
> -int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
> -{
> - return hwmgr->smumgr_funcs->start_smu(hwmgr);
> -}
>
> static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
> {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> index 01f0538f..10c8ceb 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> @@ -73,9 +73,8 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
> int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
> uint32_t value, uint32_t limit);
>
> -int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
> int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
> -int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
> +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
> int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
> int smu7_init(struct pp_hwmgr *hwmgr);
> int smu7_smu_fini(struct pp_hwmgr *hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> index 7a4c425..90f5f30 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> @@ -658,6 +658,8 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> {
> struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
> uint32_t smc_address;
> + uint32_t fw_to_check = 0;
> + int ret;
>
> smu8_smu_populate_firmware_entries(hwmgr);
>
> @@ -684,28 +686,9 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
> smu8_smu->toc_entry_power_profiling_index);
>
> - return smu8_send_msg_to_smc_with_parameter(hwmgr,
> + smu8_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_ExecuteJob,
> smu8_smu->toc_entry_initialize_index);
> -}
> -
> -static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> -{
> - int ret = 0;
> - uint32_t fw_to_check = 0;
> - struct amdgpu_device *adev = hwmgr->adev;
> -
> - uint32_t index = SMN_MP1_SRAM_START_ADDR +
> - SMU8_FIRMWARE_HEADER_LOCATION +
> - offsetof(struct SMU8_Firmware_Header, Version);
> -
> -
> - if (hwmgr == NULL || hwmgr->device == NULL)
> - return -EINVAL;
> -
> - cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> - hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
> - adev->pm.fw_version = hwmgr->smu_version >> 8;
>
> fw_to_check = UCODE_ID_RLC_G_MASK |
> UCODE_ID_SDMA0_MASK |
> @@ -719,8 +702,6 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> if (hwmgr->chip_id == CHIP_STONEY)
> fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
>
> - smu8_request_smu_load_fw(hwmgr);
> -
> ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
> if (ret) {
> pr_err("SMU firmware load failed\n");
> @@ -734,6 +715,25 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> return ret;
> }
>
> +static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> +{
> + struct amdgpu_device *adev = hwmgr->adev;
> +
> + uint32_t index = SMN_MP1_SRAM_START_ADDR +
> + SMU8_FIRMWARE_HEADER_LOCATION +
> + offsetof(struct SMU8_Firmware_Header, Version);
> +
> +
> + if (hwmgr == NULL || hwmgr->device == NULL)
> + return -EINVAL;
> +
> + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> + hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
> + adev->pm.fw_version = hwmgr->smu_version >> 8;
> +
> + return 0;
> +}
> +
> static int smu8_smu_init(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
> @@ -876,7 +876,7 @@ static bool smu8_is_dpm_running(struct pp_hwmgr *hwmgr)
> .smu_fini = smu8_smu_fini,
> .start_smu = smu8_start_smu,
> .check_fw_load_finish = smu8_check_fw_load_finish,
> - .request_smu_load_fw = NULL,
> + .request_smu_load_fw = smu8_request_smu_load_fw,
> .request_smu_load_specific_fw = NULL,
> .get_argument = smu8_get_argument,
> .send_msg_to_smc = smu8_send_msg_to_smc,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index ae8378e..d8f1ca2 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -192,7 +192,8 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
>
> static int tonga_start_smu(struct pp_hwmgr *hwmgr)
> {
> - int result;
> + struct tonga_smumgr *priv = hwmgr->smu_backend;
> + int result = 0;
>
> /* Only start SMC if SMC RAM is not running */
> if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
> @@ -209,7 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
> }
> }
>
> - result = smu7_request_smu_load_fw(hwmgr);
> + /* Setup SoftRegsStart here for register lookup in case
> + * DummyBackEnd is used and ProcessFirmwareHeader is not executed
> + */
> +
> + smu7_read_smc_sram_dword(hwmgr,
> + SMU72_FIRMWARE_HEADER_LOCATION +
> + offsetof(SMU72_Firmware_Header, SoftRegisters),
> + &(priv->smu7_data.soft_regs_start), 0x40000);
>
> return result;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> index 3d415fa..71e376f 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> @@ -218,8 +218,6 @@ static int vegam_start_smu(struct pp_hwmgr *hwmgr)
> &(smu_data->smu7_data.soft_regs_start),
> 0x40000);
>
> - result = smu7_request_smu_load_fw(hwmgr);
> -
> return result;
> }
>
> @@ -2280,7 +2278,7 @@ static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
> .smu_fini = smu7_smu_fini,
> .start_smu = vegam_start_smu,
> .check_fw_load_finish = smu7_check_fw_load_finish,
> - .request_smu_load_fw = smu7_reload_firmware,
> + .request_smu_load_fw = smu7_request_smu_load_fw,
> .request_smu_load_specific_fw = NULL,
> .send_msg_to_smc = smu7_send_msg_to_smc,
> .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
[not found] ` <CADnq5_PoCAk_k8EnFhWSvQER6ennOcDH6_N-uEe35xHTCnbNjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-09-26 15:21 ` Zhu, Rex
[not found] ` <BYAPR12MB2775099DFB71D6B0D40F4F69FB150-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Zhu, Rex @ 2018-09-26 15:21 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, September 26, 2018 10:15 PM
> To: Zhu, Rex <Rex.Zhu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
>
> On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
> >
> > Export this interface for the AMDGPU_FW_LOAD_SMU type.
> > gfx/sdma can request smu to load firmware.
> >
> > Split the smu7/8_start_smu function into two functions 1. start_smu,
> > used for load smu firmware in smu7/8 and
> > check smu firmware version.
> > 2. request_smu_load_fw, used for load other ip's firmware
> > on smu7/8 and add firmware loading staus check.
> >
> > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Don't we need to convert sdma to use this interface as well?
When load firmware via smu, I load all the firmwares(rlc/ce/pfp/me/mec/sdma) at one time.
So just need to call the interface when load rlc firmware.
We also can load the firmware separately with ucode mask.
> Alex
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++-
> > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++--
> > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 4 +-
> > .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 25 ++++-----
> > .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 +-
> > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 59
> > +++++-----------------
> > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 3 +-
> drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 46 ++++++++--
> -------
> > .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 12 ++++-
> > .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 +-
> > 10 files changed, 79 insertions(+), 103 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 2aeef2b..f020f6f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -4216,10 +4216,17 @@ static int gfx_v8_0_rlc_resume(struct
> amdgpu_device *adev)
> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> > /* legacy rlc firmware loading */
> > r = gfx_v8_0_rlc_load_microcode(adev);
> > - if (r)
> > - return r;
> > + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU &&
> adev->powerplay.pp_funcs->load_firmware) {
> > + amdgpu_ucode_init_bo(adev);
> > + r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> > + } else {
> > + r = -EINVAL;
> > }
> >
> > + if (r) {
> > + pr_err("firmware loading failed\n");
> > + return r;
> > + }
> > gfx_v8_0_rlc_start(adev);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index aff7c14..3bc825c 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle)
> > struct amdgpu_device *adev = handle;
> > struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> >
> > - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> > - amdgpu_ucode_init_bo(adev);
> > -
> > ret = hwmgr_hw_init(hwmgr);
> >
> > if (ret)
> > @@ -275,7 +272,16 @@ static int pp_set_clockgating_state(void *handle,
> >
> > static int pp_dpm_load_fw(void *handle) {
> > - return 0;
> > + struct pp_hwmgr *hwmgr = handle;
> > + int ret = 0;
> > +
> > + if (!hwmgr || !hwmgr->smumgr_funcs)
> > + return -EINVAL;
> > +
> > + if (hwmgr->smumgr_funcs->request_smu_load_fw)
> > + ret = hwmgr->smumgr_funcs->request_smu_load_fw(hwmgr);
> > +
> > + return ret;
> > }
> >
> > static int pp_dpm_fw_loading_complete(void *handle) diff --git
> > a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > index b6b62a7..ffd7d78 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > @@ -310,8 +310,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
> > offsetof(SMU73_Firmware_Header, SoftRegisters),
> > &(priv->smu7_data.soft_regs_start), 0x40000);
> >
> > - result = smu7_request_smu_load_fw(hwmgr);
> > -
> > return result;
> > }
> >
> > @@ -2643,7 +2641,7 @@ static int fiji_update_dpm_settings(struct
> pp_hwmgr *hwmgr,
> > .smu_fini = &smu7_smu_fini,
> > .start_smu = &fiji_start_smu,
> > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > - .request_smu_load_fw = &smu7_reload_firmware,
> > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > .request_smu_load_specific_fw = NULL,
> > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > .send_msg_to_smc_with_parameter =
> > &smu7_send_msg_to_smc_with_parameter,
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > index 73aa368..68a4836 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > @@ -232,27 +232,24 @@ static int
> > iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
> >
> > static int iceland_start_smu(struct pp_hwmgr *hwmgr) {
> > - int result;
> > -
> > - result = iceland_smu_upload_firmware_image(hwmgr);
> > - if (result)
> > - return result;
> > - result = iceland_smu_start_smc(hwmgr);
> > - if (result)
> > - return result;
> > + struct iceland_smumgr *priv = hwmgr->smu_backend;
> > + int result = 0;
> >
> > if (!smu7_is_smc_ram_running(hwmgr)) {
> > - pr_info("smu not running, upload firmware again \n");
> > result = iceland_smu_upload_firmware_image(hwmgr);
> > if (result)
> > return result;
> >
> > - result = iceland_smu_start_smc(hwmgr);
> > - if (result)
> > - return result;
> > + iceland_smu_start_smc(hwmgr);
> > }
> > + /* Setup SoftRegsStart here for register lookup in case
> > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> executed
> > + */
> >
> > - result = smu7_request_smu_load_fw(hwmgr);
> > + smu7_read_smc_sram_dword(hwmgr,
> > + SMU71_FIRMWARE_HEADER_LOCATION +
> > + offsetof(SMU71_Firmware_Header, SoftRegisters),
> > + &(priv->smu7_data.soft_regs_start), 0x40000);
> >
> > return result;
> > }
> > @@ -2662,7 +2659,7 @@ static bool iceland_is_dpm_running(struct
> pp_hwmgr *hwmgr)
> > .smu_fini = &smu7_smu_fini,
> > .start_smu = &iceland_start_smu,
> > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > - .request_smu_load_fw = &smu7_reload_firmware,
> > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > .request_smu_load_specific_fw =
> &iceland_request_smu_load_specific_fw,
> > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > .send_msg_to_smc_with_parameter =
> > &smu7_send_msg_to_smc_with_parameter,
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > index 872d382..2ad6ad9 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > @@ -313,8 +313,6 @@ static int polaris10_start_smu(struct pp_hwmgr
> *hwmgr)
> > smu7_read_smc_sram_dword(hwmgr,
> SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header,
> SoftRegisters),
> >
> > &(smu_data->smu7_data.soft_regs_start), 0x40000);
> >
> > - result = smu7_request_smu_load_fw(hwmgr);
> > -
> > return result;
> > }
> >
> > @@ -2478,7 +2476,7 @@ static int polaris10_update_dpm_settings(struct
> pp_hwmgr *hwmgr,
> > .smu_fini = smu7_smu_fini,
> > .start_smu = polaris10_start_smu,
> > .check_fw_load_finish = smu7_check_fw_load_finish,
> > - .request_smu_load_fw = smu7_reload_firmware,
> > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > .request_smu_load_specific_fw = NULL,
> > .send_msg_to_smc = smu7_send_msg_to_smc,
> > .send_msg_to_smc_with_parameter =
> > smu7_send_msg_to_smc_with_parameter,
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > index 10eb967..edfb061 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > @@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct
> pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_
> > return 0;
> > }
> >
> > -/* Convert the firmware type to SMU type mask. For MEC, we need to
> > check all MEC related type */
> > -
> > -static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type) -{
> > - uint32_t result = 0;
> > -
> > - switch (fw_type) {
> > - case UCODE_ID_SDMA0:
> > - result = UCODE_ID_SDMA0_MASK;
> > - break;
> > - case UCODE_ID_SDMA1:
> > - result = UCODE_ID_SDMA1_MASK;
> > - break;
> > - case UCODE_ID_CP_CE:
> > - result = UCODE_ID_CP_CE_MASK;
> > - break;
> > - case UCODE_ID_CP_PFP:
> > - result = UCODE_ID_CP_PFP_MASK;
> > - break;
> > - case UCODE_ID_CP_ME:
> > - result = UCODE_ID_CP_ME_MASK;
> > - break;
> > - case UCODE_ID_CP_MEC:
> > - case UCODE_ID_CP_MEC_JT1:
> > - case UCODE_ID_CP_MEC_JT2:
> > - result = UCODE_ID_CP_MEC_MASK;
> > - break;
> > - case UCODE_ID_RLC_G:
> > - result = UCODE_ID_RLC_G_MASK;
> > - break;
> > - default:
> > - pr_info("UCode type is out of range! \n");
> > - result = 0;
> > - }
> > -
> > - return result;
> > -}
> > -
> > static int smu7_populate_single_firmware_entry(struct pp_hwmgr
> *hwmgr,
> > uint32_t fw_type,
> > struct SMU_Entry
> > *entry) @@ -381,6 +343,11 @@ int smu7_request_smu_load_fw(struct
> pp_hwmgr *hwmgr)
> > uint32_t fw_to_load;
> > int r = 0;
> >
> > + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> > + pr_err("smu not running \n");
> > + return -EINVAL;
> > + }
> > +
> > if (smu_data->soft_regs_start)
> > cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> > smu_data->soft_regs_start +
> > smum_get_offsetof(hwmgr, @@ -462,10 +429,13 @@ int
> smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> > smu7_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data-
> >header_buffer.mc_addr));
> > smu7_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_DRV_DRAM_ADDR_LO,
> > lower_32_bits(smu_data->header_buffer.mc_addr));
> >
> > - if (smu7_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_LoadUcodes, fw_to_load))
> > - pr_err("Fail to Request SMU Load uCode");
> > + smu7_send_msg_to_smc_with_parameter(hwmgr,
> > + PPSMC_MSG_LoadUcodes, fw_to_load);
> >
> > - return r;
> > + r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
> > + if (!r)
> > + return 0;
> > +
> > + pr_err("SMU load firmware failed\n");
> >
> > failed:
> > kfree(smu_data->toc);
> > @@ -477,20 +447,15 @@ int smu7_request_smu_load_fw(struct
> pp_hwmgr
> > *hwmgr) int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr,
> > uint32_t fw_type) {
> > struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr-
> >smu_backend);
> > - uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
> > uint32_t ret;
> >
> > ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
> > smu_data->soft_regs_start +
> smum_get_offsetof(hwmgr,
> > SMU_SoftRegisters, UcodeLoadStatus),
> > - fw_mask, fw_mask);
> > + fw_type, fw_type);
> > return ret;
> > }
> >
> > -int smu7_reload_firmware(struct pp_hwmgr *hwmgr) -{
> > - return hwmgr->smumgr_funcs->start_smu(hwmgr);
> > -}
> >
> > static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
> > uint32_t length, uint32_t *src, uint32_t limit) { diff --git
> > a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > index 01f0538f..10c8ceb 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > @@ -73,9 +73,8 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr
> *hwmgr,
> > uint32_t smc_addr, int smu7_write_smc_sram_dword(struct pp_hwmgr
> *hwmgr, uint32_t smc_addr,
> > uint32_t value,
> > uint32_t limit);
> >
> > -int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr); int
> > smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
> > -int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
> > +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
> > int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr); int
> > smu7_init(struct pp_hwmgr *hwmgr); int smu7_smu_fini(struct pp_hwmgr
> > *hwmgr); diff --git
> > a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > index 7a4c425..90f5f30 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > @@ -658,6 +658,8 @@ static int smu8_request_smu_load_fw(struct
> > pp_hwmgr *hwmgr) {
> > struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
> > uint32_t smc_address;
> > + uint32_t fw_to_check = 0;
> > + int ret;
> >
> > smu8_smu_populate_firmware_entries(hwmgr);
> >
> > @@ -684,28 +686,9 @@ static int smu8_request_smu_load_fw(struct
> pp_hwmgr *hwmgr)
> > smu8_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_ExecuteJob,
> >
> > smu8_smu->toc_entry_power_profiling_index);
> >
> > - return smu8_send_msg_to_smc_with_parameter(hwmgr,
> > + smu8_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_ExecuteJob,
> >
> > smu8_smu->toc_entry_initialize_index);
> > -}
> > -
> > -static int smu8_start_smu(struct pp_hwmgr *hwmgr) -{
> > - int ret = 0;
> > - uint32_t fw_to_check = 0;
> > - struct amdgpu_device *adev = hwmgr->adev;
> > -
> > - uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > - SMU8_FIRMWARE_HEADER_LOCATION +
> > - offsetof(struct SMU8_Firmware_Header, Version);
> > -
> > -
> > - if (hwmgr == NULL || hwmgr->device == NULL)
> > - return -EINVAL;
> > -
> > - cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> > - hwmgr->smu_version = cgs_read_register(hwmgr->device,
> mmMP0PUB_IND_DATA);
> > - adev->pm.fw_version = hwmgr->smu_version >> 8;
> >
> > fw_to_check = UCODE_ID_RLC_G_MASK |
> > UCODE_ID_SDMA0_MASK | @@ -719,8 +702,6 @@
> > static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > if (hwmgr->chip_id == CHIP_STONEY)
> > fw_to_check &= ~(UCODE_ID_SDMA1_MASK |
> > UCODE_ID_CP_MEC_JT2_MASK);
> >
> > - smu8_request_smu_load_fw(hwmgr);
> > -
> > ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
> > if (ret) {
> > pr_err("SMU firmware load failed\n"); @@ -734,6
> > +715,25 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > return ret;
> > }
> >
> > +static int smu8_start_smu(struct pp_hwmgr *hwmgr) {
> > + struct amdgpu_device *adev = hwmgr->adev;
> > +
> > + uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > + SMU8_FIRMWARE_HEADER_LOCATION +
> > + offsetof(struct SMU8_Firmware_Header,
> > + Version);
> > +
> > +
> > + if (hwmgr == NULL || hwmgr->device == NULL)
> > + return -EINVAL;
> > +
> > + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> > + hwmgr->smu_version = cgs_read_register(hwmgr->device,
> mmMP0PUB_IND_DATA);
> > + adev->pm.fw_version = hwmgr->smu_version >> 8;
> > +
> > + return 0;
> > +}
> > +
> > static int smu8_smu_init(struct pp_hwmgr *hwmgr) {
> > int ret = 0;
> > @@ -876,7 +876,7 @@ static bool smu8_is_dpm_running(struct
> pp_hwmgr *hwmgr)
> > .smu_fini = smu8_smu_fini,
> > .start_smu = smu8_start_smu,
> > .check_fw_load_finish = smu8_check_fw_load_finish,
> > - .request_smu_load_fw = NULL,
> > + .request_smu_load_fw = smu8_request_smu_load_fw,
> > .request_smu_load_specific_fw = NULL,
> > .get_argument = smu8_get_argument,
> > .send_msg_to_smc = smu8_send_msg_to_smc, diff --git
> > a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > index ae8378e..d8f1ca2 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > @@ -192,7 +192,8 @@ static int
> > tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
> >
> > static int tonga_start_smu(struct pp_hwmgr *hwmgr) {
> > - int result;
> > + struct tonga_smumgr *priv = hwmgr->smu_backend;
> > + int result = 0;
> >
> > /* Only start SMC if SMC RAM is not running */
> > if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { @@
> > -209,7 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
> > }
> > }
> >
> > - result = smu7_request_smu_load_fw(hwmgr);
> > + /* Setup SoftRegsStart here for register lookup in case
> > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> executed
> > + */
> > +
> > + smu7_read_smc_sram_dword(hwmgr,
> > + SMU72_FIRMWARE_HEADER_LOCATION +
> > + offsetof(SMU72_Firmware_Header, SoftRegisters),
> > + &(priv->smu7_data.soft_regs_start), 0x40000);
> >
> > return result;
> > }
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > index 3d415fa..71e376f 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > @@ -218,8 +218,6 @@ static int vegam_start_smu(struct pp_hwmgr
> *hwmgr)
> > &(smu_data->smu7_data.soft_regs_start),
> > 0x40000);
> >
> > - result = smu7_request_smu_load_fw(hwmgr);
> > -
> > return result;
> > }
> >
> > @@ -2280,7 +2278,7 @@ static int vegam_thermal_setup_fan_table(struct
> pp_hwmgr *hwmgr)
> > .smu_fini = smu7_smu_fini,
> > .start_smu = vegam_start_smu,
> > .check_fw_load_finish = smu7_check_fw_load_finish,
> > - .request_smu_load_fw = smu7_reload_firmware,
> > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > .request_smu_load_specific_fw = NULL,
> > .send_msg_to_smc = smu7_send_msg_to_smc,
> > .send_msg_to_smc_with_parameter =
> > smu7_send_msg_to_smc_with_parameter,
> > --
> > 1.9.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
[not found] ` <BYAPR12MB2775099DFB71D6B0D40F4F69FB150-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-09-26 15:39 ` Alex Deucher
[not found] ` <CADnq5_Obr9=qhsJqjKDpJccjpW24a5yjg34+fYLyA9qrBYDDfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Alex Deucher @ 2018-09-26 15:39 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Sep 26, 2018 at 11:21 AM Zhu, Rex <Rex.Zhu@amd.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Alex Deucher <alexdeucher@gmail.com>
> > Sent: Wednesday, September 26, 2018 10:15 PM
> > To: Zhu, Rex <Rex.Zhu@amd.com>
> > Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> > Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
> >
> > On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
> > >
> > > Export this interface for the AMDGPU_FW_LOAD_SMU type.
> > > gfx/sdma can request smu to load firmware.
> > >
> > > Split the smu7/8_start_smu function into two functions 1. start_smu,
> > > used for load smu firmware in smu7/8 and
> > > check smu firmware version.
> > > 2. request_smu_load_fw, used for load other ip's firmware
> > > on smu7/8 and add firmware loading staus check.
> > >
> > > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> >
> > Don't we need to convert sdma to use this interface as well?
>
> When load firmware via smu, I load all the firmwares(rlc/ce/pfp/me/mec/sdma) at one time.
> So just need to call the interface when load rlc firmware.
> We also can load the firmware separately with ucode mask.
I see. So we rely on the call from the gfx IP to load all the FWs.
It might be better to be more explicit. E.g., if someone disables the
gfx IP via the ip_block_mask parameter, that would break sdma.
Alex
>
>
> > Alex
> >
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++-
> > > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++--
> > > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 4 +-
> > > .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 25 ++++-----
> > > .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 +-
> > > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 59
> > > +++++-----------------
> > > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 3 +-
> > drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 46 ++++++++--
> > -------
> > > .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 12 ++++-
> > > .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 +-
> > > 10 files changed, 79 insertions(+), 103 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > index 2aeef2b..f020f6f 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > @@ -4216,10 +4216,17 @@ static int gfx_v8_0_rlc_resume(struct
> > amdgpu_device *adev)
> > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> > > /* legacy rlc firmware loading */
> > > r = gfx_v8_0_rlc_load_microcode(adev);
> > > - if (r)
> > > - return r;
> > > + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU &&
> > adev->powerplay.pp_funcs->load_firmware) {
> > > + amdgpu_ucode_init_bo(adev);
> > > + r = adev->powerplay.pp_funcs->load_firmware(adev-
> > >powerplay.pp_handle);
> > > + } else {
> > > + r = -EINVAL;
> > > }
> > >
> > > + if (r) {
> > > + pr_err("firmware loading failed\n");
> > > + return r;
> > > + }
> > > gfx_v8_0_rlc_start(adev);
> > >
> > > return 0;
> > > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > index aff7c14..3bc825c 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle)
> > > struct amdgpu_device *adev = handle;
> > > struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> > >
> > > - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> > > - amdgpu_ucode_init_bo(adev);
> > > -
> > > ret = hwmgr_hw_init(hwmgr);
> > >
> > > if (ret)
> > > @@ -275,7 +272,16 @@ static int pp_set_clockgating_state(void *handle,
> > >
> > > static int pp_dpm_load_fw(void *handle) {
> > > - return 0;
> > > + struct pp_hwmgr *hwmgr = handle;
> > > + int ret = 0;
> > > +
> > > + if (!hwmgr || !hwmgr->smumgr_funcs)
> > > + return -EINVAL;
> > > +
> > > + if (hwmgr->smumgr_funcs->request_smu_load_fw)
> > > + ret = hwmgr->smumgr_funcs->request_smu_load_fw(hwmgr);
> > > +
> > > + return ret;
> > > }
> > >
> > > static int pp_dpm_fw_loading_complete(void *handle) diff --git
> > > a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > index b6b62a7..ffd7d78 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > @@ -310,8 +310,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
> > > offsetof(SMU73_Firmware_Header, SoftRegisters),
> > > &(priv->smu7_data.soft_regs_start), 0x40000);
> > >
> > > - result = smu7_request_smu_load_fw(hwmgr);
> > > -
> > > return result;
> > > }
> > >
> > > @@ -2643,7 +2641,7 @@ static int fiji_update_dpm_settings(struct
> > pp_hwmgr *hwmgr,
> > > .smu_fini = &smu7_smu_fini,
> > > .start_smu = &fiji_start_smu,
> > > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > > - .request_smu_load_fw = &smu7_reload_firmware,
> > > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > > .request_smu_load_specific_fw = NULL,
> > > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > > .send_msg_to_smc_with_parameter =
> > > &smu7_send_msg_to_smc_with_parameter,
> > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > index 73aa368..68a4836 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > @@ -232,27 +232,24 @@ static int
> > > iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
> > >
> > > static int iceland_start_smu(struct pp_hwmgr *hwmgr) {
> > > - int result;
> > > -
> > > - result = iceland_smu_upload_firmware_image(hwmgr);
> > > - if (result)
> > > - return result;
> > > - result = iceland_smu_start_smc(hwmgr);
> > > - if (result)
> > > - return result;
> > > + struct iceland_smumgr *priv = hwmgr->smu_backend;
> > > + int result = 0;
> > >
> > > if (!smu7_is_smc_ram_running(hwmgr)) {
> > > - pr_info("smu not running, upload firmware again \n");
> > > result = iceland_smu_upload_firmware_image(hwmgr);
> > > if (result)
> > > return result;
> > >
> > > - result = iceland_smu_start_smc(hwmgr);
> > > - if (result)
> > > - return result;
> > > + iceland_smu_start_smc(hwmgr);
> > > }
> > > + /* Setup SoftRegsStart here for register lookup in case
> > > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> > executed
> > > + */
> > >
> > > - result = smu7_request_smu_load_fw(hwmgr);
> > > + smu7_read_smc_sram_dword(hwmgr,
> > > + SMU71_FIRMWARE_HEADER_LOCATION +
> > > + offsetof(SMU71_Firmware_Header, SoftRegisters),
> > > + &(priv->smu7_data.soft_regs_start), 0x40000);
> > >
> > > return result;
> > > }
> > > @@ -2662,7 +2659,7 @@ static bool iceland_is_dpm_running(struct
> > pp_hwmgr *hwmgr)
> > > .smu_fini = &smu7_smu_fini,
> > > .start_smu = &iceland_start_smu,
> > > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > > - .request_smu_load_fw = &smu7_reload_firmware,
> > > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > > .request_smu_load_specific_fw =
> > &iceland_request_smu_load_specific_fw,
> > > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > > .send_msg_to_smc_with_parameter =
> > > &smu7_send_msg_to_smc_with_parameter,
> > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > index 872d382..2ad6ad9 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > @@ -313,8 +313,6 @@ static int polaris10_start_smu(struct pp_hwmgr
> > *hwmgr)
> > > smu7_read_smc_sram_dword(hwmgr,
> > SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header,
> > SoftRegisters),
> > >
> > > &(smu_data->smu7_data.soft_regs_start), 0x40000);
> > >
> > > - result = smu7_request_smu_load_fw(hwmgr);
> > > -
> > > return result;
> > > }
> > >
> > > @@ -2478,7 +2476,7 @@ static int polaris10_update_dpm_settings(struct
> > pp_hwmgr *hwmgr,
> > > .smu_fini = smu7_smu_fini,
> > > .start_smu = polaris10_start_smu,
> > > .check_fw_load_finish = smu7_check_fw_load_finish,
> > > - .request_smu_load_fw = smu7_reload_firmware,
> > > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > > .request_smu_load_specific_fw = NULL,
> > > .send_msg_to_smc = smu7_send_msg_to_smc,
> > > .send_msg_to_smc_with_parameter =
> > > smu7_send_msg_to_smc_with_parameter,
> > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > index 10eb967..edfb061 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > @@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct
> > pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_
> > > return 0;
> > > }
> > >
> > > -/* Convert the firmware type to SMU type mask. For MEC, we need to
> > > check all MEC related type */
> > > -
> > > -static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type) -{
> > > - uint32_t result = 0;
> > > -
> > > - switch (fw_type) {
> > > - case UCODE_ID_SDMA0:
> > > - result = UCODE_ID_SDMA0_MASK;
> > > - break;
> > > - case UCODE_ID_SDMA1:
> > > - result = UCODE_ID_SDMA1_MASK;
> > > - break;
> > > - case UCODE_ID_CP_CE:
> > > - result = UCODE_ID_CP_CE_MASK;
> > > - break;
> > > - case UCODE_ID_CP_PFP:
> > > - result = UCODE_ID_CP_PFP_MASK;
> > > - break;
> > > - case UCODE_ID_CP_ME:
> > > - result = UCODE_ID_CP_ME_MASK;
> > > - break;
> > > - case UCODE_ID_CP_MEC:
> > > - case UCODE_ID_CP_MEC_JT1:
> > > - case UCODE_ID_CP_MEC_JT2:
> > > - result = UCODE_ID_CP_MEC_MASK;
> > > - break;
> > > - case UCODE_ID_RLC_G:
> > > - result = UCODE_ID_RLC_G_MASK;
> > > - break;
> > > - default:
> > > - pr_info("UCode type is out of range! \n");
> > > - result = 0;
> > > - }
> > > -
> > > - return result;
> > > -}
> > > -
> > > static int smu7_populate_single_firmware_entry(struct pp_hwmgr
> > *hwmgr,
> > > uint32_t fw_type,
> > > struct SMU_Entry
> > > *entry) @@ -381,6 +343,11 @@ int smu7_request_smu_load_fw(struct
> > pp_hwmgr *hwmgr)
> > > uint32_t fw_to_load;
> > > int r = 0;
> > >
> > > + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> > > + pr_err("smu not running \n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > if (smu_data->soft_regs_start)
> > > cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> > > smu_data->soft_regs_start +
> > > smum_get_offsetof(hwmgr, @@ -462,10 +429,13 @@ int
> > smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> > > smu7_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data-
> > >header_buffer.mc_addr));
> > > smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > PPSMC_MSG_DRV_DRAM_ADDR_LO,
> > > lower_32_bits(smu_data->header_buffer.mc_addr));
> > >
> > > - if (smu7_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_LoadUcodes, fw_to_load))
> > > - pr_err("Fail to Request SMU Load uCode");
> > > + smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > + PPSMC_MSG_LoadUcodes, fw_to_load);
> > >
> > > - return r;
> > > + r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
> > > + if (!r)
> > > + return 0;
> > > +
> > > + pr_err("SMU load firmware failed\n");
> > >
> > > failed:
> > > kfree(smu_data->toc);
> > > @@ -477,20 +447,15 @@ int smu7_request_smu_load_fw(struct
> > pp_hwmgr
> > > *hwmgr) int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr,
> > > uint32_t fw_type) {
> > > struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr-
> > >smu_backend);
> > > - uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
> > > uint32_t ret;
> > >
> > > ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
> > > smu_data->soft_regs_start +
> > smum_get_offsetof(hwmgr,
> > > SMU_SoftRegisters, UcodeLoadStatus),
> > > - fw_mask, fw_mask);
> > > + fw_type, fw_type);
> > > return ret;
> > > }
> > >
> > > -int smu7_reload_firmware(struct pp_hwmgr *hwmgr) -{
> > > - return hwmgr->smumgr_funcs->start_smu(hwmgr);
> > > -}
> > >
> > > static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
> > > uint32_t length, uint32_t *src, uint32_t limit) { diff --git
> > > a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > index 01f0538f..10c8ceb 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > @@ -73,9 +73,8 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr
> > *hwmgr,
> > > uint32_t smc_addr, int smu7_write_smc_sram_dword(struct pp_hwmgr
> > *hwmgr, uint32_t smc_addr,
> > > uint32_t value,
> > > uint32_t limit);
> > >
> > > -int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr); int
> > > smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
> > > -int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
> > > +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
> > > int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr); int
> > > smu7_init(struct pp_hwmgr *hwmgr); int smu7_smu_fini(struct pp_hwmgr
> > > *hwmgr); diff --git
> > > a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > index 7a4c425..90f5f30 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > @@ -658,6 +658,8 @@ static int smu8_request_smu_load_fw(struct
> > > pp_hwmgr *hwmgr) {
> > > struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
> > > uint32_t smc_address;
> > > + uint32_t fw_to_check = 0;
> > > + int ret;
> > >
> > > smu8_smu_populate_firmware_entries(hwmgr);
> > >
> > > @@ -684,28 +686,9 @@ static int smu8_request_smu_load_fw(struct
> > pp_hwmgr *hwmgr)
> > > smu8_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_ExecuteJob,
> > >
> > > smu8_smu->toc_entry_power_profiling_index);
> > >
> > > - return smu8_send_msg_to_smc_with_parameter(hwmgr,
> > > + smu8_send_msg_to_smc_with_parameter(hwmgr,
> > > PPSMC_MSG_ExecuteJob,
> > >
> > > smu8_smu->toc_entry_initialize_index);
> > > -}
> > > -
> > > -static int smu8_start_smu(struct pp_hwmgr *hwmgr) -{
> > > - int ret = 0;
> > > - uint32_t fw_to_check = 0;
> > > - struct amdgpu_device *adev = hwmgr->adev;
> > > -
> > > - uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > > - SMU8_FIRMWARE_HEADER_LOCATION +
> > > - offsetof(struct SMU8_Firmware_Header, Version);
> > > -
> > > -
> > > - if (hwmgr == NULL || hwmgr->device == NULL)
> > > - return -EINVAL;
> > > -
> > > - cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> > > - hwmgr->smu_version = cgs_read_register(hwmgr->device,
> > mmMP0PUB_IND_DATA);
> > > - adev->pm.fw_version = hwmgr->smu_version >> 8;
> > >
> > > fw_to_check = UCODE_ID_RLC_G_MASK |
> > > UCODE_ID_SDMA0_MASK | @@ -719,8 +702,6 @@
> > > static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > > if (hwmgr->chip_id == CHIP_STONEY)
> > > fw_to_check &= ~(UCODE_ID_SDMA1_MASK |
> > > UCODE_ID_CP_MEC_JT2_MASK);
> > >
> > > - smu8_request_smu_load_fw(hwmgr);
> > > -
> > > ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
> > > if (ret) {
> > > pr_err("SMU firmware load failed\n"); @@ -734,6
> > > +715,25 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > > return ret;
> > > }
> > >
> > > +static int smu8_start_smu(struct pp_hwmgr *hwmgr) {
> > > + struct amdgpu_device *adev = hwmgr->adev;
> > > +
> > > + uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > > + SMU8_FIRMWARE_HEADER_LOCATION +
> > > + offsetof(struct SMU8_Firmware_Header,
> > > + Version);
> > > +
> > > +
> > > + if (hwmgr == NULL || hwmgr->device == NULL)
> > > + return -EINVAL;
> > > +
> > > + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> > > + hwmgr->smu_version = cgs_read_register(hwmgr->device,
> > mmMP0PUB_IND_DATA);
> > > + adev->pm.fw_version = hwmgr->smu_version >> 8;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static int smu8_smu_init(struct pp_hwmgr *hwmgr) {
> > > int ret = 0;
> > > @@ -876,7 +876,7 @@ static bool smu8_is_dpm_running(struct
> > pp_hwmgr *hwmgr)
> > > .smu_fini = smu8_smu_fini,
> > > .start_smu = smu8_start_smu,
> > > .check_fw_load_finish = smu8_check_fw_load_finish,
> > > - .request_smu_load_fw = NULL,
> > > + .request_smu_load_fw = smu8_request_smu_load_fw,
> > > .request_smu_load_specific_fw = NULL,
> > > .get_argument = smu8_get_argument,
> > > .send_msg_to_smc = smu8_send_msg_to_smc, diff --git
> > > a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > index ae8378e..d8f1ca2 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > @@ -192,7 +192,8 @@ static int
> > > tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
> > >
> > > static int tonga_start_smu(struct pp_hwmgr *hwmgr) {
> > > - int result;
> > > + struct tonga_smumgr *priv = hwmgr->smu_backend;
> > > + int result = 0;
> > >
> > > /* Only start SMC if SMC RAM is not running */
> > > if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { @@
> > > -209,7 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
> > > }
> > > }
> > >
> > > - result = smu7_request_smu_load_fw(hwmgr);
> > > + /* Setup SoftRegsStart here for register lookup in case
> > > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> > executed
> > > + */
> > > +
> > > + smu7_read_smc_sram_dword(hwmgr,
> > > + SMU72_FIRMWARE_HEADER_LOCATION +
> > > + offsetof(SMU72_Firmware_Header, SoftRegisters),
> > > + &(priv->smu7_data.soft_regs_start), 0x40000);
> > >
> > > return result;
> > > }
> > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > index 3d415fa..71e376f 100644
> > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > @@ -218,8 +218,6 @@ static int vegam_start_smu(struct pp_hwmgr
> > *hwmgr)
> > > &(smu_data->smu7_data.soft_regs_start),
> > > 0x40000);
> > >
> > > - result = smu7_request_smu_load_fw(hwmgr);
> > > -
> > > return result;
> > > }
> > >
> > > @@ -2280,7 +2278,7 @@ static int vegam_thermal_setup_fan_table(struct
> > pp_hwmgr *hwmgr)
> > > .smu_fini = smu7_smu_fini,
> > > .start_smu = vegam_start_smu,
> > > .check_fw_load_finish = smu7_check_fw_load_finish,
> > > - .request_smu_load_fw = smu7_reload_firmware,
> > > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > > .request_smu_load_specific_fw = NULL,
> > > .send_msg_to_smc = smu7_send_msg_to_smc,
> > > .send_msg_to_smc_with_parameter =
> > > smu7_send_msg_to_smc_with_parameter,
> > > --
> > > 1.9.1
> > >
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
[not found] ` <CADnq5_Obr9=qhsJqjKDpJccjpW24a5yjg34+fYLyA9qrBYDDfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-09-26 15:55 ` Zhu, Rex
0 siblings, 0 replies; 16+ messages in thread
From: Zhu, Rex @ 2018-09-26 15:55 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, September 26, 2018 11:39 PM
> To: Zhu, Rex <Rex.Zhu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
>
> On Wed, Sep 26, 2018 at 11:21 AM Zhu, Rex <Rex.Zhu@amd.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Alex Deucher <alexdeucher@gmail.com>
> > > Sent: Wednesday, September 26, 2018 10:15 PM
> > > To: Zhu, Rex <Rex.Zhu@amd.com>
> > > Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> > > Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
> > >
> > > On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu <Rex.Zhu@amd.com> wrote:
> > > >
> > > > Export this interface for the AMDGPU_FW_LOAD_SMU type.
> > > > gfx/sdma can request smu to load firmware.
> > > >
> > > > Split the smu7/8_start_smu function into two functions 1.
> > > > start_smu, used for load smu firmware in smu7/8 and
> > > > check smu firmware version.
> > > > 2. request_smu_load_fw, used for load other ip's firmware
> > > > on smu7/8 and add firmware loading staus check.
> > > >
> > > > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> > >
> > > Don't we need to convert sdma to use this interface as well?
> >
> > When load firmware via smu, I load all the
> firmwares(rlc/ce/pfp/me/mec/sdma) at one time.
> > So just need to call the interface when load rlc firmware.
> > We also can load the firmware separately with ucode mask.
>
> I see. So we rely on the call from the gfx IP to load all the FWs.
> It might be better to be more explicit. E.g., if someone disables the gfx IP via
> the ip_block_mask parameter, that would break sdma.
I didn't consider that aspect.
We can load firmware separately with ucode_id.
Or just call this function again in sdma to load all the firmware.
When firmware is loaded , clean the reload_fw in Patch5.
Best Regards
Rex
> Alex
>
> >
> >
> > > Alex
> > >
> > > > ---
> > > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++-
> > > > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++--
> > > > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 4 +-
> > > > .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 25 ++++-----
> > > > .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 +-
> > > > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 59
> > > > +++++-----------------
> > > > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 3 +-
> > > drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 46
> ++++++++--
> > > -------
> > > > .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 12 ++++-
> > > > .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 +-
> > > > 10 files changed, 79 insertions(+), 103 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > > index 2aeef2b..f020f6f 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > > > @@ -4216,10 +4216,17 @@ static int gfx_v8_0_rlc_resume(struct
> > > amdgpu_device *adev)
> > > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> > > > /* legacy rlc firmware loading */
> > > > r = gfx_v8_0_rlc_load_microcode(adev);
> > > > - if (r)
> > > > - return r;
> > > > + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU
> > > > + &&
> > > adev->powerplay.pp_funcs->load_firmware) {
> > > > + amdgpu_ucode_init_bo(adev);
> > > > + r = adev->powerplay.pp_funcs->load_firmware(adev-
> > > >powerplay.pp_handle);
> > > > + } else {
> > > > + r = -EINVAL;
> > > > }
> > > >
> > > > + if (r) {
> > > > + pr_err("firmware loading failed\n");
> > > > + return r;
> > > > + }
> > > > gfx_v8_0_rlc_start(adev);
> > > >
> > > > return 0;
> > > > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > > index aff7c14..3bc825c 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > > > @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle)
> > > > struct amdgpu_device *adev = handle;
> > > > struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> > > >
> > > > - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> > > > - amdgpu_ucode_init_bo(adev);
> > > > -
> > > > ret = hwmgr_hw_init(hwmgr);
> > > >
> > > > if (ret)
> > > > @@ -275,7 +272,16 @@ static int pp_set_clockgating_state(void
> > > > *handle,
> > > >
> > > > static int pp_dpm_load_fw(void *handle) {
> > > > - return 0;
> > > > + struct pp_hwmgr *hwmgr = handle;
> > > > + int ret = 0;
> > > > +
> > > > + if (!hwmgr || !hwmgr->smumgr_funcs)
> > > > + return -EINVAL;
> > > > +
> > > > + if (hwmgr->smumgr_funcs->request_smu_load_fw)
> > > > + ret =
> > > > + hwmgr->smumgr_funcs->request_smu_load_fw(hwmgr);
> > > > +
> > > > + return ret;
> > > > }
> > > >
> > > > static int pp_dpm_fw_loading_complete(void *handle) diff --git
> > > > a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > > index b6b62a7..ffd7d78 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > > > @@ -310,8 +310,6 @@ static int fiji_start_smu(struct pp_hwmgr
> *hwmgr)
> > > > offsetof(SMU73_Firmware_Header, SoftRegisters),
> > > > &(priv->smu7_data.soft_regs_start),
> > > > 0x40000);
> > > >
> > > > - result = smu7_request_smu_load_fw(hwmgr);
> > > > -
> > > > return result;
> > > > }
> > > >
> > > > @@ -2643,7 +2641,7 @@ static int fiji_update_dpm_settings(struct
> > > pp_hwmgr *hwmgr,
> > > > .smu_fini = &smu7_smu_fini,
> > > > .start_smu = &fiji_start_smu,
> > > > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > > > - .request_smu_load_fw = &smu7_reload_firmware,
> > > > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > > > .request_smu_load_specific_fw = NULL,
> > > > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > > > .send_msg_to_smc_with_parameter =
> > > > &smu7_send_msg_to_smc_with_parameter,
> > > > diff --git
> a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > > index 73aa368..68a4836 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > > > @@ -232,27 +232,24 @@ static int
> > > > iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
> > > >
> > > > static int iceland_start_smu(struct pp_hwmgr *hwmgr) {
> > > > - int result;
> > > > -
> > > > - result = iceland_smu_upload_firmware_image(hwmgr);
> > > > - if (result)
> > > > - return result;
> > > > - result = iceland_smu_start_smc(hwmgr);
> > > > - if (result)
> > > > - return result;
> > > > + struct iceland_smumgr *priv = hwmgr->smu_backend;
> > > > + int result = 0;
> > > >
> > > > if (!smu7_is_smc_ram_running(hwmgr)) {
> > > > - pr_info("smu not running, upload firmware again \n");
> > > > result = iceland_smu_upload_firmware_image(hwmgr);
> > > > if (result)
> > > > return result;
> > > >
> > > > - result = iceland_smu_start_smc(hwmgr);
> > > > - if (result)
> > > > - return result;
> > > > + iceland_smu_start_smc(hwmgr);
> > > > }
> > > > + /* Setup SoftRegsStart here for register lookup in case
> > > > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> > > executed
> > > > + */
> > > >
> > > > - result = smu7_request_smu_load_fw(hwmgr);
> > > > + smu7_read_smc_sram_dword(hwmgr,
> > > > + SMU71_FIRMWARE_HEADER_LOCATION +
> > > > + offsetof(SMU71_Firmware_Header, SoftRegisters),
> > > > + &(priv->smu7_data.soft_regs_start),
> > > > + 0x40000);
> > > >
> > > > return result;
> > > > }
> > > > @@ -2662,7 +2659,7 @@ static bool iceland_is_dpm_running(struct
> > > pp_hwmgr *hwmgr)
> > > > .smu_fini = &smu7_smu_fini,
> > > > .start_smu = &iceland_start_smu,
> > > > .check_fw_load_finish = &smu7_check_fw_load_finish,
> > > > - .request_smu_load_fw = &smu7_reload_firmware,
> > > > + .request_smu_load_fw = &smu7_request_smu_load_fw,
> > > > .request_smu_load_specific_fw =
> > > &iceland_request_smu_load_specific_fw,
> > > > .send_msg_to_smc = &smu7_send_msg_to_smc,
> > > > .send_msg_to_smc_with_parameter =
> > > > &smu7_send_msg_to_smc_with_parameter,
> > > > diff --git
> > > > a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > > index 872d382..2ad6ad9 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> > > > @@ -313,8 +313,6 @@ static int polaris10_start_smu(struct pp_hwmgr
> > > *hwmgr)
> > > > smu7_read_smc_sram_dword(hwmgr,
> > > SMU7_FIRMWARE_HEADER_LOCATION +
> offsetof(SMU74_Firmware_Header,
> > > SoftRegisters),
> > > >
> > > > &(smu_data->smu7_data.soft_regs_start), 0x40000);
> > > >
> > > > - result = smu7_request_smu_load_fw(hwmgr);
> > > > -
> > > > return result;
> > > > }
> > > >
> > > > @@ -2478,7 +2476,7 @@ static int
> > > > polaris10_update_dpm_settings(struct
> > > pp_hwmgr *hwmgr,
> > > > .smu_fini = smu7_smu_fini,
> > > > .start_smu = polaris10_start_smu,
> > > > .check_fw_load_finish = smu7_check_fw_load_finish,
> > > > - .request_smu_load_fw = smu7_reload_firmware,
> > > > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > > > .request_smu_load_specific_fw = NULL,
> > > > .send_msg_to_smc = smu7_send_msg_to_smc,
> > > > .send_msg_to_smc_with_parameter =
> > > > smu7_send_msg_to_smc_with_parameter,
> > > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > > index 10eb967..edfb061 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> > > > @@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct
> > > pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_
> > > > return 0;
> > > > }
> > > >
> > > > -/* Convert the firmware type to SMU type mask. For MEC, we need
> > > > to check all MEC related type */
> > > > -
> > > > -static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type) -
> {
> > > > - uint32_t result = 0;
> > > > -
> > > > - switch (fw_type) {
> > > > - case UCODE_ID_SDMA0:
> > > > - result = UCODE_ID_SDMA0_MASK;
> > > > - break;
> > > > - case UCODE_ID_SDMA1:
> > > > - result = UCODE_ID_SDMA1_MASK;
> > > > - break;
> > > > - case UCODE_ID_CP_CE:
> > > > - result = UCODE_ID_CP_CE_MASK;
> > > > - break;
> > > > - case UCODE_ID_CP_PFP:
> > > > - result = UCODE_ID_CP_PFP_MASK;
> > > > - break;
> > > > - case UCODE_ID_CP_ME:
> > > > - result = UCODE_ID_CP_ME_MASK;
> > > > - break;
> > > > - case UCODE_ID_CP_MEC:
> > > > - case UCODE_ID_CP_MEC_JT1:
> > > > - case UCODE_ID_CP_MEC_JT2:
> > > > - result = UCODE_ID_CP_MEC_MASK;
> > > > - break;
> > > > - case UCODE_ID_RLC_G:
> > > > - result = UCODE_ID_RLC_G_MASK;
> > > > - break;
> > > > - default:
> > > > - pr_info("UCode type is out of range! \n");
> > > > - result = 0;
> > > > - }
> > > > -
> > > > - return result;
> > > > -}
> > > > -
> > > > static int smu7_populate_single_firmware_entry(struct pp_hwmgr
> > > *hwmgr,
> > > > uint32_t fw_type,
> > > > struct SMU_Entry
> > > > *entry) @@ -381,6 +343,11 @@ int smu7_request_smu_load_fw(struct
> > > pp_hwmgr *hwmgr)
> > > > uint32_t fw_to_load;
> > > > int r = 0;
> > > >
> > > > + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> > > > + pr_err("smu not running \n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > if (smu_data->soft_regs_start)
> > > > cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> > > > smu_data->soft_regs_start
> > > > + smum_get_offsetof(hwmgr, @@ -462,10 +429,13 @@ int
> > > smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> > > > smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data-
> > > >header_buffer.mc_addr));
> > > > smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > > PPSMC_MSG_DRV_DRAM_ADDR_LO,
> > > > lower_32_bits(smu_data->header_buffer.mc_addr));
> > > >
> > > > - if (smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > PPSMC_MSG_LoadUcodes, fw_to_load))
> > > > - pr_err("Fail to Request SMU Load uCode");
> > > > + smu7_send_msg_to_smc_with_parameter(hwmgr,
> > > > + PPSMC_MSG_LoadUcodes, fw_to_load);
> > > >
> > > > - return r;
> > > > + r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
> > > > + if (!r)
> > > > + return 0;
> > > > +
> > > > + pr_err("SMU load firmware failed\n");
> > > >
> > > > failed:
> > > > kfree(smu_data->toc);
> > > > @@ -477,20 +447,15 @@ int smu7_request_smu_load_fw(struct
> > > pp_hwmgr
> > > > *hwmgr) int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr,
> > > >uint32_t fw_type) {
> > > > struct smu7_smumgr *smu_data = (struct smu7_smumgr
> > > >*)(hwmgr- smu_backend);
> > > > - uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
> > > > uint32_t ret;
> > > >
> > > > ret = phm_wait_on_indirect_register(hwmgr,
> mmSMC_IND_INDEX_11,
> > > > smu_data->soft_regs_start
> > > > +
> > > smum_get_offsetof(hwmgr,
> > > > SMU_SoftRegisters, UcodeLoadStatus),
> > > > - fw_mask, fw_mask);
> > > > + fw_type, fw_type);
> > > > return ret;
> > > > }
> > > >
> > > > -int smu7_reload_firmware(struct pp_hwmgr *hwmgr) -{
> > > > - return hwmgr->smumgr_funcs->start_smu(hwmgr);
> > > > -}
> > > >
> > > > static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
> > > > uint32_t length, uint32_t *src, uint32_t limit) { diff --git
> > > > a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > > index 01f0538f..10c8ceb 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> > > > @@ -73,9 +73,8 @@ int smu7_read_smc_sram_dword(struct
> pp_hwmgr
> > > *hwmgr,
> > > > uint32_t smc_addr, int smu7_write_smc_sram_dword(struct
> pp_hwmgr
> > > *hwmgr, uint32_t smc_addr,
> > > > uint32_t value,
> > > > uint32_t limit);
> > > >
> > > > -int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr); int
> > > > smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t
> > > > fw_type); -int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
> > > > +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
> > > > int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
> int
> > > > smu7_init(struct pp_hwmgr *hwmgr); int smu7_smu_fini(struct
> > > > pp_hwmgr *hwmgr); diff --git
> > > > a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > > index 7a4c425..90f5f30 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
> > > > @@ -658,6 +658,8 @@ static int smu8_request_smu_load_fw(struct
> > > > pp_hwmgr *hwmgr) {
> > > > struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
> > > > uint32_t smc_address;
> > > > + uint32_t fw_to_check = 0;
> > > > + int ret;
> > > >
> > > > smu8_smu_populate_firmware_entries(hwmgr);
> > > >
> > > > @@ -684,28 +686,9 @@ static int smu8_request_smu_load_fw(struct
> > > pp_hwmgr *hwmgr)
> > > > smu8_send_msg_to_smc_with_parameter(hwmgr,
> > > PPSMC_MSG_ExecuteJob,
> > > >
> > > > smu8_smu->toc_entry_power_profiling_index);
> > > >
> > > > - return smu8_send_msg_to_smc_with_parameter(hwmgr,
> > > > + smu8_send_msg_to_smc_with_parameter(hwmgr,
> > > > PPSMC_MSG_ExecuteJob,
> > > >
> > > > smu8_smu->toc_entry_initialize_index);
> > > > -}
> > > > -
> > > > -static int smu8_start_smu(struct pp_hwmgr *hwmgr) -{
> > > > - int ret = 0;
> > > > - uint32_t fw_to_check = 0;
> > > > - struct amdgpu_device *adev = hwmgr->adev;
> > > > -
> > > > - uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > > > - SMU8_FIRMWARE_HEADER_LOCATION +
> > > > - offsetof(struct SMU8_Firmware_Header, Version);
> > > > -
> > > > -
> > > > - if (hwmgr == NULL || hwmgr->device == NULL)
> > > > - return -EINVAL;
> > > > -
> > > > - cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX,
> index);
> > > > - hwmgr->smu_version = cgs_read_register(hwmgr->device,
> > > mmMP0PUB_IND_DATA);
> > > > - adev->pm.fw_version = hwmgr->smu_version >> 8;
> > > >
> > > > fw_to_check = UCODE_ID_RLC_G_MASK |
> > > > UCODE_ID_SDMA0_MASK | @@ -719,8 +702,6 @@
> > > > static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > > > if (hwmgr->chip_id == CHIP_STONEY)
> > > > fw_to_check &= ~(UCODE_ID_SDMA1_MASK |
> > > > UCODE_ID_CP_MEC_JT2_MASK);
> > > >
> > > > - smu8_request_smu_load_fw(hwmgr);
> > > > -
> > > > ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
> > > > if (ret) {
> > > > pr_err("SMU firmware load failed\n"); @@ -734,6
> > > > +715,25 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> > > > return ret;
> > > > }
> > > >
> > > > +static int smu8_start_smu(struct pp_hwmgr *hwmgr) {
> > > > + struct amdgpu_device *adev = hwmgr->adev;
> > > > +
> > > > + uint32_t index = SMN_MP1_SRAM_START_ADDR +
> > > > + SMU8_FIRMWARE_HEADER_LOCATION +
> > > > + offsetof(struct SMU8_Firmware_Header,
> > > > + Version);
> > > > +
> > > > +
> > > > + if (hwmgr == NULL || hwmgr->device == NULL)
> > > > + return -EINVAL;
> > > > +
> > > > + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX,
> index);
> > > > + hwmgr->smu_version = cgs_read_register(hwmgr->device,
> > > mmMP0PUB_IND_DATA);
> > > > + adev->pm.fw_version = hwmgr->smu_version >> 8;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int smu8_smu_init(struct pp_hwmgr *hwmgr) {
> > > > int ret = 0;
> > > > @@ -876,7 +876,7 @@ static bool smu8_is_dpm_running(struct
> > > pp_hwmgr *hwmgr)
> > > > .smu_fini = smu8_smu_fini,
> > > > .start_smu = smu8_start_smu,
> > > > .check_fw_load_finish = smu8_check_fw_load_finish,
> > > > - .request_smu_load_fw = NULL,
> > > > + .request_smu_load_fw = smu8_request_smu_load_fw,
> > > > .request_smu_load_specific_fw = NULL,
> > > > .get_argument = smu8_get_argument,
> > > > .send_msg_to_smc = smu8_send_msg_to_smc, diff --git
> > > > a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > > index ae8378e..d8f1ca2 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > > > @@ -192,7 +192,8 @@ static int
> > > > tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
> > > >
> > > > static int tonga_start_smu(struct pp_hwmgr *hwmgr) {
> > > > - int result;
> > > > + struct tonga_smumgr *priv = hwmgr->smu_backend;
> > > > + int result = 0;
> > > >
> > > > /* Only start SMC if SMC RAM is not running */
> > > > if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { @@
> > > > -209,7 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr
> *hwmgr)
> > > > }
> > > > }
> > > >
> > > > - result = smu7_request_smu_load_fw(hwmgr);
> > > > + /* Setup SoftRegsStart here for register lookup in case
> > > > + * DummyBackEnd is used and ProcessFirmwareHeader is not
> > > executed
> > > > + */
> > > > +
> > > > + smu7_read_smc_sram_dword(hwmgr,
> > > > + SMU72_FIRMWARE_HEADER_LOCATION +
> > > > + offsetof(SMU72_Firmware_Header, SoftRegisters),
> > > > + &(priv->smu7_data.soft_regs_start),
> > > > + 0x40000);
> > > >
> > > > return result;
> > > > }
> > > > diff --git
> a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > > b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > > index 3d415fa..71e376f 100644
> > > > --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
> > > > @@ -218,8 +218,6 @@ static int vegam_start_smu(struct pp_hwmgr
> > > *hwmgr)
> > > > &(smu_data->smu7_data.soft_regs_start),
> > > > 0x40000);
> > > >
> > > > - result = smu7_request_smu_load_fw(hwmgr);
> > > > -
> > > > return result;
> > > > }
> > > >
> > > > @@ -2280,7 +2278,7 @@ static int
> > > > vegam_thermal_setup_fan_table(struct
> > > pp_hwmgr *hwmgr)
> > > > .smu_fini = smu7_smu_fini,
> > > > .start_smu = vegam_start_smu,
> > > > .check_fw_load_finish = smu7_check_fw_load_finish,
> > > > - .request_smu_load_fw = smu7_reload_firmware,
> > > > + .request_smu_load_fw = smu7_request_smu_load_fw,
> > > > .request_smu_load_specific_fw = NULL,
> > > > .send_msg_to_smc = smu7_send_msg_to_smc,
> > > > .send_msg_to_smc_with_parameter =
> > > > smu7_send_msg_to_smc_with_parameter,
> > > > --
> > > > 1.9.1
> > > >
> > > > _______________________________________________
> > > > amd-gfx mailing list
> > > > amd-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-09-26 15:55 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-26 12:50 [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl Rex Zhu
[not found] ` <1537966249-30259-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 12:50 ` [PATCH 2/7] drm/amdgpu: Move out power up/down sdma out of smu Rex Zhu
[not found] ` <1537966249-30259-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 14:13 ` Alex Deucher
2018-09-26 12:50 ` [PATCH 3/7] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu Rex Zhu
[not found] ` <1537966249-30259-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 14:13 ` Alex Deucher
2018-09-26 12:50 ` [PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu Rex Zhu
[not found] ` <1537966249-30259-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 14:14 ` Alex Deucher
2018-09-26 12:50 ` [PATCH 5/7] drm/amd/pp: Remove useless code in smu Rex Zhu
[not found] ` <1537966249-30259-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 14:07 ` Alex Deucher
2018-09-26 12:50 ` [PATCH 6/7] drm/amd/pp: Export load_firmware interface Rex Zhu
[not found] ` <1537966249-30259-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-26 14:15 ` Alex Deucher
[not found] ` <CADnq5_PoCAk_k8EnFhWSvQER6ennOcDH6_N-uEe35xHTCnbNjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-26 15:21 ` Zhu, Rex
[not found] ` <BYAPR12MB2775099DFB71D6B0D40F4F69FB150-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-09-26 15:39 ` Alex Deucher
[not found] ` <CADnq5_Obr9=qhsJqjKDpJccjpW24a5yjg34+fYLyA9qrBYDDfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-26 15:55 ` Zhu, Rex
2018-09-26 12:50 ` [PATCH 7/7] drm/amdgpu: Change the gfx/sdma init/fini sequence Rex Zhu
2018-09-26 14:13 ` [PATCH 1/7] drm/amd/pp: Expose the smu support for SDMA PG cntl Alex Deucher
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