* [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0
@ 2018-10-09 6:31 tao.zhou1-5C7GfCeVMHo
[not found] ` <1539066696-20803-1-git-send-email-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: tao.zhou1-5C7GfCeVMHo @ 2018-10-09 6:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Tao Zhou, maciej.jesionowski-5C7GfCeVMHo, yukun1.li-5C7GfCeVMHo
From: Tao Zhou <tao.zhou1@amd.com>
Add CP_DEBUG register definition.
Change-Id: I38b0e5accc9ed2f516f409f1ffd88a9690356083
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index 4ce090d..529b37d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -2449,6 +2449,8 @@
#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
#define mmGB_EDC_MODE 0x107e
#define mmGB_EDC_MODE_BASE_IDX 0
+#define mmCP_DEBUG 0x107f
+#define mmCP_DEBUG_BASE_IDX 0
#define mmCP_CPF_DEBUG 0x1080
#define mmCP_PQ_WPTR_POLL_CNTL 0x1083
#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/amdgpu: fix CPDMA hang in PRT mode
[not found] ` <1539066696-20803-1-git-send-email-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-09 6:31 ` tao.zhou1-5C7GfCeVMHo
2018-10-09 7:38 ` [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0 Christian König
1 sibling, 0 replies; 3+ messages in thread
From: tao.zhou1-5C7GfCeVMHo @ 2018-10-09 6:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Tao Zhou, maciej.jesionowski-5C7GfCeVMHo, yukun1.li-5C7GfCeVMHo
From: Tao Zhou <tao.zhou1@amd.com>
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX
Affected ASICs: Vega10 Vega12 Raven
Change-Id: I1029c9cf39c82f8415af77012cb289b565ba996b
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Yukun.Li <yukun1.li@amd.com>
Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d6b5069..e61f6a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -133,7 +133,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
};
static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
@@ -173,7 +176,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
};
static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
@@ -247,7 +253,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
};
static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0
[not found] ` <1539066696-20803-1-git-send-email-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2018-10-09 6:31 ` [PATCH 2/2] drm/amdgpu: fix CPDMA hang in PRT mode tao.zhou1-5C7GfCeVMHo
@ 2018-10-09 7:38 ` Christian König
1 sibling, 0 replies; 3+ messages in thread
From: Christian König @ 2018-10-09 7:38 UTC (permalink / raw)
To: tao.zhou1-5C7GfCeVMHo, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: maciej.jesionowski-5C7GfCeVMHo, yukun1.li-5C7GfCeVMHo
Am 09.10.2018 um 08:31 schrieb tao.zhou1@amd.com:
> From: Tao Zhou <tao.zhou1@amd.com>
>
> Add CP_DEBUG register definition.
>
> Change-Id: I38b0e5accc9ed2f516f409f1ffd88a9690356083
> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Christian König <christian.koenig@amd.com> for the series.
> ---
> drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> index 4ce090d..529b37d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> @@ -2449,6 +2449,8 @@
> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
> #define mmGB_EDC_MODE 0x107e
> #define mmGB_EDC_MODE_BASE_IDX 0
> +#define mmCP_DEBUG 0x107f
> +#define mmCP_DEBUG_BASE_IDX 0
> #define mmCP_CPF_DEBUG 0x1080
> #define mmCP_PQ_WPTR_POLL_CNTL 0x1083
> #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-10-09 7:38 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-09 6:31 [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0 tao.zhou1-5C7GfCeVMHo
[not found] ` <1539066696-20803-1-git-send-email-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2018-10-09 6:31 ` [PATCH 2/2] drm/amdgpu: fix CPDMA hang in PRT mode tao.zhou1-5C7GfCeVMHo
2018-10-09 7:38 ` [PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0 Christian König
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.