* [Qemu-devel] [PATCH 0/3] target/mips: Add two CP0 related comments and update mailmap
@ 2018-10-15 10:50 Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Aleksandar Markovic @ 2018-10-15 10:50 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
This series contains three cosmetic changes that do not affect any
QEMU feature, but are still hopefully helpful for development.
Aleksandar Markovic (3):
target/mips: Add a comment with an overview of CP0 registers
target/mips: Add a comment before each CP0 register section in cpu.h
mailmap: Add an item for Yongbok Kim
.mailmap | 1 +
target/mips/cpu.h | 197 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 198 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers
2018-10-15 10:50 [Qemu-devel] [PATCH 0/3] target/mips: Add two CP0 related comments and update mailmap Aleksandar Markovic
@ 2018-10-15 10:50 ` Aleksandar Markovic
2018-10-15 14:27 ` Stefan Markovic
2018-10-15 23:01 ` Philippe Mathieu-Daudé
2018-10-15 10:50 ` [Qemu-devel] [PATCH 2/3] target/mips: Add a comment before each CP0 register section in cpu.h Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
2 siblings, 2 replies; 7+ messages in thread
From: Aleksandar Markovic @ 2018-10-15 10:50 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..cd54073 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -195,6 +195,115 @@ struct CPUMIPSState {
#define MSAIR_ProcID 8
#define MSAIR_Rev 0
+/*
+ * Summary of CP0 registers
+ * ========================
+ *
+ *
+ * Register 0 Register 1 Register 2 Register 3
+ * ---------- ---------- ---------- ----------
+ *
+ * 0 Index Random EntryLo0 EntryLo1
+ * 1 MVPControl VPEControl TCStatus GlobalNumber
+ * 2 MVPConf0 VPEConf0 TCBind
+ * 3 MVPConf1 VPEConf1 TCRestart
+ * 4 VPControl YQMask TCHalt
+ * 5 VPESchedule TCContext
+ * 6 VPEScheFBack TCSchedule
+ * 7 VPEOpt TCScheFBack TCOpt
+ *
+ *
+ * Register 4 Register 5 Register 6 Register 7
+ * ---------- ---------- ---------- ----------
+ *
+ * 0 Context PageMask Wired HWREna
+ * 1 ContextConfig PageGrain SRSConf0
+ * 2 UserLocal SegCtl0 SRSConf1
+ * 3 XContextConfig SegCtl1 SRSConf2
+ * 4 DebugContextID SegCtl2 SRSConf3
+ * 5 MemoryMapID PWBase SRSConf4
+ * 6 PWField PWCtl
+ * 7 PWSize
+ *
+ *
+ * Register 8 Register 9 Register 10 Register 11
+ * ---------- ---------- ----------- -----------
+ *
+ * 0 BadVAddr Count EntryHi Compare
+ * 1 BadInstr
+ * 2 BadInstrP
+ * 3 BadInstrX
+ * 4 GuestCtl1 GuestCtl0Ext
+ * 5 GuestCtl2
+ * 6 GuestCtl3
+ * 7
+ *
+ *
+ * Register 12 Register 13 Register 14 Register 15
+ * ----------- ----------- ----------- -----------
+ *
+ * 0 Status Cause EPC PRId
+ * 1 IntCtl EBase
+ * 2 SRSCtl NestedEPC CDMMBase
+ * 3 SRSMap CMGCRBase
+ * 4 View_IPL View_RIPL BEVVA
+ * 5 SRSMap2 NestedExc
+ * 6 GuestCtl0
+ * 7 GTOffset
+ *
+ *
+ * Register 16 Register 17 Register 18 Register 19
+ * ----------- ----------- ----------- -----------
+ *
+ * 0 Config LLAddr WatchLo WatchHi
+ * 1 Config1 MAAR WatchLo WatchHi
+ * 2 Config2 MAARI WatchLo WatchHi
+ * 3 Config3 WatchLo WatchHi
+ * 4 Config4 WatchLo WatchHi
+ * 5 Config5 WatchLo WatchHi
+ * 6 WatchLo WatchHi
+ * 7 WatchLo WatchHi
+ *
+ *
+ * Register 20 Register 21 Register 22 Register 23
+ * ----------- ----------- ----------- -----------
+ *
+ * 0 XContext Debug
+ * 1 TraceControl
+ * 2 TraceControl2
+ * 3 UserTraceData1
+ * 4 TraceIBPC
+ * 5 TraceDBPC
+ * 6 Debug2
+ * 7
+ *
+ *
+ * Register 24 Register 25 Register 26 Register 27
+ * ----------- ----------- ----------- -----------
+ *
+ * 0 DEPC PerfCnt ErrCtl CacheErr
+ * 1 PerfCnt
+ * 2 TraceControl3 PerfCnt
+ * 3 UserTraceData2 PerfCnt
+ * 4 PerfCnt
+ * 5 PerfCnt
+ * 6 PerfCnt
+ * 7 PerfCnt
+ *
+ *
+ * Register 28 Register 29 Register 30 Register 31
+ * ----------- ----------- ----------- -----------
+ *
+ * 0 DataLo DataHi ErrorEPC DESAVE
+ * 1 TagLo TagHi
+ * 2 DataLo DataHi KScratch<n>
+ * 3 TagLo TagHi KScratch<n>
+ * 4 DataLo DataHi KScratch<n>
+ * 5 TagLo TagHi KScratch<n>
+ * 6 DataLo DataHi KScratch<n>
+ * 7 TagLo TagHi KScratch<n>
+ *
+ */
int32_t CP0_Index;
/* CP0_MVP* are per MVP registers. */
int32_t CP0_VPControl;
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 2/3] target/mips: Add a comment before each CP0 register section in cpu.h
2018-10-15 10:50 [Qemu-devel] [PATCH 0/3] target/mips: Add two CP0 related comments and update mailmap Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
@ 2018-10-15 10:50 ` Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
2 siblings, 0 replies; 7+ messages in thread
From: Aleksandar Markovic @ 2018-10-15 10:50 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment before each CP0 register section in CPUMIPSState
definition, thus visually separating these sections.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index cd54073..37703ea 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -304,10 +304,16 @@ struct CPUMIPSState {
* 7 TagLo TagHi KScratch<n>
*
*/
+/*
+ * CP0 Register 0
+ */
int32_t CP0_Index;
/* CP0_MVP* are per MVP registers. */
int32_t CP0_VPControl;
#define CP0VPCtl_DIS 0
+/*
+ * CP0 Register 1
+ */
int32_t CP0_Random;
int32_t CP0_VPEControl;
#define CP0VPECo_YSI 21
@@ -348,7 +354,13 @@ struct CPUMIPSState {
#define CP0VPEOpt_DWX2 2
#define CP0VPEOpt_DWX1 1
#define CP0VPEOpt_DWX0 0
+/*
+ * CP0 Register 2
+ */
uint64_t CP0_EntryLo0;
+/*
+ * CP0 Register 3
+ */
uint64_t CP0_EntryLo1;
#if defined(TARGET_MIPS64)
# define CP0EnLo_RI 63
@@ -359,8 +371,14 @@ struct CPUMIPSState {
#endif
int32_t CP0_GlobalNumber;
#define CP0GN_VPId 0
+/*
+ * CP0 Register 4
+ */
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+/*
+ * CP0 Register 5
+ */
int32_t CP0_PageMask;
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
@@ -398,6 +416,9 @@ struct CPUMIPSState {
#define CP0SC2_XR 56
#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
+/*
+ * CP0 Register 6
+ */
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
@@ -428,16 +449,34 @@ struct CPUMIPSState {
#define CP0SRSC4_SRS15 20
#define CP0SRSC4_SRS14 10
#define CP0SRSC4_SRS13 0
+/*
+ * CP0 Register 7
+ */
int32_t CP0_HWREna;
+/*
+ * CP0 Register 8
+ */
target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
uint32_t CP0_BadInstrX;
+/*
+ * CP0 Register 9
+ */
int32_t CP0_Count;
+/*
+ * CP0 Register 10
+ */
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
target_ulong CP0_EntryHi_ASID_mask;
+/*
+ * CP0 Register 11
+ */
int32_t CP0_Compare;
+/*
+ * CP0 Register 12
+ */
int32_t CP0_Status;
#define CP0St_CU3 31
#define CP0St_CU2 30
@@ -479,6 +518,9 @@ struct CPUMIPSState {
#define CP0SRSMap_SSV2 8
#define CP0SRSMap_SSV1 4
#define CP0SRSMap_SSV0 0
+/*
+ * CP0 Register 13
+ */
int32_t CP0_Cause;
#define CP0Ca_BD 31
#define CP0Ca_TI 30
@@ -490,12 +532,21 @@ struct CPUMIPSState {
#define CP0Ca_IP 8
#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC 2
+/*
+ * CP0 Register 14
+ */
target_ulong CP0_EPC;
+/*
+ * CP0 Register 15
+ */
int32_t CP0_PRid;
target_ulong CP0_EBase;
target_ulong CP0_EBaseWG_rw_bitmask;
#define CP0EBase_WG 11
target_ulong CP0_CMGCRBase;
+/*
+ * CP0 Register 16
+ */
int32_t CP0_Config0;
#define CP0C0_M 31
#define CP0C0_K23 28 /* 30..28 */
@@ -612,6 +663,9 @@ struct CPUMIPSState {
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
int32_t CP0_MAARI;
/* XXX: Maybe make LLAddr per-TC? */
+/*
+ * CP0 Register 17
+ */
uint64_t lladdr;
target_ulong llval;
target_ulong llnewval;
@@ -620,11 +674,23 @@ struct CPUMIPSState {
target_ulong llreg;
uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
+/*
+ * CP0 Register 18
+ */
target_ulong CP0_WatchLo[8];
+/*
+ * CP0 Register 19
+ */
int32_t CP0_WatchHi[8];
#define CP0WH_ASID 16
+/*
+ * CP0 Register 20
+ */
target_ulong CP0_XContext;
int32_t CP0_Framemask;
+/*
+ * CP0 Register 23
+ */
int32_t CP0_Debug;
#define CP0DB_DBD 31
#define CP0DB_DM 30
@@ -644,18 +710,40 @@ struct CPUMIPSState {
#define CP0DB_DDBL 2
#define CP0DB_DBp 1
#define CP0DB_DSS 0
+/*
+ * CP0 Register 24
+ */
target_ulong CP0_DEPC;
+/*
+ * CP0 Register 25
+ */
int32_t CP0_Performance0;
+/*
+ * CP0 Register 26
+ */
int32_t CP0_ErrCtl;
#define CP0EC_WST 29
#define CP0EC_SPR 28
#define CP0EC_ITC 26
+/*
+ * CP0 Register 28
+ */
uint64_t CP0_TagLo;
int32_t CP0_DataLo;
+/*
+ * CP0 Register 29
+ */
int32_t CP0_TagHi;
int32_t CP0_DataHi;
+/*
+ * CP0 Register 30
+ */
target_ulong CP0_ErrorEPC;
+/*
+ * CP0 Register 31
+ */
int32_t CP0_DESAVE;
+
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim
2018-10-15 10:50 [Qemu-devel] [PATCH 0/3] target/mips: Add two CP0 related comments and update mailmap Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 2/3] target/mips: Add a comment before each CP0 register section in cpu.h Aleksandar Markovic
@ 2018-10-15 10:50 ` Aleksandar Markovic
2018-10-15 14:31 ` Stefan Markovic
2 siblings, 1 reply; 7+ messages in thread
From: Aleksandar Markovic @ 2018-10-15 10:50 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Yongbok Kim used two email adresses for QEMU contributions -
his company changed its ownership/name.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 2c2b9b1..0d886a1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -12,6 +12,7 @@ Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
+Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
@ 2018-10-15 14:27 ` Stefan Markovic
2018-10-15 23:01 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 7+ messages in thread
From: Stefan Markovic @ 2018-10-15 14:27 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, amarkovic, pjovanovic
On 15.10.2018. 12:50, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add a comment with an overview of CP0 registers close to the
> definition of their corresponding fields in CPUMIPSState.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/cpu.h | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 28af4d1..cd54073 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -195,6 +195,115 @@ struct CPUMIPSState {
> #define MSAIR_ProcID 8
> #define MSAIR_Rev 0
>
> +/*
> + * Summary of CP0 registers
> + * ========================
> + *
> + *
> + * Register 0 Register 1 Register 2 Register 3
> + * ---------- ---------- ---------- ----------
> + *
> + * 0 Index Random EntryLo0 EntryLo1
> + * 1 MVPControl VPEControl TCStatus GlobalNumber
> + * 2 MVPConf0 VPEConf0 TCBind
> + * 3 MVPConf1 VPEConf1 TCRestart
> + * 4 VPControl YQMask TCHalt
> + * 5 VPESchedule TCContext
> + * 6 VPEScheFBack TCSchedule
> + * 7 VPEOpt TCScheFBack TCOpt
> + *
> + *
> + * Register 4 Register 5 Register 6 Register 7
> + * ---------- ---------- ---------- ----------
> + *
> + * 0 Context PageMask Wired HWREna
> + * 1 ContextConfig PageGrain SRSConf0
> + * 2 UserLocal SegCtl0 SRSConf1
> + * 3 XContextConfig SegCtl1 SRSConf2
> + * 4 DebugContextID SegCtl2 SRSConf3
> + * 5 MemoryMapID PWBase SRSConf4
> + * 6 PWField PWCtl
> + * 7 PWSize
> + *
> + *
> + * Register 8 Register 9 Register 10 Register 11
> + * ---------- ---------- ----------- -----------
> + *
> + * 0 BadVAddr Count EntryHi Compare
> + * 1 BadInstr
> + * 2 BadInstrP
> + * 3 BadInstrX
> + * 4 GuestCtl1 GuestCtl0Ext
> + * 5 GuestCtl2
> + * 6 GuestCtl3
> + * 7
> + *
> + *
> + * Register 12 Register 13 Register 14 Register 15
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 Status Cause EPC PRId
> + * 1 IntCtl EBase
> + * 2 SRSCtl NestedEPC CDMMBase
> + * 3 SRSMap CMGCRBase
> + * 4 View_IPL View_RIPL BEVVA
> + * 5 SRSMap2 NestedExc
> + * 6 GuestCtl0
> + * 7 GTOffset
> + *
> + *
> + * Register 16 Register 17 Register 18 Register 19
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 Config LLAddr WatchLo WatchHi
> + * 1 Config1 MAAR WatchLo WatchHi
> + * 2 Config2 MAARI WatchLo WatchHi
> + * 3 Config3 WatchLo WatchHi
> + * 4 Config4 WatchLo WatchHi
> + * 5 Config5 WatchLo WatchHi
> + * 6 WatchLo WatchHi
> + * 7 WatchLo WatchHi
> + *
> + *
> + * Register 20 Register 21 Register 22 Register 23
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 XContext Debug
> + * 1 TraceControl
> + * 2 TraceControl2
> + * 3 UserTraceData1
> + * 4 TraceIBPC
> + * 5 TraceDBPC
> + * 6 Debug2
> + * 7
> + *
> + *
> + * Register 24 Register 25 Register 26 Register 27
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 DEPC PerfCnt ErrCtl CacheErr
> + * 1 PerfCnt
> + * 2 TraceControl3 PerfCnt
> + * 3 UserTraceData2 PerfCnt
> + * 4 PerfCnt
> + * 5 PerfCnt
> + * 6 PerfCnt
> + * 7 PerfCnt
> + *
> + *
> + * Register 28 Register 29 Register 30 Register 31
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 DataLo DataHi ErrorEPC DESAVE
> + * 1 TagLo TagHi
> + * 2 DataLo DataHi KScratch<n>
> + * 3 TagLo TagHi KScratch<n>
> + * 4 DataLo DataHi KScratch<n>
> + * 5 TagLo TagHi KScratch<n>
> + * 6 DataLo DataHi KScratch<n>
> + * 7 TagLo TagHi KScratch<n>
> + *
> + */
> int32_t CP0_Index;
> /* CP0_MVP* are per MVP registers. */
> int32_t CP0_VPControl;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim
2018-10-15 10:50 ` [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
@ 2018-10-15 14:31 ` Stefan Markovic
0 siblings, 0 replies; 7+ messages in thread
From: Stefan Markovic @ 2018-10-15 14:31 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, amarkovic, pjovanovic
On 15.10.2018. 12:50, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Yongbok Kim used two email adresses for QEMU contributions -
> his company changed its ownership/name.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> .mailmap | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> diff --git a/.mailmap b/.mailmap
> index 2c2b9b1..0d886a1 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -12,6 +12,7 @@ Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
> James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
> Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
> Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
> +Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
> Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
> Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
> Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
2018-10-15 14:27 ` Stefan Markovic
@ 2018-10-15 23:01 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-15 23:01 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: smarkovic, pjovanovic, amarkovic, aurelien
Hi Aleksandar,
On 15/10/2018 12:50, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add a comment with an overview of CP0 registers close to the
> definition of their corresponding fields in CPUMIPSState.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/cpu.h | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 28af4d1..cd54073 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -195,6 +195,115 @@ struct CPUMIPSState {
> #define MSAIR_ProcID 8
> #define MSAIR_Rev 0
>
> +/*
> + * Summary of CP0 registers
"since MIPS32/MIPS64 release 1"? Previous have different registers.
> + * ========================
> + *
> + *
> + * Register 0 Register 1 Register 2 Register 3
> + * ---------- ---------- ---------- ----------
> + *
> + * 0 Index Random EntryLo0 EntryLo1
> + * 1 MVPControl VPEControl TCStatus GlobalNumber
> + * 2 MVPConf0 VPEConf0 TCBind
> + * 3 MVPConf1 VPEConf1 TCRestart
> + * 4 VPControl YQMask TCHalt
> + * 5 VPESchedule TCContext
> + * 6 VPEScheFBack TCSchedule
> + * 7 VPEOpt TCScheFBack TCOpt
> + *
> + *
> + * Register 4 Register 5 Register 6 Register 7
> + * ---------- ---------- ---------- ----------
> + *
> + * 0 Context PageMask Wired HWREna
> + * 1 ContextConfig PageGrain SRSConf0
> + * 2 UserLocal SegCtl0 SRSConf1
> + * 3 XContextConfig SegCtl1 SRSConf2
> + * 4 DebugContextID SegCtl2 SRSConf3
> + * 5 MemoryMapID PWBase SRSConf4
> + * 6 PWField PWCtl
> + * 7 PWSize
> + *
> + *
> + * Register 8 Register 9 Register 10 Register 11
> + * ---------- ---------- ----------- -----------
> + *
> + * 0 BadVAddr Count EntryHi Compare
> + * 1 BadInstr
> + * 2 BadInstrP
> + * 3 BadInstrX
> + * 4 GuestCtl1 GuestCtl0Ext
> + * 5 GuestCtl2
> + * 6 GuestCtl3
> + * 7
> + *
> + *
> + * Register 12 Register 13 Register 14 Register 15
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 Status Cause EPC PRId
> + * 1 IntCtl EBase
> + * 2 SRSCtl NestedEPC CDMMBase
> + * 3 SRSMap CMGCRBase
> + * 4 View_IPL View_RIPL BEVVA
> + * 5 SRSMap2 NestedExc
> + * 6 GuestCtl0
> + * 7 GTOffset
> + *
> + *
> + * Register 16 Register 17 Register 18 Register 19
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 Config LLAddr WatchLo WatchHi
> + * 1 Config1 MAAR WatchLo WatchHi
> + * 2 Config2 MAARI WatchLo WatchHi
> + * 3 Config3 WatchLo WatchHi
> + * 4 Config4 WatchLo WatchHi
> + * 5 Config5 WatchLo WatchHi
> + * 6 WatchLo WatchHi
> + * 7 WatchLo WatchHi
> + *
> + *
> + * Register 20 Register 21 Register 22 Register 23
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 XContext Debug
> + * 1 TraceControl
> + * 2 TraceControl2
> + * 3 UserTraceData1
> + * 4 TraceIBPC
> + * 5 TraceDBPC
> + * 6 Debug2
> + * 7
> + *
> + *
> + * Register 24 Register 25 Register 26 Register 27
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 DEPC PerfCnt ErrCtl CacheErr
> + * 1 PerfCnt
> + * 2 TraceControl3 PerfCnt
> + * 3 UserTraceData2 PerfCnt
> + * 4 PerfCnt
> + * 5 PerfCnt
> + * 6 PerfCnt
> + * 7 PerfCnt
> + *
> + *
> + * Register 28 Register 29 Register 30 Register 31
> + * ----------- ----------- ----------- -----------
> + *
> + * 0 DataLo DataHi ErrorEPC DESAVE
> + * 1 TagLo TagHi
> + * 2 DataLo DataHi KScratch<n>
> + * 3 TagLo TagHi KScratch<n>
> + * 4 DataLo DataHi KScratch<n>
> + * 5 TagLo TagHi KScratch<n>
> + * 6 DataLo DataHi KScratch<n>
> + * 7 TagLo TagHi KScratch<n>
> + *
> + */
> int32_t CP0_Index;
> /* CP0_MVP* are per MVP registers. */
> int32_t CP0_VPControl;
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-10-15 23:02 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-15 10:50 [Qemu-devel] [PATCH 0/3] target/mips: Add two CP0 related comments and update mailmap Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
2018-10-15 14:27 ` Stefan Markovic
2018-10-15 23:01 ` Philippe Mathieu-Daudé
2018-10-15 10:50 ` [Qemu-devel] [PATCH 2/3] target/mips: Add a comment before each CP0 register section in cpu.h Aleksandar Markovic
2018-10-15 10:50 ` [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
2018-10-15 14:31 ` Stefan Markovic
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.