[Qemu-devel] [PATCH v5 00/14] Add limited MXU instruction support

[Aleksandar Markovic <aleksandar.markovic@rt-rk.com>]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

This patch set begins to add MXU instruction support for
MIPS emulation.

v4->v5:

  - added full decoding engine for MXU ASE
  - changes on aptn2, optn2, optn3 are now stand-alone patches
  - all patches on individual instructions are reworked to fit
    new decoding engine, and also cosmetically improved
  - rebased to the latest code

Aleksandar Markovic (2):
  target/mips: Add and integrate MXU decoding engine placeholder
  target/mips: Add MXU decoding engine

Craig Janeczek (12):
  target/mips: Introduce MXU registers
  target/mips: Define a bit for MXU in insn_flags
  target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2'
  target/mips: Add bit encoding for MXU operand getting patterns 'optn2'
  target/mips: Add bit encoding for MXU operand getting patterns 'optn3'
  target/mips: Add emulation of non-MXU MULL within MXU decoding engine
  target/mips: Add emulation of MXU instructions S32I2M and S32M2I
  target/mips: Add emulation of MXU instruction S8LDD
  target/mips: Add emulation of MXU instruction D16MUL
  target/mips: Add emulation of MXU instruction D16MAC
  target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
  target/mips: Add emulation of MXU instructions S32LDD and S32LDDR

 target/mips/cpu.h       |   10 +
 target/mips/mips-defs.h |    1 +
 target/mips/translate.c | 1979 +++++++++++++++++++++++++++++++++++++++++++----
 3 files changed, 1834 insertions(+), 156 deletions(-)

-- 
2.7.4