[PATCH v3 0/4] Enable Y210, Y212, Y216 formats for ICL

[PATCH v3 0/4] Enable Y210, Y212, Y216 formats for ICL

[Swati Sharma]

These patches enable packed format YUV422-Y210, Y212 and Y216
for 10, 12 and 16 bit respectively for ICL.

For user space component IGT
IGT needs libraries for Pixman and Cairo to support more than 8bpc.
Work going on from Maarten Lankhorst.

v2: addressed review comments of mahesh and alexandru
    hdr handling of these 64 bit pixel format not inscope 
    of this series

v3: addressed review comments of Juha-pekka(JP)

Vidya Srinivas (4):
  drm: Add Y210, Y212, Y216 format definitions and fourcc
  drm/i915/icl: Add Y210, Y212, Y216 plane control definitions
  drm/i915/icl: Preparations for enabling Y210, Y212, Y216 formats
  drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite
    planes

 drivers/gpu/drm/drm_fourcc.c         |  3 ++
 drivers/gpu/drm/i915/i915_reg.h      |  3 ++
 drivers/gpu/drm/i915/intel_display.c | 79 +++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_sprite.c  | 45 +++++++++++++++++++-
 include/uapi/drm/drm_fourcc.h        |  8 ++++
 5 files changed, 130 insertions(+), 8 deletions(-)

-- 
1.9.1

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[PATCH v3 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc

[Swati Sharma]

From: Vidya Srinivas <vidya.srinivas@intel.com>

The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.

Y210: Valid data occupies MSB 10 bits.
      LSB 6 bits are filled with zeroes.
Y212: Valid data occupies MSB 12 bits.
      LSB 4 bits are filled with zeroes.
Y216: Valid data occupies 16 bits,
      doesn't require any padding bits.

First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.

v2: is_yuv setted to true (mahesh)
    different order of yuv samples (mahesh): still update from
    hardware team pending
    change in comment (alexandru)

v3: change in patch comment (juha)
    change in fourcc_code comment (juha)
    different order of yuv samples needs to be defined for Y210/
    Y212/Y216 (update from h/w folks): not including in this patch,
    will do in other patch series (if reqd)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  | 3 +++
 include/uapi/drm/drm_fourcc.h | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90a1c84..667527b 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -225,6 +225,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 	};
 
 	unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 139632b..af1c900 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -153,6 +153,14 @@
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
 
 /*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
+#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
+/*
  * 2 plane RGB + A
  * index 0 = RGB plane, same format as the corresponding non _A8 format has
  * index 1 = A plane, [7:0] A
-- 
1.9.1

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[PATCH v3 2/4] drm/i915/icl: Add Y210, Y212, Y216 plane control definitions

[Swati Sharma]

From: Vidya Srinivas <vidya.srinivas@intel.com>

Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.

v3: no change

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507..cbb2917 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6506,6 +6506,9 @@ enum {
 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
+#define   PLANE_CTL_FORMAT_Y210			(1 << 23)
+#define   PLANE_CTL_FORMAT_Y212			(3 << 23)
+#define   PLANE_CTL_FORMAT_Y216			(5 << 23)
 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
-- 
1.9.1

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[PATCH v3 3/4] drm/i915/icl: Preparations for enabling Y210, Y212, Y216 formats

[Swati Sharma]

From: Vidya Srinivas <vidya.srinivas@intel.com>

v3: case handling checking INTEL_GEN(dev_priv) < 11 added for these 3
    new pixel formats (juha)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 36434c5..98f2939 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3565,6 +3565,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_Y210:
+		return PLANE_CTL_FORMAT_Y210;
+	case DRM_FORMAT_Y212:
+		return PLANE_CTL_FORMAT_Y212;
+	case DRM_FORMAT_Y216:
+		return PLANE_CTL_FORMAT_Y216;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -5022,6 +5028,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13474,6 +13483,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
 	case DRM_FORMAT_NV12:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
@@ -14632,6 +14644,15 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
+		if (INTEL_GEN(dev_priv) < 11) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 783fc0a..c831360 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1702,6 +1702,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
 	case DRM_FORMAT_NV12:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
-- 
1.9.1

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[PATCH v3 4/4] drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite planes

[Swati Sharma]

From: Vidya Srinivas <vidya.srinivas@intel.com>

In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.

v3: since support for planar formats on ICL was getting totally
    skipped, added support for the same in intel_display.c and
    intel_sprite.c. (juha)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_sprite.c  | 42 ++++++++++++++++++++++++--
 2 files changed, 92 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 98f2939..f83fbb4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -105,6 +105,42 @@
 	DRM_FORMAT_NV12,
 };
 
+static const uint32_t icl_primary_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
+static const uint32_t icl_pri_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
 static const uint64_t skl_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -13788,16 +13824,26 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
 		fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
 	}
 
+
 	if (INTEL_GEN(dev_priv) >= 9) {
 		primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
-						     PLANE_PRIMARY);
-
-		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+				PLANE_PRIMARY);
+
+		if (skl_plane_has_planar(dev_priv, pipe,
+					PLANE_PRIMARY)) {
+			if (INTEL_GEN(dev_priv) >= 11) {
+				intel_primary_formats = icl_primary_formats;
+				num_formats = ARRAY_SIZE(icl_primary_formats);
+			} else {
+				intel_primary_formats = skl_primary_formats;
+				num_formats = ARRAY_SIZE(skl_primary_formats);
+			}
+		} else if (INTEL_GEN(dev_priv) >= 11) {
+			intel_primary_formats = icl_pri_planar_formats;
+			num_formats = ARRAY_SIZE(icl_pri_planar_formats);
+		} else {
 			intel_primary_formats = skl_pri_planar_formats;
 			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
-		} else {
-			intel_primary_formats = skl_primary_formats;
-			num_formats = ARRAY_SIZE(skl_primary_formats);
 		}
 
 		if (primary->has_ccs)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index c831360..7d9b3e4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1564,6 +1564,36 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_NV12,
 };
 
+static uint32_t icl_plane_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
+static uint32_t icl_planar_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1822,8 +1852,16 @@ struct intel_plane *
 
 		if (skl_plane_has_planar(dev_priv, pipe,
 					 PLANE_SPRITE0 + plane)) {
-			plane_formats = skl_planar_formats;
-			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+			if (INTEL_GEN(dev_priv) >= 11) {
+				plane_formats = icl_planar_formats;
+				num_plane_formats = ARRAY_SIZE(icl_planar_formats);
+			} else {
+				plane_formats = skl_planar_formats;
+				num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+			}
+		} else if (INTEL_GEN(dev_priv) >= 11) {
+			plane_formats = icl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(icl_plane_formats);
 		} else {
 			plane_formats = skl_plane_formats;
 			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
-- 
1.9.1

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✗ Fi.CI.BAT: failure for Enable Y210, Y212, Y216 formats for ICL (rev3)

[Patchwork]

== Series Details ==

Series: Enable Y210, Y212, Y216 formats for ICL (rev3)
URL   : https://patchwork.freedesktop.org/series/48729/
State : failure

== Summary ==

Applying: drm: Add Y210, Y212, Y216 format definitions and fourcc
Applying: drm/i915/icl: Add Y210, Y212, Y216 plane control definitions
Applying: drm/i915/icl: Preparations for enabling Y210, Y212, Y216 formats
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/intel_display.c
M	drivers/gpu/drm/i915/intel_sprite.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_sprite.c
Auto-merging drivers/gpu/drm/i915/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.c
error: Failed to merge in the changes.
Patch failed at 0003 drm/i915/icl: Preparations for enabling Y210, Y212, Y216 formats
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH v3 2/4] drm/i915/icl: Add Y210, Y212, Y216 plane control definitions

[Juha-Pekka Heikkilä]

I did earlier give R-b for this patch. The patch anyway hasn't changed 
as those defines have not changed.

/Juha-Pekka

Swati Sharma kirjoitti 22.10.2018 klo 8.31:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> Added needed plane control flag definitions for Y210, Y212 and
> Y216 formats.
> 
> v3: no change
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a71c507..cbb2917 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6506,6 +6506,9 @@ enum {
>   #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>   #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
>   #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
> +#define   PLANE_CTL_FORMAT_Y210			(1 << 23)
> +#define   PLANE_CTL_FORMAT_Y212			(3 << 23)
> +#define   PLANE_CTL_FORMAT_Y216			(5 << 23)
>   #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
> 
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Re: [PATCH v3 4/4] drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite planes

[Juha-Pekka Heikkilä]

Swati Sharma kirjoitti 22.10.2018 klo 8.31:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> In this patch, a list for icl specific pixel formats is created
> in which Y210, Y212 and Y216 pixel formats are added along with
> legacy pixel formats for primary and sprite plane.
> 
> v3: since support for planar formats on ICL was getting totally
>      skipped, added support for the same in intel_display.c and
>      intel_sprite.c. (juha)
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++++++++++++++----
>   drivers/gpu/drm/i915/intel_sprite.c  | 42 ++++++++++++++++++++++++--
>   2 files changed, 92 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 98f2939..f83fbb4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -105,6 +105,42 @@
>   	DRM_FORMAT_NV12,
>   };
>   
> +static const uint32_t icl_primary_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
> +static const uint32_t icl_pri_planar_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
>   static const uint64_t skl_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -13788,16 +13824,26 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
>   		fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
>   	}
>   
> +
^^ stray newline?

The next if(){}else{} I would write separating gen11 from gen9 because 
you need both tables, primary_formats as well as pri_planar_formats, for 
gen11.

So, instead of having

if(>=gen9) {
   if(>=gen11) {
   ..
   } else {
   ..
   }
}

I'd write it like

if(>=gen11) {
   ..
} else if(>=gen9) {
   ..
} els...

I think it will be much easier to read. Same below in intel_sprite.c

/Juha-Pekka

>   	if (INTEL_GEN(dev_priv) >= 9) {
>   		primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> -						     PLANE_PRIMARY);
> -
> -		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> +				PLANE_PRIMARY);
> +
> +		if (skl_plane_has_planar(dev_priv, pipe,
> +					PLANE_PRIMARY)) {
> +			if (INTEL_GEN(dev_priv) >= 11) {
> +				intel_primary_formats = icl_primary_formats;
> +				num_formats = ARRAY_SIZE(icl_primary_formats);
> +			} else {
> +				intel_primary_formats = skl_primary_formats;
> +				num_formats = ARRAY_SIZE(skl_primary_formats);
> +			}
> +		} else if (INTEL_GEN(dev_priv) >= 11) {
> +			intel_primary_formats = icl_pri_planar_formats;
> +			num_formats = ARRAY_SIZE(icl_pri_planar_formats);
> +		} else {
>   			intel_primary_formats = skl_pri_planar_formats;
>   			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
> -		} else {
> -			intel_primary_formats = skl_primary_formats;
> -			num_formats = ARRAY_SIZE(skl_primary_formats);
>   		}
>   
>   		if (primary->has_ccs)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index c831360..7d9b3e4 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1564,6 +1564,36 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_NV12,
>   };
>   
> +static uint32_t icl_plane_formats[] = {
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
> +static uint32_t icl_planar_formats[] = {
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +};
> +
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -1822,8 +1852,16 @@ struct intel_plane *
>   
>   		if (skl_plane_has_planar(dev_priv, pipe,
>   					 PLANE_SPRITE0 + plane)) {
> -			plane_formats = skl_planar_formats;
> -			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
> +			if (INTEL_GEN(dev_priv) >= 11) {
> +				plane_formats = icl_planar_formats;
> +				num_plane_formats = ARRAY_SIZE(icl_planar_formats);
> +			} else {
> +				plane_formats = skl_planar_formats;
> +				num_plane_formats = ARRAY_SIZE(skl_planar_formats);
> +			}
> +		} else if (INTEL_GEN(dev_priv) >= 11) {
> +			plane_formats = icl_plane_formats;
> +			num_plane_formats = ARRAY_SIZE(icl_plane_formats);
>   		} else {
>   			plane_formats = skl_plane_formats;
>   			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> 
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Re: [PATCH v3 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc

[Alexandru-Cosmin Gheorghe]

Hi Swati,

On Mon, Oct 15, 2018 at 01:39:54PM +0530, SwatiSharma@outlook.ms-acdc.office.com wrote:

Btw, I can't reply to this address.

> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> 
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies 32bit.
> 
> Y210: Valid data occupies MSB 10 bits.
>       LSB 6 bits are filled with zeroes.
> Y212: Valid data occupies MSB 12 bits.
>       LSB 4 bits are filled with zeroes.
> Y216: Valid data occupies 16 bits,
>       doesn't require any padding bits.
> 
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
> 
> v2: is_yuv setted to true (mahesh)
>     different order of yuv samples (mahesh): still update from
>     hardware team pending
>     change in comment (alexandru)
> 
> v3: change in patch comment (juha)
>     change in fourcc_code comment (juha)
>     different order of yuv samples needs to be defined for Y210/
>     Y212/Y216 (update from h/w folks): not including in this patch,
>     will do in other patch series (if reqd)
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/drm_fourcc.c  | 3 +++
>  include/uapi/drm/drm_fourcc.h | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90a1c84..667527b 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -225,6 +225,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
>  		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },


I think this should be .cpp {4, 0, 0}, otherwise framebuffer_check
will demand a min pitch(width * cpp)  that's greater of what's actually really
required.
I think you should apply the same convetion as for other 422 packed
formats see DRM_FORMAT_UYVY and others.


>  	};
>  
>  	unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 139632b..af1c900 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -153,6 +153,14 @@
>  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>  
>  /*
> + * packed Y2xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb
> + */
> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
> +
> +/*
>   * 2 plane RGB + A
>   * index 0 = RGB plane, same format as the corresponding non _A8 format has
>   * index 1 = A plane, [7:0] A
> -- 
> 1.9.1

-- 
Cheers,
Alex G
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Re: [PATCH v3 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc

[Alexandru-Cosmin Gheorghe]

Hi Swati,

On Mon, Oct 15, 2018 at 01:39:54PM +0530, SwatiSharma@outlook.ms-acdc.office.com wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies 32bit.
> 
> Y210: Valid data occupies MSB 10 bits.
>       LSB 6 bits are filled with zeroes.
> Y212: Valid data occupies MSB 12 bits.
>       LSB 4 bits are filled with zeroes.
> Y216: Valid data occupies 16 bits,
>       doesn't require any padding bits.
> 
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
> 
> v2: is_yuv setted to true (mahesh)
>     different order of yuv samples (mahesh): still update from
>     hardware team pending
>     change in comment (alexandru)
> 
> v3: change in patch comment (juha)
>     change in fourcc_code comment (juha)
>     different order of yuv samples needs to be defined for Y210/
>     Y212/Y216 (update from h/w folks): not including in this patch,
>     will do in other patch series (if reqd)
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/drm_fourcc.c  | 3 +++
>  include/uapi/drm/drm_fourcc.h | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 90a1c84..667527b 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -225,6 +225,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
>  		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

Shouldn't this be .cpp {4, 0, 0}? otherwise framebuffer_check will
require a minimum pitch bigger than actually required.

I think you need to apply the same convention as with other 422 packed
formats, see DRM_FORMAT_YUYV & DRM_FORMAT_UYVY.

>  	};
>  
>  	unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 139632b..af1c900 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -153,6 +153,14 @@
>  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>  
>  /*
> + * packed Y2xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb
> + */
> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
> +
> +/*
>   * 2 plane RGB + A
>   * index 0 = RGB plane, same format as the corresponding non _A8 format has
>   * index 1 = A plane, [7:0] A
> -- 
> 1.9.1

-- 
Cheers,
Alex G
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