[v3 0/2] Enable Plane Input CSC for ICL

[v3 0/2] Enable Plane Input CSC for ICL

[Uma Shankar]

This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.

This series enables color conversion for Full Range YUV data,
limited range handling will be done as a separate patch.

v2: Separated the patch into 2 parts as per Maarten's comments.
Addressed Ville and Maarten's review comment.

v3: Redesigned the register macro definition as per Matt's comment.
Addressed Maarten's review comment.

Note: This is currently untested and floated to get feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.

Uma Shankar (2):
  drm/i915/icl: Define Plane Input CSC Coefficient Registers
  drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

 drivers/gpu/drm/i915/i915_reg.h      | 50 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_color.c   | 58 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 4 files changed, 128 insertions(+), 6 deletions(-)

-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev2)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev2)
URL   : https://patchwork.freedesktop.org/series/51463/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
300ba10fc48e drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:6603:
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)

-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:6603:
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)

-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:6619:
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)

-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:6619:
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)

-:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#83: FILE: drivers/gpu/drm/i915/i915_reg.h:6635:
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)

-:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#83: FILE: drivers/gpu/drm/i915/i915_reg.h:6635:
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)

total: 0 errors, 0 warnings, 6 checks, 62 lines checked
f8ddd10579f0 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

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✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev2)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev2)
URL   : https://patchwork.freedesktop.org/series/51463/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!

Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)

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[v3 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers

[Uma Shankar]

Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.

v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.

v3: Removed a redundant 3rd register definition and simplified
the equally spaced register definition by adding an offset as
per Matt's comment.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..d806e6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
+#define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
@@ -6585,6 +6586,55 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
 
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+	     _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+	     _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
 
 #define _PLANE_CTL_1_B				0x71180
 #define _PLANE_CTL_2_B				0x71280
-- 
1.9.1

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[v3 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

[Uma Shankar]

Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.

This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.

v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.

v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 58 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 3 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..2f77c8b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
 #define CSC_RGB_TO_YUV_BV 0x1e080000
 
+#define  ROFF(x)          (((x) & 0xffff) << 16)
+#define  GOFF(x)          (((x) & 0xffff) << 0)
+#define  BOFF(x)          (((x) & 0xffff) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI		0x800
+#define PREOFF_YUV_TO_RGB_ME		0xF00
+#define PREOFF_YUV_TO_RGB_LO		0x800
+
 /*
  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  * format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,55 @@ int intel_color_check(struct drm_crtc *crtc,
 	return -EINVAL;
 }
 
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv =
+		to_i915(plane_state->base.plane->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	enum pipe pipe = crtc->pipe;
+	struct intel_plane *intel_plane =
+		to_intel_plane(plane_state->base.plane);
+	enum plane_id plane = intel_plane->id;
+
+	static const u16 input_csc_matrix[][9] = {
+		/* BT.601 full range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x7AF8, 7800, 0x0,
+			0x8B28, 7800, 0x9AC0,
+			0x0, 7800, 0x7DD8,
+		},
+		/* BT.709 full range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x7C98, 7800, 0x0,
+			0x9EF8, 7800, 0xABF8,
+			0x0, 0x7800,  0x7ED8,
+		},
+	};
+	const u16 *csc = input_csc_matrix[plane_state->base.color_encoding];
+
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
+		   GOFF(csc[1]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
+		   GOFF(csc[4]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
+		   GOFF(csc[7]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
+
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
+		   PREOFF_YUV_TO_RGB_HI);
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
+		   PREOFF_YUV_TO_RGB_ME);
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
+		   PREOFF_YUV_TO_RGB_LO);
+
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0);
+}
+
 void intel_color_init(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fe045ab..be65419 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3666,6 +3666,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+
 	u32 plane_color_ctl = 0;
 
 	if (INTEL_GEN(dev_priv) < 11) {
@@ -3676,13 +3678,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
 	if (fb->format->is_yuv) {
-		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
-			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
-		else
-			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+		if (!icl_is_hdr_plane(plane)) {
+			if (plane_state->base.color_encoding ==
+					DRM_COLOR_YCBCR_BT709)
+				plane_color_ctl |=
+					PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
+			else
+				plane_color_ctl |=
+					PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
 
-		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
-			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+			if (plane_state->base.color_range ==
+					DRM_COLOR_YCBCR_FULL_RANGE)
+				plane_color_ctl |=
+				PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+		} else {
+			icl_program_input_csc_coeff(crtc_state, plane_state);
+			plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
+		}
 	}
 
 	return plane_color_ctl;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308..bd9e946 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state);
 
 /* intel_lspcon.c */
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
-- 
1.9.1

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✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev2)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev2)
URL   : https://patchwork.freedesktop.org/series/51463/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10582 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10582 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-plain-flip:
      fi-ilk-650:         PASS -> DMESG-WARN (fdo#106387)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@pm_rpm@basic-pci-d3-state:
      fi-glk-dsi:         PASS -> INCOMPLETE (k.org#198133, fdo#103359)

    
    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (46 -> 42) ==

  Additional (1): fi-icl-u 
  Missing    (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-glk-j4005 


== Build changes ==

    * Linux: CI_DRM_5037 -> Patchwork_10582

  CI_DRM_5037: e11750586cb6054bd319ad217cecd045febaacc5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4694: ff8d1156723f235e82cb4fcfd2cd6e5a5bb211fa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10582: f8ddd10579f0945f49761c4af0e7eb23a5a1c7f8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f8ddd10579f0 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
300ba10fc48e drm/i915/icl: Define Plane Input CSC Coefficient Registers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10582/issues.html
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