* [PATCH 1/2] drm/i915: Mark up GTT sizes as u64
@ 2018-10-25 9:18 Chris Wilson
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2018-10-25 9:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Joonas Lahtinen, stable
Since we use a 64b virtual GTT irrespective of the system, we want to
ensure that the GTT computations remains 64b even on 32b systems,
including treatment of huge virtual pages.
No code generation changes on 64b:
Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++---
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 +++---
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1eb1ed2..19b2d991b5d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1708,7 +1708,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
if (i == 4)
continue;
- seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
+ seq_printf(m, "\t\t(%03d, %04d) %08llx: ",
pde, pte,
(pde * GEN6_PTES + pte) * I915_GTT_PAGE_SIZE);
for (i = 0; i < 4; i++) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..aa8307043036 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,9 +42,9 @@
#include "i915_selftest.h"
#include "i915_timeline.h"
-#define I915_GTT_PAGE_SIZE_4K BIT(12)
-#define I915_GTT_PAGE_SIZE_64K BIT(16)
-#define I915_GTT_PAGE_SIZE_2M BIT(21)
+#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
+#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
+#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 09ea65a29d98..256001b00e32 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -551,7 +551,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
err = igt_check_page_sizes(vma);
if (vma->page_sizes.gtt != I915_GTT_PAGE_SIZE_4K) {
- pr_err("page_sizes.gtt=%u, expected %lu\n",
+ pr_err("page_sizes.gtt=%u, expected %llu\n",
vma->page_sizes.gtt, I915_GTT_PAGE_SIZE_4K);
err = -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 17b5aaaa7a50..69fe86b30fbb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1337,7 +1337,7 @@ static int igt_gtt_reserve(void *arg)
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
if (vma->node.start != total ||
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
vma->node.start, vma->node.size,
total, 2*I915_GTT_PAGE_SIZE);
err = -EINVAL;
@@ -1386,7 +1386,7 @@ static int igt_gtt_reserve(void *arg)
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
if (vma->node.start != total ||
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
vma->node.start, vma->node.size,
total, 2*I915_GTT_PAGE_SIZE);
err = -EINVAL;
@@ -1430,7 +1430,7 @@ static int igt_gtt_reserve(void *arg)
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
if (vma->node.start != offset ||
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
vma->node.start, vma->node.size,
offset, 2*I915_GTT_PAGE_SIZE);
err = -EINVAL;
--
2.19.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b
2018-10-25 9:18 [PATCH 1/2] drm/i915: Mark up GTT sizes as u64 Chris Wilson
@ 2018-10-25 9:18 ` Chris Wilson
2018-10-25 17:16 ` [Intel-gfx] " Matthew Auld
2018-11-14 11:52 ` Lionel Landwerlin
2018-10-25 10:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64 Patchwork
2018-10-25 17:15 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
2 siblings, 2 replies; 7+ messages in thread
From: Chris Wilson @ 2018-10-25 9:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Joonas Lahtinen, stable
Beware mixing unsigned long constants and 64b values, as on 32b the
constant will be zero extended and discard the high 32b when used as
a mask!
Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gvt/gtt.h | 1 -
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 7a9b36176efb..bfb6f652b09f 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -35,7 +35,6 @@
#define _GVT_GTT_H_
#define I915_GTT_PAGE_SHIFT 12
-#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
struct intel_vgpu_mm;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f90a09b83370..1a1c04db6c80 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -460,7 +460,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
* any non-page-aligned or non-canonical addresses.
*/
if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
- entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
+ entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
return -EINVAL;
/* pad_to_size was once a reserved field, so sanitize it */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index aa8307043036..5d2c5ba55ad8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -49,6 +49,8 @@
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
+#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
+
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
#define I915_FENCE_REG_NONE -1
--
2.19.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64
2018-10-25 9:18 [PATCH 1/2] drm/i915: Mark up GTT sizes as u64 Chris Wilson
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
@ 2018-10-25 10:25 ` Patchwork
2018-10-26 11:38 ` Chris Wilson
2018-10-25 17:15 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
2 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2018-10-25 10:25 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Mark up GTT sizes as u64
URL : https://patchwork.freedesktop.org/series/51505/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5033 -> Patchwork_10575 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10575 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10575, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51505/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10575:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_guc:
fi-apl-guc: PASS -> SKIP
igt@pm_rpm@module-reload:
fi-hsw-4770r: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10575 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_module_reload@basic-reload:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106248, fdo#106725)
igt@drv_selftest@live_execlists:
fi-apl-guc: PASS -> INCOMPLETE (fdo#106693)
igt@drv_selftest@live_sanitycheck:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719)
igt@kms_flip@basic-flip-vs-modeset:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000)
==== Possible fixes ====
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: DMESG-WARN (fdo#107425, fdo#107924) -> PASS
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924
fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
== Participating hosts (47 -> 42) ==
Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u
== Build changes ==
* Linux: CI_DRM_5033 -> Patchwork_10575
CI_DRM_5033: f935e4c7634781e6ffef10bb8a1c93225ac42d90 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4691: d445be01f5edc7e7a324444c73e221c9ed75602e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10575: f26318af4224fe693787fa837dbe8d925d76bfc2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f26318af4224 drm/i915: Compare user's 64b GTT offset even on 32b
95ef779cdd41 drm/i915: Mark up GTT sizes as u64
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10575/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Mark up GTT sizes as u64
2018-10-25 9:18 [PATCH 1/2] drm/i915: Mark up GTT sizes as u64 Chris Wilson
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
2018-10-25 10:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64 Patchwork
@ 2018-10-25 17:15 ` Matthew Auld
2 siblings, 0 replies; 7+ messages in thread
From: Matthew Auld @ 2018-10-25 17:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, stable
On Thu, 25 Oct 2018 at 10:18, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Since we use a 64b virtual GTT irrespective of the system, we want to
> ensure that the GTT computations remains 64b even on 32b systems,
> including treatment of huge virtual pages.
>
> No code generation changes on 64b:
>
> Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: stable@vger.kernel.org
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
@ 2018-10-25 17:16 ` Matthew Auld
2018-11-14 11:52 ` Lionel Landwerlin
1 sibling, 0 replies; 7+ messages in thread
From: Matthew Auld @ 2018-10-25 17:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, stable
On Thu, 25 Oct 2018 at 10:18, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Beware mixing unsigned long constants and 64b values, as on 32b the
> constant will be zero extended and discard the high 32b when used as
> a mask!
>
> Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: stable@vger.kernel.org
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64
2018-10-25 10:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64 Patchwork
@ 2018-10-26 11:38 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-10-26 11:38 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
Quoting Patchwork (2018-10-25 11:25:34)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Mark up GTT sizes as u64
> URL : https://patchwork.freedesktop.org/series/51505/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5033 -> Patchwork_10575 =
>
> == Summary - WARNING ==
>
> Minor unknown changes coming with Patchwork_10575 need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10575, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://patchwork.freedesktop.org/api/1.0/series/51505/revisions/1/mbox/
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in Patchwork_10575:
>
> === IGT changes ===
>
> ==== Warnings ====
>
> igt@drv_selftest@live_guc:
> fi-apl-guc: PASS -> SKIP
>
> igt@pm_rpm@module-reload:
> fi-hsw-4770r: SKIP -> PASS
I gave up waiting for the full report and pushed. Thanks for the review
and bug report,
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
2018-10-25 17:16 ` [Intel-gfx] " Matthew Auld
@ 2018-11-14 11:52 ` Lionel Landwerlin
1 sibling, 0 replies; 7+ messages in thread
From: Lionel Landwerlin @ 2018-11-14 11:52 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: stable
Reminds me that we should probably update the uAPI...
struct drm_i915_gem_exec_object2 has a u64 flags and all the
EXEC_OBJECT_* flags are (1<<X)
-
Lionel
On 25/10/2018 10:18, Chris Wilson wrote:
> Beware mixing unsigned long constants and 64b values, as on 32b the
> constant will be zero extended and discard the high 32b when used as
> a mask!
>
> Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gvt/gtt.h | 1 -
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index 7a9b36176efb..bfb6f652b09f 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -35,7 +35,6 @@
> #define _GVT_GTT_H_
>
> #define I915_GTT_PAGE_SHIFT 12
> -#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
>
> struct intel_vgpu_mm;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index f90a09b83370..1a1c04db6c80 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -460,7 +460,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
> * any non-page-aligned or non-canonical addresses.
> */
> if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
> - entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
> + entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
> return -EINVAL;
>
> /* pad_to_size was once a reserved field, so sanitize it */
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index aa8307043036..5d2c5ba55ad8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -49,6 +49,8 @@
> #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
> #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
>
> +#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
> +
> #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
>
> #define I915_FENCE_REG_NONE -1
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-11-14 21:55 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-25 9:18 [PATCH 1/2] drm/i915: Mark up GTT sizes as u64 Chris Wilson
2018-10-25 9:18 ` [PATCH 2/2] drm/i915: Compare user's 64b GTT offset even on 32b Chris Wilson
2018-10-25 17:16 ` [Intel-gfx] " Matthew Auld
2018-11-14 11:52 ` Lionel Landwerlin
2018-10-25 10:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark up GTT sizes as u64 Patchwork
2018-10-26 11:38 ` Chris Wilson
2018-10-25 17:15 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
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