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From: Trent Piepho <tpiepho@impinj.com>
To: "marc.zyngier@arm.com" <marc.zyngier@arm.com>
Cc: "jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
	"faiz_abbas@ti.com" <faiz_abbas@ti.com>,
	"Joao.Pinto@synopsys.com" <Joao.Pinto@synopsys.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"helgaas@google.com" <helgaas@google.com>,
	"vigneshr@ti.com" <vigneshr@ti.com>
Subject: Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow
Date: Mon, 19 Nov 2018 20:14:55 +0000	[thread overview]
Message-ID: <1542658494.30311.552.camel@impinj.com> (raw)
In-Reply-To: <865zwyw351.wl-marc.zyngier@arm.com>

On Thu, 2018-11-15 at 19:29 +0000, Marc Zyngier wrote:
> On Thu, 15 Nov 2018 18:37:33 +0000,
> Trent Piepho <tpiepho@impinj.com> wrote:
> > 
> > On Thu, 2018-11-15 at 15:22 +0000, Gustavo Pimentel wrote:
> > > On 14/11/2018 18:28, Trent Piepho wrote:
> > > > On Tue, 2018-11-13 at 22:57 +0000, Marc Zyngier wrote:
> > > > > 
> > > > 
> > > > Now it works again.  Race still present.  I don't see the
> > > > dw_pci_msi_bottom_(un)mask methods ever get called.  I seem to recall
> > > > that they are called as a substitute if enable/disable are not present,
> > > > but haven't confirmed that, which would explain why they are not called
> > > > after I added enable.
> > > 
> > > Hum, this probably is correlated with [1] where on the describition the this
> > > enumerator says that "One shot does not require mask/unmask" see [2]
> > 
> > That seems reasonable then.  I've said before that while I think
> > masking could be added in the interrupt flow without breaking anything,
> > I think it's redundant to do it at this layer.
> > 
> > I suspect it might be possible mask/unmask the interrupt "manually",
> > e.g. UIO does this to allow handling a level interrupt from userspace,
> > and that would be a path to reach the mask methods.
> 
> The real use case is that a driver can perfectly disable (mask) an
> interrupt while being in the interrupt handler, and enable it again at
> a later time.

That's what I was thinking of with UIO, but uio_dmem_genirq_handler()
actually calls disable_irq_nosync().  I had thought it masked the irq
rather than disabled it.

I wonder if this is a UIO bug.  The distinction between disable and
mask is usually that the masked interrupt is not lost while the
disabled interrupt is.  But there are irq chips (like dwc!) that do not
 implement enable/disable methods and use mask methods instead.

  reply	other threads:[~2018-11-19 20:15 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13 22:57 [PATCH 0/3] PCI: designware: Fixing MSI handling flow Marc Zyngier
2018-11-13 22:57 ` [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling Marc Zyngier
2018-12-03 18:02   ` [1/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 1/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 2/3] PCI: designware: Take lock when ACKing an interrupt Marc Zyngier
2018-11-14 19:08   ` Trent Piepho
2018-12-03 18:02   ` [2/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 2/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 3/3] PCI: designware: Move interrupt acking into the proper callback Marc Zyngier
2018-11-14 19:01   ` Trent Piepho
2018-12-03 18:02   ` [3/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 3/3] " Gustavo Pimentel
2018-12-04 10:20   ` Kishon Vijay Abraham I
2018-12-04 13:45     ` Marc Zyngier
2018-12-07  8:12       ` Kishon Vijay Abraham I
2018-12-07  9:45         ` Marc Zyngier
2018-12-07 10:13           ` Kishon Vijay Abraham I
2018-12-11 12:35             ` Lorenzo Pieralisi
2018-12-12  5:54               ` Kishon Vijay Abraham I
2018-11-13 23:16 ` [PATCH 0/3] PCI: designware: Fixing MSI handling flow Gustavo Pimentel
2018-11-14  9:54   ` Marc Zyngier
2018-11-14 19:19     ` Trent Piepho
2018-11-14 22:01       ` Marc Zyngier
2018-11-14 22:25         ` Trent Piepho
2018-11-14 22:44           ` Marc Zyngier
2018-11-14 23:23             ` Trent Piepho
2018-11-19 20:37         ` Trent Piepho
2018-11-22 12:03     ` Gustavo Pimentel
2018-11-22 16:07       ` Gustavo Pimentel
2018-11-22 16:26       ` Lorenzo Pieralisi
2018-11-22 16:38         ` Marc Zyngier
2018-11-22 17:40           ` Gustavo Pimentel
2018-11-26 16:06           ` Trent Piepho
2018-11-27  7:51             ` Marc Zyngier
2018-11-27 17:23               ` Trent Piepho
2018-11-22 17:49         ` Gustavo Pimentel
2018-11-26 15:52       ` Trent Piepho
2018-11-27  7:50         ` Marc Zyngier
2018-11-27 18:12           ` Trent Piepho
2018-12-07 16:16           ` Gustavo Pimentel
2018-11-14 18:28 ` Trent Piepho
2018-11-14 22:07   ` Marc Zyngier
2018-11-14 22:50     ` Trent Piepho
2018-11-15 15:22   ` Gustavo Pimentel
2018-11-15 18:37     ` Trent Piepho
2018-11-15 19:29       ` Marc Zyngier
2018-11-19 20:14         ` Trent Piepho [this message]
2018-11-21 17:24 ` Stanimir Varbanov
2018-12-01 23:50   ` Niklas Cassel
2018-12-02 11:28     ` Stanimir Varbanov
2018-12-03 10:42     ` Lorenzo Pieralisi
2018-12-03 13:09       ` Niklas Cassel
2018-12-03 17:42         ` Lorenzo Pieralisi
2018-12-03 20:31           ` Trent Piepho
2018-12-10 16:17 ` Lorenzo Pieralisi
2018-12-10 16:30   ` Marc Zyngier
2018-12-10 18:15   ` Trent Piepho
2018-12-10 18:31     ` Marc Zyngier
2018-12-10 20:34       ` Trent Piepho
2018-12-12  9:10         ` Gustavo Pimentel
2018-12-12  8:55   ` Gustavo Pimentel
2018-12-11 11:43 ` Lorenzo Pieralisi

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