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From: Trent Piepho <tpiepho@impinj.com>
To: "marc.zyngier@arm.com" <marc.zyngier@arm.com>
Cc: "Joao.Pinto@synopsys.com" <Joao.Pinto@synopsys.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
	"vigneshr@ti.com" <vigneshr@ti.com>,
	"helgaas@google.com" <helgaas@google.com>
Subject: Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow
Date: Mon, 19 Nov 2018 20:37:18 +0000	[thread overview]
Message-ID: <1542659838.30311.561.camel@impinj.com> (raw)
In-Reply-To: <86sh0348tu.wl-marc.zyngier@arm.com>

On Wed, 2018-11-14 at 22:01 +0000, Marc Zyngier wrote:
> On Wed, 14 Nov 2018 19:19:27 +0000,
> 
> > It looks to me that the previous code was using whatever MSIs were
> > already enabled when the driver is initialized as the set to leave
> > enabled.
> 
> And I claim that this is a gross bug. We don't want to inherit
> anything at all, rather start from a fresh start.
> 
> > This looks like it changing that behavior, and instead enabling all
> > MSIs on initialization.
> > 
> > I would think the default value for a MSI should be disabled until
> > something enables it.
> 
> Sure, that's no big deal. We can plug in the enable/disable callbacks
> to that effect, although we'll end-up with similar result, I'd expect.
> 
> > I speculated that the previous behavior was trying to work with an MSI
> > enabled by the bootloader, ACPI firmware, etc. that should be left
> > alone.  Or perhaps there was no good reason not to disable everything
> > on initialization and that code just got copied from somewhere else and
> > no one thought about it.  There's certainly evidence of that in this
> > driver.
> 
> As you said, you're speculating. Nonetheless, there is no reason to
> start with anything enabled the first place.

First introduction of this concept explicitly appears to be by Gustavo
in commit 7c5925afbc.  It added irq_status to the driver state and
initialized it from the existing value of the enable register.  Prior
to this the bits were always set in a RMW operation I don't think
initialization was considered.

I don't see any note about why.  All disabled makes far more sense to
me.  You get hard to track down bugs with unexpected interrupts during
kernel boot, but only a soft reboot, because the irq is enabled before
the drivers expected it to be.

  parent reply	other threads:[~2018-11-19 20:38 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13 22:57 [PATCH 0/3] PCI: designware: Fixing MSI handling flow Marc Zyngier
2018-11-13 22:57 ` [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling Marc Zyngier
2018-12-03 18:02   ` [1/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 1/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 2/3] PCI: designware: Take lock when ACKing an interrupt Marc Zyngier
2018-11-14 19:08   ` Trent Piepho
2018-12-03 18:02   ` [2/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 2/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 3/3] PCI: designware: Move interrupt acking into the proper callback Marc Zyngier
2018-11-14 19:01   ` Trent Piepho
2018-12-03 18:02   ` [3/3] " Niklas Cassel
2018-12-04  9:41   ` [PATCH 3/3] " Gustavo Pimentel
2018-12-04 10:20   ` Kishon Vijay Abraham I
2018-12-04 13:45     ` Marc Zyngier
2018-12-07  8:12       ` Kishon Vijay Abraham I
2018-12-07  9:45         ` Marc Zyngier
2018-12-07 10:13           ` Kishon Vijay Abraham I
2018-12-11 12:35             ` Lorenzo Pieralisi
2018-12-12  5:54               ` Kishon Vijay Abraham I
2018-11-13 23:16 ` [PATCH 0/3] PCI: designware: Fixing MSI handling flow Gustavo Pimentel
2018-11-14  9:54   ` Marc Zyngier
2018-11-14 19:19     ` Trent Piepho
2018-11-14 22:01       ` Marc Zyngier
2018-11-14 22:25         ` Trent Piepho
2018-11-14 22:44           ` Marc Zyngier
2018-11-14 23:23             ` Trent Piepho
2018-11-19 20:37         ` Trent Piepho [this message]
2018-11-22 12:03     ` Gustavo Pimentel
2018-11-22 16:07       ` Gustavo Pimentel
2018-11-22 16:26       ` Lorenzo Pieralisi
2018-11-22 16:38         ` Marc Zyngier
2018-11-22 17:40           ` Gustavo Pimentel
2018-11-26 16:06           ` Trent Piepho
2018-11-27  7:51             ` Marc Zyngier
2018-11-27 17:23               ` Trent Piepho
2018-11-22 17:49         ` Gustavo Pimentel
2018-11-26 15:52       ` Trent Piepho
2018-11-27  7:50         ` Marc Zyngier
2018-11-27 18:12           ` Trent Piepho
2018-12-07 16:16           ` Gustavo Pimentel
2018-11-14 18:28 ` Trent Piepho
2018-11-14 22:07   ` Marc Zyngier
2018-11-14 22:50     ` Trent Piepho
2018-11-15 15:22   ` Gustavo Pimentel
2018-11-15 18:37     ` Trent Piepho
2018-11-15 19:29       ` Marc Zyngier
2018-11-19 20:14         ` Trent Piepho
2018-11-21 17:24 ` Stanimir Varbanov
2018-12-01 23:50   ` Niklas Cassel
2018-12-02 11:28     ` Stanimir Varbanov
2018-12-03 10:42     ` Lorenzo Pieralisi
2018-12-03 13:09       ` Niklas Cassel
2018-12-03 17:42         ` Lorenzo Pieralisi
2018-12-03 20:31           ` Trent Piepho
2018-12-10 16:17 ` Lorenzo Pieralisi
2018-12-10 16:30   ` Marc Zyngier
2018-12-10 18:15   ` Trent Piepho
2018-12-10 18:31     ` Marc Zyngier
2018-12-10 20:34       ` Trent Piepho
2018-12-12  9:10         ` Gustavo Pimentel
2018-12-12  8:55   ` Gustavo Pimentel
2018-12-11 11:43 ` Lorenzo Pieralisi

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