[PATCH] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[PATCH] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_irq.c         |  9 ---------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++++++----
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..07e47023f557 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -428,17 +428,25 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		mmio = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (1) {
+		i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
 		u32 mask = ~0u;
 
 		/*
 		 * Keep the render interrupt unmasked as this papers over
 		 * lost interrupts following a reset.
 		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+		if (engine->id == RCS) {
+			if (INTEL_GEN(dev_priv) >= 6)
+				mask &= ~BIT(0);
+			else
+				mask &= ~I915_USER_INTERRUPT;
+		}
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
+		if (INTEL_GEN(dev_priv) >= 3)
+			I915_WRITE(hwstam, mask);
+		else
+			I915_WRITE16(hwstam, mask);
 	}
 
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-- 
2.20.0

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✓ Fi.CI.BAT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5310 -> Patchwork_11082
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11082 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@amdgpu/amd_prime@amd-to-i915:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#107341]

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       PASS -> FAIL [fdo#108767]

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-icl-u3:          NOTRUN -> DMESG-WARN [fdo#108924] / [fdo#109044]

  * {igt@runner@aborted}:
    - fi-icl-u3:          NOTRUN -> FAIL [fdo#108924]

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       DMESG-WARN [fdo#108965] -> PASS

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        DMESG-FAIL [fdo#108735] -> PASS
    - fi-kbl-7560u:       INCOMPLETE [fdo#108044] -> PASS

  * igt@kms_busy@basic-flip-b:
    - fi-bdw-gvtdvm:      FAIL [fdo#103182] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108924]: https://bugs.freedesktop.org/show_bug.cgi?id=108924
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [fdo#109044]: https://bugs.freedesktop.org/show_bug.cgi?id=109044


Participating hosts (47 -> 44)
------------------------------

  Additional (1): fi-icl-u3 
  Missing    (4): fi-kbl-soraka fi-ctg-p8600 fi-ilk-m540 fi-hsw-4200u 


Build changes
-------------

    * Linux: CI_DRM_5310 -> Patchwork_11082

  CI_DRM_5310: 1f86f1fb70f082ed93450c328e518d8013d23953 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11082: 49b3bd88fe244d221eda29cdd5375cb20bb5ab46 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

49b3bd88fe24 drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11082/
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Re: [PATCH] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Tvrtko Ursulin]

On 13/12/2018 08:53, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_irq.c         |  9 ---------
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++++++----
>   2 files changed, 12 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(dev);
>   
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET(DE);
>   	if (IS_GEN(dev_priv, 7))
>   		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>   	GEN2_IRQ_RESET();
>   }
>   
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET();
>   }
>   
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET();
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..07e47023f557 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -428,17 +428,25 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>   		mmio = RING_HWS_PGA(engine->mmio_base);
>   	}
>   
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (1) {

A tad too lazy. :) Suggest a helper function some_appropriate_name(engine);

Regards,

Tvrtko

> +		i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
>   		u32 mask = ~0u;
>   
>   		/*
>   		 * Keep the render interrupt unmasked as this papers over
>   		 * lost interrupts following a reset.
>   		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> +		if (engine->id == RCS) {
> +			if (INTEL_GEN(dev_priv) >= 6)
> +				mask &= ~BIT(0);
> +			else
> +				mask &= ~I915_USER_INTERRUPT;
> +		}
>   
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> +		if (INTEL_GEN(dev_priv) >= 3)
> +			I915_WRITE(hwstam, mask);
> +		else
> +			I915_WRITE16(hwstam, mask);
>   	}
>   
>   	I915_WRITE(mmio, engine->status_page.ggtt_offset);
> 
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[PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |  9 ------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..10e7b7a6ba88 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -393,12 +393,38 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
+static void set_hwstam_mask(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+	u32 mask = ~0u;
+
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->id == RCS) {
+		if (INTEL_GEN(dev_priv) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
+	}
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 	i915_reg_t mmio;
 
-	/* The ring status page addresses are no longer next to the rest of
+	set_hwstam_mask(engine);
+
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -428,19 +454,6 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		mmio = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
-
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
-
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
-	}
-
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
 	POSTING_READ(mmio);
 
-- 
2.20.0

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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> v2: Delazy and move the HWSTAM into its own function
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
>  2 files changed, 27 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET(DE);
>  	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>  	GEN2_IRQ_RESET();
>  }
>  
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }

So we're not worried about enabling interrupts and having
something unmasked in HWSTAM by accident before we have the
status page set up?

>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..10e7b7a6ba88 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -393,12 +393,38 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>  	I915_WRITE(HWS_PGA, addr);
>  }
>  
> +static void set_hwstam_mask(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
> +	u32 mask = ~0u;
> +
> +	/*
> +	 * Keep the render interrupt unmasked as this papers over
> +	 * lost interrupts following a reset.
> +	 */
> +	if (engine->id == RCS) {
> +		if (INTEL_GEN(dev_priv) >= 6)
> +			mask &= ~BIT(0);
> +		else
> +			mask &= ~I915_USER_INTERRUPT;
> +	}
> +
> +	if (INTEL_GEN(dev_priv) >= 3)
> +		I915_WRITE(hwstam, mask);
> +	else
> +		I915_WRITE16(hwstam, mask);
> +}
> +
>  static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	i915_reg_t mmio;
>  
> -	/* The ring status page addresses are no longer next to the rest of
> +	set_hwstam_mask(engine);
> +
> +	/*
> +	 * The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
>  	 */
>  	if (IS_GEN(dev_priv, 7)) {
> @@ -428,19 +454,6 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		mmio = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> -		u32 mask = ~0u;
> -
> -		/*
> -		 * Keep the render interrupt unmasked as this papers over
> -		 * lost interrupts following a reset.
> -		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> -
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> -	}
> -
>  	I915_WRITE(mmio, engine->status_page.ggtt_offset);
>  	POSTING_READ(mmio);
>  
> -- 
> 2.20.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Ville Syrjälä (2018-12-13 11:59:28)
> On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > Having completed a test run of gem_eio across all machines in CI we also
> > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > the same HWSTAM workaround that was effective for gen6+ for all, as
> > although we haven't seen the same failure on gen4/5 it seems prudent to
> > keep the code the same.
> > 
> > As a consequence we can remove the extra setting of HWSTAM and apply the
> > register from a single site.
> > 
> > v2: Delazy and move the HWSTAM into its own function
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> >  2 files changed, 27 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index e2dac9b5f4ce..0c7fc9890891 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> >  {
> >       struct drm_i915_private *dev_priv = to_i915(dev);
> >  
> > -     if (IS_GEN(dev_priv, 5))
> > -             I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET(DE);
> >       if (IS_GEN(dev_priv, 7))
> >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE16(HWSTAM, 0xffff);
> > -
> >       GEN2_IRQ_RESET();
> >  }
> >  
> > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET();
> >  }
> >  
> > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET();
> >  }
> 
> So we're not worried about enabling interrupts and having
> something unmasked in HWSTAM by accident before we have the
> status page set up?

Sanitization of the HWSP setup would be off during early engine setup.
We do the irq install & reset during i915_load_modeset_init after we do
the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
HWSP moves the sanitisation earlier.

The only question then is order inside the HWSP setup, and the
suggestion would be to make sure the HWSP is set before the HWSTAM to be
safe on the bits we control.
-Chris
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Chris Wilson (2018-12-13 12:07:35)
> Quoting Ville Syrjälä (2018-12-13 11:59:28)
> > On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > > Having completed a test run of gem_eio across all machines in CI we also
> > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > keep the code the same.
> > > 
> > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > register from a single site.
> > > 
> > > v2: Delazy and move the HWSTAM into its own function
> > > 
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> > >  2 files changed, 27 insertions(+), 23 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > >  {
> > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > >  
> > > -     if (IS_GEN(dev_priv, 5))
> > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET(DE);
> > >       if (IS_GEN(dev_priv, 7))
> > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > -
> > >       GEN2_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > 
> > So we're not worried about enabling interrupts and having
> > something unmasked in HWSTAM by accident before we have the
> > status page set up?
> 
> Sanitization of the HWSP setup would be off during early engine setup.
> We do the irq install & reset during i915_load_modeset_init after we do
> the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
> HWSP moves the sanitisation earlier.

More aptly though, we should reset the mask on unload. Which should be
taken care of by issuing a GPU reset. But in any case probably wise to
make sure all writes are masked off.
-Chris
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Thu, Dec 13, 2018 at 12:07:35PM +0000, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-12-13 11:59:28)
> > On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > > Having completed a test run of gem_eio across all machines in CI we also
> > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > keep the code the same.
> > > 
> > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > register from a single site.
> > > 
> > > v2: Delazy and move the HWSTAM into its own function
> > > 
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> > >  2 files changed, 27 insertions(+), 23 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > >  {
> > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > >  
> > > -     if (IS_GEN(dev_priv, 5))
> > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET(DE);
> > >       if (IS_GEN(dev_priv, 7))
> > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > -
> > >       GEN2_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > 
> > So we're not worried about enabling interrupts and having
> > something unmasked in HWSTAM by accident before we have the
> > status page set up?
> 
> Sanitization of the HWSP setup would be off during early engine setup.
> We do the irq install & reset during i915_load_modeset_init after we do
> the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
> HWSP moves the sanitisation earlier.

To me it looks like the hwsp setup happens via i915_gem_init(), which
gets called after irq install. But maybe I'm just hopelessly lost
in the maze.

Oh, and what about the hws_needs_physical case?

> 
> The only question then is order inside the HWSP setup, and the
> suggestion would be to make sure the HWSP is set before the HWSTAM to be
> safe on the bits we control.
> -Chris

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Ville Syrjälä (2018-12-13 12:29:15)
> On Thu, Dec 13, 2018 at 12:07:35PM +0000, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2018-12-13 11:59:28)
> > > On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > > > Having completed a test run of gem_eio across all machines in CI we also
> > > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > > keep the code the same.
> > > > 
> > > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > > register from a single site.
> > > > 
> > > > v2: Delazy and move the HWSTAM into its own function
> > > > 
> > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> > > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> > > >  2 files changed, 27 insertions(+), 23 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > > >  {
> > > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > > >  
> > > > -     if (IS_GEN(dev_priv, 5))
> > > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > > -
> > > >       GEN3_IRQ_RESET(DE);
> > > >       if (IS_GEN(dev_priv, 7))
> > > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > > >  
> > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > >  
> > > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > > -
> > > >       GEN2_IRQ_RESET();
> > > >  }
> > > >  
> > > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > > >  
> > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > >  
> > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > -
> > > >       GEN3_IRQ_RESET();
> > > >  }
> > > >  
> > > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > > >  
> > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > >  
> > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > -
> > > >       GEN3_IRQ_RESET();
> > > >  }
> > > 
> > > So we're not worried about enabling interrupts and having
> > > something unmasked in HWSTAM by accident before we have the
> > > status page set up?
> > 
> > Sanitization of the HWSP setup would be off during early engine setup.
> > We do the irq install & reset during i915_load_modeset_init after we do
> > the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
> > HWSP moves the sanitisation earlier.
> 
> To me it looks like the hwsp setup happens via i915_gem_init(), which
> gets called after irq install. But maybe I'm just hopelessly lost
> in the maze.

i915_driver_init_hw -> i915_gem_init_hw -> init_ringbuffer...

i915_load_modeset_init -> intel_irq_install -> irq_reset

Aiui, with init_hw called before modeset_init.
 
> Oh, and what about the hws_needs_physical case?

Good point.
-Chris
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Thu, Dec 13, 2018 at 12:34:02PM +0000, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-12-13 12:29:15)
> > On Thu, Dec 13, 2018 at 12:07:35PM +0000, Chris Wilson wrote:
> > > Quoting Ville Syrjälä (2018-12-13 11:59:28)
> > > > On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > > > > Having completed a test run of gem_eio across all machines in CI we also
> > > > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > > > keep the code the same.
> > > > > 
> > > > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > > > register from a single site.
> > > > > 
> > > > > v2: Delazy and move the HWSTAM into its own function
> > > > > 
> > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> > > > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> > > > >  2 files changed, 27 insertions(+), 23 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > > > >  {
> > > > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > > > >  
> > > > > -     if (IS_GEN(dev_priv, 5))
> > > > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > > > -
> > > > >       GEN3_IRQ_RESET(DE);
> > > > >       if (IS_GEN(dev_priv, 7))
> > > > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > > > >  
> > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > >  
> > > > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > > > -
> > > > >       GEN2_IRQ_RESET();
> > > > >  }
> > > > >  
> > > > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > > > >  
> > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > >  
> > > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > > -
> > > > >       GEN3_IRQ_RESET();
> > > > >  }
> > > > >  
> > > > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > > > >  
> > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > >  
> > > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > > -
> > > > >       GEN3_IRQ_RESET();
> > > > >  }
> > > > 
> > > > So we're not worried about enabling interrupts and having
> > > > something unmasked in HWSTAM by accident before we have the
> > > > status page set up?
> > > 
> > > Sanitization of the HWSP setup would be off during early engine setup.
> > > We do the irq install & reset during i915_load_modeset_init after we do
> > > the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
> > > HWSP moves the sanitisation earlier.
> > 
> > To me it looks like the hwsp setup happens via i915_gem_init(), which
> > gets called after irq install. But maybe I'm just hopelessly lost
> > in the maze.
> 
> i915_driver_init_hw -> i915_gem_init_hw -> init_ringbuffer...

i915_gem_init_hw() doesn't seem to be called from there, unless I'm
looking at a stale tree already. I did checkout ~4 hours ago so
could very well be outdated already :)

> 
> i915_load_modeset_init -> intel_irq_install -> irq_reset
> 
> Aiui, with init_hw called before modeset_init.
>  
> > Oh, and what about the hws_needs_physical case?
> 
> Good point.
> -Chris

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Ville Syrjälä (2018-12-13 12:45:00)
> On Thu, Dec 13, 2018 at 12:34:02PM +0000, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2018-12-13 12:29:15)
> > > On Thu, Dec 13, 2018 at 12:07:35PM +0000, Chris Wilson wrote:
> > > > Quoting Ville Syrjälä (2018-12-13 11:59:28)
> > > > > On Thu, Dec 13, 2018 at 11:01:05AM +0000, Chris Wilson wrote:
> > > > > > Having completed a test run of gem_eio across all machines in CI we also
> > > > > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > > > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > > > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > > > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > > > > keep the code the same.
> > > > > > 
> > > > > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > > > > register from a single site.
> > > > > > 
> > > > > > v2: Delazy and move the HWSTAM into its own function
> > > > > > 
> > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/i915_irq.c         |  9 ------
> > > > > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++---------
> > > > > >  2 files changed, 27 insertions(+), 23 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > > > > >  {
> > > > > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > >  
> > > > > > -     if (IS_GEN(dev_priv, 5))
> > > > > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > > > > -
> > > > > >       GEN3_IRQ_RESET(DE);
> > > > > >       if (IS_GEN(dev_priv, 7))
> > > > > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > > > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > > > > >  
> > > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > > >  
> > > > > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > > > > -
> > > > > >       GEN2_IRQ_RESET();
> > > > > >  }
> > > > > >  
> > > > > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > > > > >  
> > > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > > >  
> > > > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > > > -
> > > > > >       GEN3_IRQ_RESET();
> > > > > >  }
> > > > > >  
> > > > > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > > > > >  
> > > > > >       i9xx_pipestat_irq_reset(dev_priv);
> > > > > >  
> > > > > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > > > > -
> > > > > >       GEN3_IRQ_RESET();
> > > > > >  }
> > > > > 
> > > > > So we're not worried about enabling interrupts and having
> > > > > something unmasked in HWSTAM by accident before we have the
> > > > > status page set up?
> > > > 
> > > > Sanitization of the HWSP setup would be off during early engine setup.
> > > > We do the irq install & reset during i915_load_modeset_init after we do
> > > > the status page setup. Unless I'm mistaken, moving the HWSTAM alongside
> > > > HWSP moves the sanitisation earlier.
> > > 
> > > To me it looks like the hwsp setup happens via i915_gem_init(), which
> > > gets called after irq install. But maybe I'm just hopelessly lost
> > > in the maze.
> > 
> > i915_driver_init_hw -> i915_gem_init_hw -> init_ringbuffer...
> 
> i915_gem_init_hw() doesn't seem to be called from there, unless I'm
> looking at a stale tree already. I did checkout ~4 hours ago so
> could very well be outdated already :)

Indeed not. So moved the sanitization to
	i915_driver_init_mmio -> intel_engines_init_mmio
which is unarguably as early as we can do it :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5310_full -> Patchwork_11082_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11082_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11082_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11082_full:

### IGT changes ###

#### Warnings ####

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          PASS -> SKIP
    - shard-snb:          PASS -> SKIP

  
Known issues
------------

  Here are the changes found in Patchwork_11082_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@pi-ringfull-bsd:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-skl:          NOTRUN -> TIMEOUT [fdo#108039]

  * igt@kms_atomic_transition@1x-modeset-transitions-fencing:
    - shard-skl:          PASS -> FAIL [fdo#107815] / [fdo#108470]

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          PASS -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#107956] +1

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107725]

  * igt@kms_chv_cursor_fail@pipe-b-128x128-top-edge:
    - shard-skl:          NOTRUN -> FAIL [fdo#104671]

  * igt@kms_chv_cursor_fail@pipe-c-64x64-right-edge:
    - shard-skl:          PASS -> FAIL [fdo#104671]

  * igt@kms_color@pipe-a-ctm-blue-to-red:
    - shard-skl:          PASS -> FAIL [fdo#107201]

  * igt@kms_color@pipe-c-ctm-0-5:
    - shard-skl:          PASS -> FAIL [fdo#108682]

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#104108]

  * igt@kms_cursor_crc@cursor-128x42-onscreen:
    - shard-glk:          PASS -> FAIL [fdo#103232] +5

  * igt@kms_cursor_crc@cursor-256x256-sliding:
    - shard-skl:          NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x21-offscreen:
    - shard-skl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#105454] / [fdo#106509]

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
    - shard-skl:          NOTRUN -> FAIL [fdo#103184]

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-glk:          PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-skl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-apl:          PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-skl:          NOTRUN -> FAIL [fdo#105682] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-skl:          NOTRUN -> FAIL [fdo#105683]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-skl:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +3

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - shard-skl:          PASS -> FAIL [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108948]

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885] +1

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-glk:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
    - shard-iclb:         PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
    - shard-apl:          PASS -> FAIL [fdo#103166]

  * igt@kms_rmfb@close-fd:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +3

  * igt@kms_setmode@basic:
    - shard-apl:          PASS -> FAIL [fdo#99912]
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@pm_rpm@cursor:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807]

  * igt@pm_rpm@debugfs-forcewake-user:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#108654]

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS +3

  * igt@kms_cursor_crc@cursor-64x64-random:
    - shard-glk:          FAIL [fdo#103232] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
    - shard-skl:          FAIL [fdo#103184] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-iclb:         WARN [fdo#108336] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> PASS +3

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +5

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-iclb:         DMESG-FAIL [fdo#103166] / [fdo#107724] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +3

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-iclb:         FAIL [fdo#103166] -> PASS

  * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +8

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@pm_rpm@pm-caching:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS

  * igt@pm_rpm@universal-planes:
    - shard-iclb:         INCOMPLETE [fdo#108840] -> PASS

  * igt@syncobj_wait@multi-wait-for-submit-unsubmitted-signaled:
    - shard-snb:          INCOMPLETE [fdo#105411] -> PASS

  
#### Warnings ####

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232]

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-iclb:         FAIL [fdo#108948] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          DMESG-WARN [fdo#105604] -> DMESG-FAIL [fdo#108950]
    - shard-glk:          DMESG-FAIL [fdo#105763] / [fdo#106538] -> DMESG-WARN [fdo#105763] / [fdo#106538]

  
  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5310 -> Patchwork_11082

  CI_DRM_5310: 1f86f1fb70f082ed93450c328e518d8013d23953 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11082: 49b3bd88fe244d221eda29cdd5375cb20bb5ab46 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11082/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev2)
URL   : https://patchwork.freedesktop.org/series/53979/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5311 -> Patchwork_11084
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_11084 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11084, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/2/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11084:

### IGT changes ###

#### Possible regressions ####

  * igt@pm_rpm@basic-rte:
    - fi-byt-n2820:       PASS -> FAIL
    - fi-byt-j1900:       PASS -> FAIL

  
#### Warnings ####

  * igt@pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       PASS -> SKIP
    - fi-byt-n2820:       PASS -> SKIP

  
Known issues
------------

  Here are the changes found in Patchwork_11084 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * {igt@runner@aborted}:
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-kbl-7560u:       INCOMPLETE [fdo#103665] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070


Participating hosts (47 -> 44)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (4): fi-kbl-soraka fi-ctg-p8600 fi-byt-squawks fi-ilk-m540 


Build changes
-------------

    * Linux: CI_DRM_5311 -> Patchwork_11084

  CI_DRM_5311: a42fd8bf199784ee4ff1cdb5ee03eedd9a535d4a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11084: faea0cabad7732d0ac7d3554897f08b42cbf517e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

faea0cabad77 drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11084/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function
v3: Mask off all HWSP writes on driver unload and engine cleanup.

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |  9 ---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 97 ++++++++++++++++---------
 2 files changed, 63 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..5ab564999cc6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -393,12 +393,13 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	i915_reg_t mmio;
+	i915_reg_t hwsp;
 
-	/* The ring status page addresses are no longer next to the rest of
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -410,56 +411,82 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		default:
 			GEM_BUG_ON(engine->id);
 		case RCS:
-			mmio = RENDER_HWS_PGA_GEN7;
+			hwsp = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
-			mmio = BLT_HWS_PGA_GEN7;
+			hwsp = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
-			mmio = BSD_HWS_PGA_GEN7;
+			hwsp = BSD_HWS_PGA_GEN7;
 			break;
 		case VECS:
-			mmio = VEBOX_HWS_PGA_GEN7;
+			hwsp = VEBOX_HWS_PGA_GEN7;
 			break;
 		}
 	} else if (IS_GEN(dev_priv, 6)) {
-		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
 	} else {
-		mmio = RING_HWS_PGA(engine->mmio_base);
+		hwsp = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
+	I915_WRITE(hwsp, offset);
+	POSTING_READ(hwsp);
+}
 
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+static void __set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
+static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->id == RCS) {
+		if (INTEL_GEN(engine->i915) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
 	}
 
-	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-	POSTING_READ(mmio);
+	__set_hwstam(engine, mask);
+}
 
-	/* Flush the TLB for this page */
-	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
-		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+static void flush_cs_tlb(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
 
-		/* ring should be idle before issuing a sync flush*/
-		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+	if (!IS_GEN_RANGE(dev_priv, 6, 7))
+		return;
 
-		I915_WRITE(reg,
-			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-					      INSTPM_SYNC_FLUSH));
-		if (intel_wait_for_register(dev_priv,
-					    reg, INSTPM_SYNC_FLUSH, 0,
-					    1000))
-			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-				  engine->name);
-	}
+	/* ring should be idle before issuing a sync flush*/
+	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+
+	I915_WRITE(instpm,
+		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+				      INSTPM_SYNC_FLUSH));
+	if (intel_wait_for_register(dev_priv,
+				    instpm, INSTPM_SYNC_FLUSH, 0,
+				    1000))
+		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+			  engine->name);
+}
+
+static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+{
+	set_hwsp(engine, engine->status_page.ggtt_offset);
+	set_hwstam(engine, ~0u);
+
+	flush_cs_tlb(engine);
 }
 
 static bool stop_ring(struct intel_engine_cs *engine)
@@ -1511,6 +1538,8 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
 	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
 		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
+	__set_hwstam(engine, ~0u);
+
 	intel_ring_unpin(engine->buffer);
 	intel_ring_free(engine->buffer);
 
-- 
2.20.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v4] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function
v3: Mask off all HWSP writes on driver unload and engine cleanup.
v4: And what about the physical hwsp?

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |   9 --
 drivers/gpu/drm/i915/intel_ringbuffer.c | 114 ++++++++++++++++--------
 2 files changed, 75 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..cefac3d9bba2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -379,11 +379,36 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 	return 0;
 }
 
-static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+static void __set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->id == RCS) {
+		if (INTEL_GEN(engine->i915) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
+	}
+
+	__set_hwstam(engine, mask);
+}
+
+static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct page *page = virt_to_page(engine->status_page.page_addr);
-	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
 	u32 addr;
 
 	addr = lower_32_bits(phys);
@@ -393,12 +418,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+{
+	struct page *page = virt_to_page(engine->status_page.page_addr);
+	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
+
+	set_hws_pga(engine, phys);
+	set_hwstam(engine, ~0u);
+}
+
+static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	i915_reg_t mmio;
+	i915_reg_t hwsp;
 
-	/* The ring status page addresses are no longer next to the rest of
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -410,56 +445,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		default:
 			GEM_BUG_ON(engine->id);
 		case RCS:
-			mmio = RENDER_HWS_PGA_GEN7;
+			hwsp = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
-			mmio = BLT_HWS_PGA_GEN7;
+			hwsp = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
-			mmio = BSD_HWS_PGA_GEN7;
+			hwsp = BSD_HWS_PGA_GEN7;
 			break;
 		case VECS:
-			mmio = VEBOX_HWS_PGA_GEN7;
+			hwsp = VEBOX_HWS_PGA_GEN7;
 			break;
 		}
 	} else if (IS_GEN(dev_priv, 6)) {
-		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
 	} else {
-		mmio = RING_HWS_PGA(engine->mmio_base);
+		hwsp = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
+	I915_WRITE(hwsp, offset);
+	POSTING_READ(hwsp);
+}
 
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+static void flush_cs_tlb(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
-	}
+	if (!IS_GEN_RANGE(dev_priv, 6, 7))
+		return;
 
-	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-	POSTING_READ(mmio);
+	/* ring should be idle before issuing a sync flush*/
+	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
-	/* Flush the TLB for this page */
-	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
-		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+	I915_WRITE(instpm,
+		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+				      INSTPM_SYNC_FLUSH));
+	if (intel_wait_for_register(dev_priv,
+				    instpm, INSTPM_SYNC_FLUSH, 0,
+				    1000))
+		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+			  engine->name);
+}
 
-		/* ring should be idle before issuing a sync flush*/
-		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+static void ring_setup_status_page(struct intel_engine_cs *engine)
+{
+	set_hwsp(engine, engine->status_page.ggtt_offset);
+	set_hwstam(engine, ~0u);
 
-		I915_WRITE(reg,
-			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-					      INSTPM_SYNC_FLUSH));
-		if (intel_wait_for_register(dev_priv,
-					    reg, INSTPM_SYNC_FLUSH, 0,
-					    1000))
-			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-				  engine->name);
-	}
+	flush_cs_tlb(engine);
 }
 
 static bool stop_ring(struct intel_engine_cs *engine)
@@ -529,7 +563,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
 	if (HWS_NEEDS_PHYSICAL(dev_priv))
 		ring_setup_phys_status_page(engine);
 	else
-		intel_ring_setup_status_page(engine);
+		ring_setup_status_page(engine);
 
 	intel_engine_reset_breadcrumbs(engine);
 
@@ -1511,6 +1545,8 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
 	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
 		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
+	__set_hwstam(engine, ~0u);
+
 	intel_ring_unpin(engine->buffer);
 	intel_ring_free(engine->buffer);
 
-- 
2.20.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function
v3: Mask off all HWSP writes on driver unload and engine cleanup.
v4: And what about the physical hwsp?
v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
daft. Really scrub HWSTAM as early as we can in driver_init_mmio()

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |   9 --
 drivers/gpu/drm/i915/intel_engine_cs.c  |  24 ++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++++---------
 3 files changed, 92 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6f165f9ad2bf..24245dba3207 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -261,6 +261,24 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
 			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
 }
 
+static void set_hwsp(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam;
+
+	hwstam = RING_HWSTAM(engine->mmio_base);
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
+{
+	/* Mask off all writes into the unknown HWSP */
+	set_hwsp(engine, ~0u);
+}
+
 static int
 intel_engine_setup(struct drm_i915_private *dev_priv,
 		   enum intel_engine_id id)
@@ -312,6 +330,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 
 	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 
+	/* Scrub mmio state on takeover */
+	intel_engine_sanitize_mmio(engine);
+
 	dev_priv->engine_class[info->class][info->instance] = engine;
 	dev_priv->engine[id] = engine;
 	return 0;
@@ -495,6 +516,9 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
 
 static void cleanup_status_page(struct intel_engine_cs *engine)
 {
+	/* Stop writing into the status page before returnig it to the system */
+	set_hwsp(engine, ~0u);
+
 	if (HWS_NEEDS_PHYSICAL(engine->i915)) {
 		void *addr = fetch_and_zero(&engine->status_page.page_addr);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..88f50e30a0c4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -379,11 +379,31 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 	return 0;
 }
 
-static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->id == RCS) {
+		if (INTEL_GEN(engine->i915) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
+	}
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct page *page = virt_to_page(engine->status_page.page_addr);
-	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
 	u32 addr;
 
 	addr = lower_32_bits(phys);
@@ -393,12 +413,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+{
+	struct page *page = virt_to_page(engine->status_page.page_addr);
+	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
+
+	set_hws_pga(engine, phys);
+	set_hwstam(engine, ~0u);
+}
+
+static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	i915_reg_t mmio;
+	i915_reg_t hwsp;
 
-	/* The ring status page addresses are no longer next to the rest of
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -410,56 +440,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		default:
 			GEM_BUG_ON(engine->id);
 		case RCS:
-			mmio = RENDER_HWS_PGA_GEN7;
+			hwsp = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
-			mmio = BLT_HWS_PGA_GEN7;
+			hwsp = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
-			mmio = BSD_HWS_PGA_GEN7;
+			hwsp = BSD_HWS_PGA_GEN7;
 			break;
 		case VECS:
-			mmio = VEBOX_HWS_PGA_GEN7;
+			hwsp = VEBOX_HWS_PGA_GEN7;
 			break;
 		}
 	} else if (IS_GEN(dev_priv, 6)) {
-		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
 	} else {
-		mmio = RING_HWS_PGA(engine->mmio_base);
+		hwsp = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
+	I915_WRITE(hwsp, offset);
+	POSTING_READ(hwsp);
+}
 
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+static void flush_cs_tlb(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
-	}
+	if (!IS_GEN_RANGE(dev_priv, 6, 7))
+		return;
 
-	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-	POSTING_READ(mmio);
+	/* ring should be idle before issuing a sync flush*/
+	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
-	/* Flush the TLB for this page */
-	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
-		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+	I915_WRITE(instpm,
+		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+				      INSTPM_SYNC_FLUSH));
+	if (intel_wait_for_register(dev_priv,
+				    instpm, INSTPM_SYNC_FLUSH, 0,
+				    1000))
+		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+			  engine->name);
+}
 
-		/* ring should be idle before issuing a sync flush*/
-		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+static void ring_setup_status_page(struct intel_engine_cs *engine)
+{
+	set_hwsp(engine, engine->status_page.ggtt_offset);
+	set_hwstam(engine, ~0u);
 
-		I915_WRITE(reg,
-			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-					      INSTPM_SYNC_FLUSH));
-		if (intel_wait_for_register(dev_priv,
-					    reg, INSTPM_SYNC_FLUSH, 0,
-					    1000))
-			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-				  engine->name);
-	}
+	flush_cs_tlb(engine);
 }
 
 static bool stop_ring(struct intel_engine_cs *engine)
@@ -529,7 +558,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
 	if (HWS_NEEDS_PHYSICAL(dev_priv))
 		ring_setup_phys_status_page(engine);
 	else
-		intel_ring_setup_status_page(engine);
+		ring_setup_status_page(engine);
 
 	intel_engine_reset_breadcrumbs(engine);
 
-- 
2.20.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev5)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5311 -> Patchwork_11086
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11086 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11086, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/5/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11086:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       PASS -> SKIP +33

  
Known issues
------------

  Here are the changes found in Patchwork_11086 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> DMESG-WARN [fdo#108622]

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-icl-u3:          NOTRUN -> DMESG-WARN [fdo#108924] / [fdo#109044]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362] +1

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#108529]

  * {igt@runner@aborted}:
    - fi-icl-u3:          NOTRUN -> FAIL [fdo#108924]
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622]

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-kbl-7560u:       INCOMPLETE [fdo#103665] -> PASS

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       DMESG-WARN [fdo#108473] -> DMESG-FAIL [fdo#105079]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
  [fdo#108473]: https://bugs.freedesktop.org/show_bug.cgi?id=108473
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#108924]: https://bugs.freedesktop.org/show_bug.cgi?id=108924
  [fdo#109044]: https://bugs.freedesktop.org/show_bug.cgi?id=109044


Participating hosts (47 -> 45)
------------------------------

  Additional (2): fi-icl-y fi-icl-u3 
  Missing    (4): fi-kbl-soraka fi-ctg-p8600 fi-byt-squawks fi-ilk-m540 


Build changes
-------------

    * Linux: CI_DRM_5311 -> Patchwork_11086

  CI_DRM_5311: a42fd8bf199784ee4ff1cdb5ee03eedd9a535d4a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11086: 3f34af703e8e3ad78f1b903d0e523c3b15afc2bb @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3f34af703e8e drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11086/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev6)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5311 -> Patchwork_11087
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11087 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11087, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/6/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11087:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       PASS -> SKIP +33

  
Known issues
------------

  Here are the changes found in Patchwork_11087 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-icl-u3:          NOTRUN -> DMESG-WARN [fdo#108924] / [fdo#109044]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#108529]

  * {igt@runner@aborted}:
    - fi-icl-u3:          NOTRUN -> FAIL [fdo#108924]

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-kbl-7560u:       INCOMPLETE [fdo#103665] -> PASS

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       DMESG-WARN [fdo#108473] -> DMESG-FAIL [fdo#105079]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108473]: https://bugs.freedesktop.org/show_bug.cgi?id=108473
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108924]: https://bugs.freedesktop.org/show_bug.cgi?id=108924
  [fdo#109044]: https://bugs.freedesktop.org/show_bug.cgi?id=109044


Participating hosts (47 -> 44)
------------------------------

  Additional (1): fi-icl-u3 
  Missing    (4): fi-kbl-soraka fi-ctg-p8600 fi-byt-squawks fi-ilk-m540 


Build changes
-------------

    * Linux: CI_DRM_5311 -> Patchwork_11087

  CI_DRM_5311: a42fd8bf199784ee4ff1cdb5ee03eedd9a535d4a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11087: 3d73335eb4f6f635113e7c49cb70e7a9888972b8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3d73335eb4f6 drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11087/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev6)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5311_full -> Patchwork_11087_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11087_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11087_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11087_full:

### IGT changes ###

#### Warnings ####

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          SKIP -> PASS

  
Known issues
------------

  Here are the changes found in Patchwork_11087_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@pi-ringfull-bsd:
    - shard-apl:          NOTRUN -> FAIL [fdo#103158]

  * igt@gem_exec_schedule@pi-ringfull-render:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]
    - shard-iclb:         NOTRUN -> FAIL [fdo#103158]

  * igt@gem_softpin@noreloc-s3:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713] +1
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-skl:          NOTRUN -> TIMEOUT [fdo#108887]

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          PASS -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-snb:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107725] +2

  * igt@kms_cursor_crc@cursor-256x256-dpms:
    - shard-glk:          PASS -> FAIL [fdo#103232] +2

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-glk:          PASS -> FAIL [fdo#104873]

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
    - shard-iclb:         PASS -> WARN [fdo#108336]

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          PASS -> FAIL [fdo#105363]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-apl:          PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#107724] +10

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +1

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108948] +1

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-iclb:         PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +4

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
    - shard-glk:          PASS -> FAIL [fdo#103166] +2

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
    - shard-apl:          PASS -> FAIL [fdo#103166]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#108950]

  * igt@kms_vblank@pipe-a-ts-continuation-idle:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +20

  * igt@pm_rpm@universal-planes:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#108654] / [fdo#108756]

  
#### Possible fixes ####

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-iclb:         TIMEOUT -> PASS

  * igt@gem_workarounds@suspend-resume-context:
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@i915_suspend@sysfs-reader:
    - shard-skl:          INCOMPLETE [fdo#104108] -> PASS

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
    - shard-glk:          FAIL [fdo#108145] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x256-sliding:
    - shard-glk:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-512x512-onscreen:
    - shard-apl:          INCOMPLETE [fdo#103927] -> SKIP

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
    - shard-skl:          FAIL [fdo#103184] -> PASS

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-apl:          FAIL [fdo#103060] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-apl:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_plane@plane-panning-top-left-pipe-c-planes:
    - shard-skl:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] -> PASS

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-kbl:          INCOMPLETE [fdo#103665] -> PASS

  * igt@pm_rpm@drm-resources-equal:
    - shard-iclb:         INCOMPLETE [fdo#108840] -> PASS

  * igt@pm_rpm@legacy-planes:
    - shard-iclb:         DMESG-WARN [fdo#108654] -> PASS

  
#### Warnings ####

  * igt@i915_selftest@live_contexts:
    - shard-iclb:         DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]

  * igt@kms_ccs@pipe-a-crc-primary-basic:
    - shard-iclb:         FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#108756]: https://bugs.freedesktop.org/show_bug.cgi?id=108756
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108887]: https://bugs.freedesktop.org/show_bug.cgi?id=108887
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5311 -> Patchwork_11087

  CI_DRM_5311: a42fd8bf199784ee4ff1cdb5ee03eedd9a535d4a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4746: 2c793666d8c8328733f5769b16ae5858fee97f3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11087: 3d73335eb4f6f635113e7c49cb70e7a9888972b8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11087/
_______________________________________________
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[PATCH v6] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function
v3: Mask off all HWSP writes on driver unload and engine cleanup.
v4: And what about the physical hwsp?
v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
v6: Rename set_hwsp as it was setting the mask not the hwsp register.

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |   9 --
 drivers/gpu/drm/i915/intel_engine_cs.c  |  23 +++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++++---------
 3 files changed, 91 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6f165f9ad2bf..f1a2aeb34e5e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -261,6 +261,23 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
 			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
 }
 
+static void set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
+{
+	/* Mask off all writes into the unknown HWSP */
+	set_hwsp_writemask(engine, ~0u);
+}
+
 static int
 intel_engine_setup(struct drm_i915_private *dev_priv,
 		   enum intel_engine_id id)
@@ -312,6 +329,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 
 	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 
+	/* Scrub mmio state on takeover */
+	intel_engine_sanitize_mmio(engine);
+
 	dev_priv->engine_class[info->class][info->instance] = engine;
 	dev_priv->engine[id] = engine;
 	return 0;
@@ -495,6 +515,9 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
 
 static void cleanup_status_page(struct intel_engine_cs *engine)
 {
+	/* Stop writing into the status page before returnig it to the system */
+	set_hwsp_writemask(engine, ~0u);
+
 	if (HWS_NEEDS_PHYSICAL(engine->i915)) {
 		void *addr = fetch_and_zero(&engine->status_page.page_addr);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..88f50e30a0c4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -379,11 +379,31 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 	return 0;
 }
 
-static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
+
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->id == RCS) {
+		if (INTEL_GEN(engine->i915) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
+	}
+
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct page *page = virt_to_page(engine->status_page.page_addr);
-	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
 	u32 addr;
 
 	addr = lower_32_bits(phys);
@@ -393,12 +413,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+{
+	struct page *page = virt_to_page(engine->status_page.page_addr);
+	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
+
+	set_hws_pga(engine, phys);
+	set_hwstam(engine, ~0u);
+}
+
+static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	i915_reg_t mmio;
+	i915_reg_t hwsp;
 
-	/* The ring status page addresses are no longer next to the rest of
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -410,56 +440,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		default:
 			GEM_BUG_ON(engine->id);
 		case RCS:
-			mmio = RENDER_HWS_PGA_GEN7;
+			hwsp = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
-			mmio = BLT_HWS_PGA_GEN7;
+			hwsp = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
-			mmio = BSD_HWS_PGA_GEN7;
+			hwsp = BSD_HWS_PGA_GEN7;
 			break;
 		case VECS:
-			mmio = VEBOX_HWS_PGA_GEN7;
+			hwsp = VEBOX_HWS_PGA_GEN7;
 			break;
 		}
 	} else if (IS_GEN(dev_priv, 6)) {
-		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
 	} else {
-		mmio = RING_HWS_PGA(engine->mmio_base);
+		hwsp = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
+	I915_WRITE(hwsp, offset);
+	POSTING_READ(hwsp);
+}
 
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+static void flush_cs_tlb(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
-	}
+	if (!IS_GEN_RANGE(dev_priv, 6, 7))
+		return;
 
-	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-	POSTING_READ(mmio);
+	/* ring should be idle before issuing a sync flush*/
+	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
-	/* Flush the TLB for this page */
-	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
-		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+	I915_WRITE(instpm,
+		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+				      INSTPM_SYNC_FLUSH));
+	if (intel_wait_for_register(dev_priv,
+				    instpm, INSTPM_SYNC_FLUSH, 0,
+				    1000))
+		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+			  engine->name);
+}
 
-		/* ring should be idle before issuing a sync flush*/
-		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+static void ring_setup_status_page(struct intel_engine_cs *engine)
+{
+	set_hwsp(engine, engine->status_page.ggtt_offset);
+	set_hwstam(engine, ~0u);
 
-		I915_WRITE(reg,
-			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-					      INSTPM_SYNC_FLUSH));
-		if (intel_wait_for_register(dev_priv,
-					    reg, INSTPM_SYNC_FLUSH, 0,
-					    1000))
-			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-				  engine->name);
-	}
+	flush_cs_tlb(engine);
 }
 
 static bool stop_ring(struct intel_engine_cs *engine)
@@ -529,7 +558,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
 	if (HWS_NEEDS_PHYSICAL(dev_priv))
 		ring_setup_phys_status_page(engine);
 	else
-		intel_ring_setup_status_page(engine);
+		ring_setup_status_page(engine);
 
 	intel_engine_reset_breadcrumbs(engine);
 
-- 
2.20.0

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Re: [PATCH v6] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Mon, Dec 17, 2018 at 03:20:55PM +0000, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> v2: Delazy and move the HWSTAM into its own function
> v3: Mask off all HWSP writes on driver unload and engine cleanup.
> v4: And what about the physical hwsp?
> v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
> daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
> v6: Rename set_hwsp as it was setting the mask not the hwsp register.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c         |   9 --
>  drivers/gpu/drm/i915/intel_engine_cs.c  |  23 +++++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++++---------
>  3 files changed, 91 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET(DE);
>  	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>  	GEN2_IRQ_RESET();
>  }
>  
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 6f165f9ad2bf..f1a2aeb34e5e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -261,6 +261,23 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
>  			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
>  }
>  
> +static void set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);

g4x/ilk don't have HWSTAM for the bsd. A quick test on my ilk shows that
the register at that offset stays at 0x0 even if written, so it might
even be safe. But maybe we shouldn't poke at things that aren't there?

> +
> +	if (INTEL_GEN(dev_priv) >= 3)
> +		I915_WRITE(hwstam, mask);
> +	else
> +		I915_WRITE16(hwstam, mask);
> +}
> +
> +static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
> +{
> +	/* Mask off all writes into the unknown HWSP */
> +	set_hwsp_writemask(engine, ~0u);
> +}
> +
>  static int
>  intel_engine_setup(struct drm_i915_private *dev_priv,
>  		   enum intel_engine_id id)
> @@ -312,6 +329,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
>  
>  	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
>  
> +	/* Scrub mmio state on takeover */
> +	intel_engine_sanitize_mmio(engine);
> +
>  	dev_priv->engine_class[info->class][info->instance] = engine;
>  	dev_priv->engine[id] = engine;
>  	return 0;
> @@ -495,6 +515,9 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
>  
>  static void cleanup_status_page(struct intel_engine_cs *engine)
>  {
> +	/* Stop writing into the status page before returnig it to the system */
> +	set_hwsp_writemask(engine, ~0u);
> +
>  	if (HWS_NEEDS_PHYSICAL(engine->i915)) {
>  		void *addr = fetch_and_zero(&engine->status_page.page_addr);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..88f50e30a0c4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -379,11 +379,31 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
>  	return 0;
>  }
>  
> -static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> +static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
> +

Ditto.

Otherwise this looks good to me.

> +	/*
> +	 * Keep the render interrupt unmasked as this papers over
> +	 * lost interrupts following a reset.
> +	 */
> +	if (engine->id == RCS) {
> +		if (INTEL_GEN(engine->i915) >= 6)
> +			mask &= ~BIT(0);
> +		else
> +			mask &= ~I915_USER_INTERRUPT;
> +	}
> +
> +	if (INTEL_GEN(dev_priv) >= 3)
> +		I915_WRITE(hwstam, mask);
> +	else
> +		I915_WRITE16(hwstam, mask);
> +}
> +
> +static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> -	struct page *page = virt_to_page(engine->status_page.page_addr);
> -	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
>  	u32 addr;
>  
>  	addr = lower_32_bits(phys);
> @@ -393,12 +413,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>  	I915_WRITE(HWS_PGA, addr);
>  }
>  
> -static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> +static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> +{
> +	struct page *page = virt_to_page(engine->status_page.page_addr);
> +	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
> +
> +	set_hws_pga(engine, phys);
> +	set_hwstam(engine, ~0u);
> +}
> +
> +static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> -	i915_reg_t mmio;
> +	i915_reg_t hwsp;
>  
> -	/* The ring status page addresses are no longer next to the rest of
> +	/*
> +	 * The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
>  	 */
>  	if (IS_GEN(dev_priv, 7)) {
> @@ -410,56 +440,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		default:
>  			GEM_BUG_ON(engine->id);
>  		case RCS:
> -			mmio = RENDER_HWS_PGA_GEN7;
> +			hwsp = RENDER_HWS_PGA_GEN7;
>  			break;
>  		case BCS:
> -			mmio = BLT_HWS_PGA_GEN7;
> +			hwsp = BLT_HWS_PGA_GEN7;
>  			break;
>  		case VCS:
> -			mmio = BSD_HWS_PGA_GEN7;
> +			hwsp = BSD_HWS_PGA_GEN7;
>  			break;
>  		case VECS:
> -			mmio = VEBOX_HWS_PGA_GEN7;
> +			hwsp = VEBOX_HWS_PGA_GEN7;
>  			break;
>  		}
>  	} else if (IS_GEN(dev_priv, 6)) {
> -		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> +		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
>  	} else {
> -		mmio = RING_HWS_PGA(engine->mmio_base);
> +		hwsp = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> -		u32 mask = ~0u;
> +	I915_WRITE(hwsp, offset);
> +	POSTING_READ(hwsp);
> +}
>  
> -		/*
> -		 * Keep the render interrupt unmasked as this papers over
> -		 * lost interrupts following a reset.
> -		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> +static void flush_cs_tlb(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
>  
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> -	}
> +	if (!IS_GEN_RANGE(dev_priv, 6, 7))
> +		return;
>  
> -	I915_WRITE(mmio, engine->status_page.ggtt_offset);
> -	POSTING_READ(mmio);
> +	/* ring should be idle before issuing a sync flush*/
> +	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
>  
> -	/* Flush the TLB for this page */
> -	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> -		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
> +	I915_WRITE(instpm,
> +		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> +				      INSTPM_SYNC_FLUSH));
> +	if (intel_wait_for_register(dev_priv,
> +				    instpm, INSTPM_SYNC_FLUSH, 0,
> +				    1000))
> +		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
> +			  engine->name);
> +}
>  
> -		/* ring should be idle before issuing a sync flush*/
> -		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
> +static void ring_setup_status_page(struct intel_engine_cs *engine)
> +{
> +	set_hwsp(engine, engine->status_page.ggtt_offset);
> +	set_hwstam(engine, ~0u);
>  
> -		I915_WRITE(reg,
> -			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> -					      INSTPM_SYNC_FLUSH));
> -		if (intel_wait_for_register(dev_priv,
> -					    reg, INSTPM_SYNC_FLUSH, 0,
> -					    1000))
> -			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
> -				  engine->name);
> -	}
> +	flush_cs_tlb(engine);
>  }
>  
>  static bool stop_ring(struct intel_engine_cs *engine)
> @@ -529,7 +558,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  	if (HWS_NEEDS_PHYSICAL(dev_priv))
>  		ring_setup_phys_status_page(engine);
>  	else
> -		intel_ring_setup_status_page(engine);
> +		ring_setup_status_page(engine);
>  
>  	intel_engine_reset_breadcrumbs(engine);
>  
> -- 
> 2.20.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v6] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Ville Syrjälä (2018-12-17 18:02:25)
> On Mon, Dec 17, 2018 at 03:20:55PM +0000, Chris Wilson wrote:
> > Having completed a test run of gem_eio across all machines in CI we also
> > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > the same HWSTAM workaround that was effective for gen6+ for all, as
> > although we haven't seen the same failure on gen4/5 it seems prudent to
> > keep the code the same.
> > 
> > As a consequence we can remove the extra setting of HWSTAM and apply the
> > register from a single site.
> > 
> > v2: Delazy and move the HWSTAM into its own function
> > v3: Mask off all HWSP writes on driver unload and engine cleanup.
> > v4: And what about the physical hwsp?
> > v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
> > daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
> > v6: Rename set_hwsp as it was setting the mask not the hwsp register.
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c         |   9 --
> >  drivers/gpu/drm/i915/intel_engine_cs.c  |  23 +++++
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++++---------
> >  3 files changed, 91 insertions(+), 48 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index e2dac9b5f4ce..0c7fc9890891 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> >  {
> >       struct drm_i915_private *dev_priv = to_i915(dev);
> >  
> > -     if (IS_GEN(dev_priv, 5))
> > -             I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET(DE);
> >       if (IS_GEN(dev_priv, 7))
> >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE16(HWSTAM, 0xffff);
> > -
> >       GEN2_IRQ_RESET();
> >  }
> >  
> > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET();
> >  }
> >  
> > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> >  
> >       i9xx_pipestat_irq_reset(dev_priv);
> >  
> > -     I915_WRITE(HWSTAM, 0xffffffff);
> > -
> >       GEN3_IRQ_RESET();
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 6f165f9ad2bf..f1a2aeb34e5e 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -261,6 +261,23 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
> >                        info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
> >  }
> >  
> > +static void set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> > +{
> > +     struct drm_i915_private *dev_priv = engine->i915;
> > +     i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
> 
> g4x/ilk don't have HWSTAM for the bsd. A quick test on my ilk shows that
> the register at that offset stays at 0x0 even if written, so it might
> even be safe. But maybe we shouldn't poke at things that aren't there?

Swines. Did they forget where the copy function was? Or did they use the
one mask for both status pages? Probably just don't maintain a copy of
the iir in hwsp/bsd.

Oh well, another respin.
-Chris
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Re: [PATCH v6] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Mon, Dec 17, 2018 at 06:07:45PM +0000, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-12-17 18:02:25)
> > On Mon, Dec 17, 2018 at 03:20:55PM +0000, Chris Wilson wrote:
> > > Having completed a test run of gem_eio across all machines in CI we also
> > > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > > the same HWSTAM workaround that was effective for gen6+ for all, as
> > > although we haven't seen the same failure on gen4/5 it seems prudent to
> > > keep the code the same.
> > > 
> > > As a consequence we can remove the extra setting of HWSTAM and apply the
> > > register from a single site.
> > > 
> > > v2: Delazy and move the HWSTAM into its own function
> > > v3: Mask off all HWSP writes on driver unload and engine cleanup.
> > > v4: And what about the physical hwsp?
> > > v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
> > > daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
> > > v6: Rename set_hwsp as it was setting the mask not the hwsp register.
> > > 
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c         |   9 --
> > >  drivers/gpu/drm/i915/intel_engine_cs.c  |  23 +++++
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++++---------
> > >  3 files changed, 91 insertions(+), 48 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index e2dac9b5f4ce..0c7fc9890891 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
> > >  {
> > >       struct drm_i915_private *dev_priv = to_i915(dev);
> > >  
> > > -     if (IS_GEN(dev_priv, 5))
> > > -             I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET(DE);
> > >       if (IS_GEN(dev_priv, 7))
> > >               I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> > > @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE16(HWSTAM, 0xffff);
> > > -
> > >       GEN2_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > >  
> > > @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
> > >  
> > >       i9xx_pipestat_irq_reset(dev_priv);
> > >  
> > > -     I915_WRITE(HWSTAM, 0xffffffff);
> > > -
> > >       GEN3_IRQ_RESET();
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > index 6f165f9ad2bf..f1a2aeb34e5e 100644
> > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > @@ -261,6 +261,23 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
> > >                        info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
> > >  }
> > >  
> > > +static void set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> > > +{
> > > +     struct drm_i915_private *dev_priv = engine->i915;
> > > +     i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
> > 
> > g4x/ilk don't have HWSTAM for the bsd. A quick test on my ilk shows that
> > the register at that offset stays at 0x0 even if written, so it might
> > even be safe. But maybe we shouldn't poke at things that aren't there?
> 
> Swines. Did they forget where the copy function was? Or did they use the
> one mask for both status pages? Probably just don't maintain a copy of
> the iir in hwsp/bsd.

Not sure. Morbid curiosity might force me to find out one day.

-- 
Ville Syrjälä
Intel
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✓ Fi.CI.BAT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev7)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5324 -> Patchwork_11108
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/7/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11108 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6700hq:      DMESG-WARN [fdo#105998] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - fi-byt-clapper:     FAIL [fdo#107362] -> PASS

  
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718


Participating hosts (49 -> 45)
------------------------------

  Additional (1): fi-cfl-8109u 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 


Build changes
-------------

    * Linux: CI_DRM_5324 -> Patchwork_11108

  CI_DRM_5324: 93009153b9bde1d65ca49bb1729cd1111591144b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4748: 90c76cb9bb47a5a3ebb34ad6b1a557bc02d39713 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11108: 7029bd589bfc719f2b8a3e06bf4cbe7cfdeaec62 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7029bd589bfc drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11108/
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✓ Fi.CI.IGT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev7)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5324_full -> Patchwork_11108_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11108_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11108_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11108_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-snb:          SKIP -> PASS

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          SKIP -> PASS

  
Known issues
------------

  Here are the changes found in Patchwork_11108_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@pi-ringfull-vebox:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]

  * igt@i915_selftest@live_workarounds:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#108954]

  * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
    - shard-skl:          PASS -> FAIL [fdo#107815] / [fdo#108228] / [fdo#108470]

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#102614]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-glk:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_chv_cursor_fail@pipe-b-64x64-left-edge:
    - shard-skl:          PASS -> FAIL [fdo#104671]

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +2

  * igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
    - shard-skl:          PASS -> FAIL [fdo#103184]

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          PASS -> FAIL [fdo#107791]

  * igt@kms_fbcon_fbt@psr:
    - shard-skl:          NOTRUN -> FAIL [fdo#107882]

  * igt@kms_flip_tiling@flip-yf-tiled:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +1
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-glk:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render:
    - shard-skl:          PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-skl:          PASS -> FAIL [fdo#105682] +1

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-skl:          PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - shard-skl:          PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-apl:          PASS -> FAIL [fdo#103166] +1
    - shard-iclb:         PASS -> FAIL [fdo#103166]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +2

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#108950]

  * igt@kms_setmode@basic:
    - shard-apl:          PASS -> FAIL [fdo#99912]
    - shard-skl:          NOTRUN -> FAIL [fdo#99912]
    - shard-hsw:          PASS -> FAIL [fdo#99912]
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@kms_universal_plane@universal-plane-pipe-b-functional:
    - shard-glk:          PASS -> FAIL [fdo#103166] +1

  * igt@pm_rpm@fences-dpms:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807]

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-iclb:         DMESG-WARN [fdo#107956] -> PASS +1

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-128x42-onscreen:
    - shard-skl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-size-change:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          FAIL [fdo#105454] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
    - shard-skl:          FAIL [fdo#108472] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-iclb:         FAIL [fdo#105683] -> PASS

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +5

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - shard-apl:          DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +20

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
    - shard-skl:          FAIL [fdo#107362] -> PASS

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
    - shard-apl:          FAIL [fdo#103166] -> PASS
    - shard-iclb:         FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> PASS
    - shard-glk:          DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS

  * igt@pm_rpm@modeset-lpsp-stress:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS

  
#### Warnings ####

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-apl:          DMESG-FAIL [fdo#103166] / [fdo#103558] / [fdo#105602] -> FAIL [fdo#103166]

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
  [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
  [fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
  [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
  [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5324 -> Patchwork_11108

  CI_DRM_5324: 93009153b9bde1d65ca49bb1729cd1111591144b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4748: 90c76cb9bb47a5a3ebb34ad6b1a557bc02d39713 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11108: 7029bd589bfc719f2b8a3e06bf4cbe7cfdeaec62 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11108/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v7] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

v2: Delazy and move the HWSTAM into its own function
v3: Mask off all HWSP writes on driver unload and engine cleanup.
v4: And what about the physical hwsp?
v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
v6: Rename set_hwsp as it was setting the mask not the hwsp register.
v7: Ville pointed out that although vcs(bsd) was introduced for g4x/ilk,
per-engine HWSTAM was not introduced until gen6!

References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |   9 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  31 ++++++++
 drivers/gpu/drm/i915/intel_lrc.c        |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 101 +++++++++++++++---------
 drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +
 5 files changed, 96 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2dac9b5f4ce..0c7fc9890891 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN(dev_priv, 5))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN(dev_priv, 7))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6f165f9ad2bf..d3dec31df123 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -261,6 +261,31 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
 			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
 }
 
+void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t hwstam;
+
+	/*
+	 * Though they added more rings on g4x/ilk, they did not add
+	 * per-engine HWSTAM until gen6.
+	 */
+	if (INTEL_GEN(dev_priv) < 6 && engine->class != RENDER_CLASS)
+		return;
+
+	hwstam = RING_HWSTAM(engine->mmio_base);
+	if (INTEL_GEN(dev_priv) >= 3)
+		I915_WRITE(hwstam, mask);
+	else
+		I915_WRITE16(hwstam, mask);
+}
+
+static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
+{
+	/* Mask off all writes into the unknown HWSP */
+	intel_engine_set_hwsp_writemask(engine, ~0u);
+}
+
 static int
 intel_engine_setup(struct drm_i915_private *dev_priv,
 		   enum intel_engine_id id)
@@ -312,6 +337,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 
 	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 
+	/* Scrub mmio state on takeover */
+	intel_engine_sanitize_mmio(engine);
+
 	dev_priv->engine_class[info->class][info->instance] = engine;
 	dev_priv->engine[id] = engine;
 	return 0;
@@ -495,6 +523,9 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
 
 static void cleanup_status_page(struct intel_engine_cs *engine)
 {
+	/* Prevent writes into HWSP after returning the page to the system */
+	intel_engine_set_hwsp_writemask(engine, ~0u);
+
 	if (HWS_NEEDS_PHYSICAL(engine->i915)) {
 		void *addr = fetch_and_zero(&engine->status_page.page_addr);
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c9748f391fe..b05d0561f99a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1655,7 +1655,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
+	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
 
 	/*
 	 * Make sure we're not enabling the new 12-deep CSB
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdeca2b877c9..65fd92eb071d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -379,11 +379,25 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 	return 0;
 }
 
-static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
+{
+	/*
+	 * Keep the render interrupt unmasked as this papers over
+	 * lost interrupts following a reset.
+	 */
+	if (engine->class == RENDER_CLASS) {
+		if (INTEL_GEN(engine->i915) >= 6)
+			mask &= ~BIT(0);
+		else
+			mask &= ~I915_USER_INTERRUPT;
+	}
+
+	intel_engine_set_hwsp_writemask(engine, mask);
+}
+
+static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct page *page = virt_to_page(engine->status_page.page_addr);
-	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
 	u32 addr;
 
 	addr = lower_32_bits(phys);
@@ -393,12 +407,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
+static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
+{
+	struct page *page = virt_to_page(engine->status_page.page_addr);
+	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
+
+	set_hws_pga(engine, phys);
+	set_hwstam(engine, ~0u);
+}
+
+static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	i915_reg_t mmio;
+	i915_reg_t hwsp;
 
-	/* The ring status page addresses are no longer next to the rest of
+	/*
+	 * The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
 	 */
 	if (IS_GEN(dev_priv, 7)) {
@@ -410,56 +434,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		default:
 			GEM_BUG_ON(engine->id);
 		case RCS:
-			mmio = RENDER_HWS_PGA_GEN7;
+			hwsp = RENDER_HWS_PGA_GEN7;
 			break;
 		case BCS:
-			mmio = BLT_HWS_PGA_GEN7;
+			hwsp = BLT_HWS_PGA_GEN7;
 			break;
 		case VCS:
-			mmio = BSD_HWS_PGA_GEN7;
+			hwsp = BSD_HWS_PGA_GEN7;
 			break;
 		case VECS:
-			mmio = VEBOX_HWS_PGA_GEN7;
+			hwsp = VEBOX_HWS_PGA_GEN7;
 			break;
 		}
 	} else if (IS_GEN(dev_priv, 6)) {
-		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
 	} else {
-		mmio = RING_HWS_PGA(engine->mmio_base);
+		hwsp = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		u32 mask = ~0u;
+	I915_WRITE(hwsp, offset);
+	POSTING_READ(hwsp);
+}
 
-		/*
-		 * Keep the render interrupt unmasked as this papers over
-		 * lost interrupts following a reset.
-		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+static void flush_cs_tlb(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
-	}
+	if (!IS_GEN_RANGE(dev_priv, 6, 7))
+		return;
 
-	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-	POSTING_READ(mmio);
+	/* ring should be idle before issuing a sync flush*/
+	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
-	/* Flush the TLB for this page */
-	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
-		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+	I915_WRITE(instpm,
+		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+				      INSTPM_SYNC_FLUSH));
+	if (intel_wait_for_register(dev_priv,
+				    instpm, INSTPM_SYNC_FLUSH, 0,
+				    1000))
+		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+			  engine->name);
+}
 
-		/* ring should be idle before issuing a sync flush*/
-		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+static void ring_setup_status_page(struct intel_engine_cs *engine)
+{
+	set_hwsp(engine, engine->status_page.ggtt_offset);
+	set_hwstam(engine, ~0u);
 
-		I915_WRITE(reg,
-			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-					      INSTPM_SYNC_FLUSH));
-		if (intel_wait_for_register(dev_priv,
-					    reg, INSTPM_SYNC_FLUSH, 0,
-					    1000))
-			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-				  engine->name);
-	}
+	flush_cs_tlb(engine);
 }
 
 static bool stop_ring(struct intel_engine_cs *engine)
@@ -529,7 +552,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
 	if (HWS_NEEDS_PHYSICAL(dev_priv))
 		ring_setup_phys_status_page(engine);
 	else
-		intel_ring_setup_status_page(engine);
+		ring_setup_status_page(engine);
 
 	intel_engine_reset_breadcrumbs(engine);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1ae74e579386..6b41b9ce5f5b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -903,6 +903,8 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
 
+void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
+
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
 
-- 
2.20.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v7] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Ville Syrjälä]

On Tue, Dec 18, 2018 at 10:27:12AM +0000, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> v2: Delazy and move the HWSTAM into its own function
> v3: Mask off all HWSP writes on driver unload and engine cleanup.
> v4: And what about the physical hwsp?
> v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
> daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
> v6: Rename set_hwsp as it was setting the mask not the hwsp register.
> v7: Ville pointed out that although vcs(bsd) was introduced for g4x/ilk,
> per-engine HWSTAM was not introduced until gen6!
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c         |   9 ---
>  drivers/gpu/drm/i915/intel_engine_cs.c  |  31 ++++++++
>  drivers/gpu/drm/i915/intel_lrc.c        |   2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 101 +++++++++++++++---------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +
>  5 files changed, 96 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET(DE);
>  	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>  	GEN2_IRQ_RESET();
>  }
>  
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>  	GEN3_IRQ_RESET();
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 6f165f9ad2bf..d3dec31df123 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -261,6 +261,31 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
>  			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
>  }
>  
> +void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t hwstam;
> +
> +	/*
> +	 * Though they added more rings on g4x/ilk, they did not add
> +	 * per-engine HWSTAM until gen6.
> +	 */
> +	if (INTEL_GEN(dev_priv) < 6 && engine->class != RENDER_CLASS)
> +		return;
> +
> +	hwstam = RING_HWSTAM(engine->mmio_base);
> +	if (INTEL_GEN(dev_priv) >= 3)
> +		I915_WRITE(hwstam, mask);
> +	else
> +		I915_WRITE16(hwstam, mask);
> +}
> +
> +static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
> +{
> +	/* Mask off all writes into the unknown HWSP */
> +	intel_engine_set_hwsp_writemask(engine, ~0u);
> +}
> +
>  static int
>  intel_engine_setup(struct drm_i915_private *dev_priv,
>  		   enum intel_engine_id id)
> @@ -312,6 +337,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
>  
>  	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
>  
> +	/* Scrub mmio state on takeover */
> +	intel_engine_sanitize_mmio(engine);
> +
>  	dev_priv->engine_class[info->class][info->instance] = engine;
>  	dev_priv->engine[id] = engine;
>  	return 0;
> @@ -495,6 +523,9 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
>  
>  static void cleanup_status_page(struct intel_engine_cs *engine)
>  {
> +	/* Prevent writes into HWSP after returning the page to the system */
> +	intel_engine_set_hwsp_writemask(engine, ~0u);
> +
>  	if (HWS_NEEDS_PHYSICAL(engine->i915)) {
>  		void *addr = fetch_and_zero(&engine->status_page.page_addr);
>  
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 1c9748f391fe..b05d0561f99a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1655,7 +1655,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
> -	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> +	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>  
>  	/*
>  	 * Make sure we're not enabling the new 12-deep CSB
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..65fd92eb071d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -379,11 +379,25 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode)
>  	return 0;
>  }
>  
> -static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> +static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> +{
> +	/*
> +	 * Keep the render interrupt unmasked as this papers over
> +	 * lost interrupts following a reset.
> +	 */
> +	if (engine->class == RENDER_CLASS) {
> +		if (INTEL_GEN(engine->i915) >= 6)
> +			mask &= ~BIT(0);
> +		else
> +			mask &= ~I915_USER_INTERRUPT;
> +	}
> +
> +	intel_engine_set_hwsp_writemask(engine, mask);
> +}
> +
> +static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> -	struct page *page = virt_to_page(engine->status_page.page_addr);
> -	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
>  	u32 addr;
>  
>  	addr = lower_32_bits(phys);
> @@ -393,12 +407,22 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>  	I915_WRITE(HWS_PGA, addr);
>  }
>  
> -static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> +static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> +{
> +	struct page *page = virt_to_page(engine->status_page.page_addr);
> +	phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
> +
> +	set_hws_pga(engine, phys);
> +	set_hwstam(engine, ~0u);
> +}
> +
> +static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> -	i915_reg_t mmio;
> +	i915_reg_t hwsp;
>  
> -	/* The ring status page addresses are no longer next to the rest of
> +	/*
> +	 * The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
>  	 */
>  	if (IS_GEN(dev_priv, 7)) {
> @@ -410,56 +434,55 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		default:
>  			GEM_BUG_ON(engine->id);
>  		case RCS:
> -			mmio = RENDER_HWS_PGA_GEN7;
> +			hwsp = RENDER_HWS_PGA_GEN7;
>  			break;
>  		case BCS:
> -			mmio = BLT_HWS_PGA_GEN7;
> +			hwsp = BLT_HWS_PGA_GEN7;
>  			break;
>  		case VCS:
> -			mmio = BSD_HWS_PGA_GEN7;
> +			hwsp = BSD_HWS_PGA_GEN7;
>  			break;
>  		case VECS:
> -			mmio = VEBOX_HWS_PGA_GEN7;
> +			hwsp = VEBOX_HWS_PGA_GEN7;
>  			break;
>  		}
>  	} else if (IS_GEN(dev_priv, 6)) {
> -		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> +		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
>  	} else {
> -		mmio = RING_HWS_PGA(engine->mmio_base);
> +		hwsp = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> -		u32 mask = ~0u;
> +	I915_WRITE(hwsp, offset);
> +	POSTING_READ(hwsp);
> +}
>  
> -		/*
> -		 * Keep the render interrupt unmasked as this papers over
> -		 * lost interrupts following a reset.
> -		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> +static void flush_cs_tlb(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
>  
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> -	}
> +	if (!IS_GEN_RANGE(dev_priv, 6, 7))
> +		return;
>  
> -	I915_WRITE(mmio, engine->status_page.ggtt_offset);
> -	POSTING_READ(mmio);
> +	/* ring should be idle before issuing a sync flush*/
> +	WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
>  
> -	/* Flush the TLB for this page */
> -	if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> -		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
> +	I915_WRITE(instpm,
> +		   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> +				      INSTPM_SYNC_FLUSH));
> +	if (intel_wait_for_register(dev_priv,
> +				    instpm, INSTPM_SYNC_FLUSH, 0,
> +				    1000))
> +		DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
> +			  engine->name);
> +}
>  
> -		/* ring should be idle before issuing a sync flush*/
> -		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
> +static void ring_setup_status_page(struct intel_engine_cs *engine)
> +{
> +	set_hwsp(engine, engine->status_page.ggtt_offset);
> +	set_hwstam(engine, ~0u);
>  
> -		I915_WRITE(reg,
> -			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> -					      INSTPM_SYNC_FLUSH));
> -		if (intel_wait_for_register(dev_priv,
> -					    reg, INSTPM_SYNC_FLUSH, 0,
> -					    1000))
> -			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
> -				  engine->name);
> -	}
> +	flush_cs_tlb(engine);
>  }
>  
>  static bool stop_ring(struct intel_engine_cs *engine)
> @@ -529,7 +552,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  	if (HWS_NEEDS_PHYSICAL(dev_priv))
>  		ring_setup_phys_status_page(engine);
>  	else
> -		intel_ring_setup_status_page(engine);
> +		ring_setup_status_page(engine);
>  
>  	intel_engine_reset_breadcrumbs(engine);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 1ae74e579386..6b41b9ce5f5b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -903,6 +903,8 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
>  int intel_engine_stop_cs(struct intel_engine_cs *engine);
>  void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
>  
> +void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
> +
>  u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
>  u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
>  
> -- 
> 2.20.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v7] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Quoting Ville Syrjälä (2018-12-18 14:15:09)
> On Tue, Dec 18, 2018 at 10:27:12AM +0000, Chris Wilson wrote:
> > Having completed a test run of gem_eio across all machines in CI we also
> > observe the phenomenon (of lost interrupts after resetting the GPU) on
> > gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> > the same HWSTAM workaround that was effective for gen6+ for all, as
> > although we haven't seen the same failure on gen4/5 it seems prudent to
> > keep the code the same.
> > 
> > As a consequence we can remove the extra setting of HWSTAM and apply the
> > register from a single site.
> > 
> > v2: Delazy and move the HWSTAM into its own function
> > v3: Mask off all HWSP writes on driver unload and engine cleanup.
> > v4: And what about the physical hwsp?
> > v5: No, engine->init_hw() is not called from driver_init_hw(), don't be
> > daft. Really scrub HWSTAM as early as we can in driver_init_mmio()
> > v6: Rename set_hwsp as it was setting the mask not the hwsp register.
> > v7: Ville pointed out that although vcs(bsd) was introduced for g4x/ilk,
> > per-engine HWSTAM was not introduced until gen6!
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks a lot for the thorough checking. Hopefully this will be the last
we see of that blasted live_hangcheck failure on brw!
-Chris
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✓ Fi.CI.BAT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev8)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5325 -> Patchwork_11113
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53979/revisions/8/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11113 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       PASS -> DMESG-WARN [fdo#108965]

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-bxt-j4205:       PASS -> INCOMPLETE [fdo#103927]
    - fi-ilk-650:         PASS -> DMESG-WARN [fdo#106387] +1

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * {igt@runner@aborted}:
    - fi-bxt-j4205:       NOTRUN -> FAIL [fdo#103927]

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-small-copy-xy:
    - fi-glk-dsi:         INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - fi-byt-clapper:     FAIL [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (49 -> 45)
------------------------------

  Additional (1): fi-cfl-8109u 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y 


Build changes
-------------

    * Linux: CI_DRM_5325 -> Patchwork_11113

  CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11113: e60f8a2ea67991c16e4c2d3432dc4d2ce17321aa @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e60f8a2ea679 drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11113/
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✓ Fi.CI.IGT: success for drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen (rev8)
URL   : https://patchwork.freedesktop.org/series/53979/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5325_full -> Patchwork_11113_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11113_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11113_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11113_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-snb:          PASS -> SKIP +1

  * igt@perf_pmu@rc6:
    - shard-kbl:          PASS -> SKIP

  
Known issues
------------

  Here are the changes found in Patchwork_11113_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_create@forked:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  * igt@gem_exec_schedule@pi-ringfull-render:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]

  * igt@gem_exec_schedule@pi-ringfull-vebox:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103158]

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-skl:          NOTRUN -> TIMEOUT [fdo#108887]

  * igt@kms_atomic_transition@plane-all-transition:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +2

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +2

  * igt@kms_cursor_crc@cursor-128x42-onscreen:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x256-onscreen:
    - shard-glk:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-size-change:
    - shard-apl:          PASS -> FAIL [fdo#103232] +2

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-glk:          PASS -> FAIL [fdo#103060]

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          PASS -> FAIL [fdo#102887]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-glk:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-iclb:         PASS -> FAIL [fdo#105683]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +1

  * igt@kms_plane@pixel-format-pipe-c-planes:
    - shard-glk:          PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-apl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - shard-apl:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-iclb:         PASS -> FAIL [fdo#103166] +2

  * igt@kms_psr@no_drrs:
    - shard-iclb:         PASS -> FAIL [fdo#108341]

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> FAIL [fdo#100047]

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-kbl:          PASS -> INCOMPLETE [fdo#103665]

  * igt@pm_rpm@modeset-non-lpsp-stress:
    - shard-skl:          SKIP -> INCOMPLETE [fdo#107807]

  * igt@pm_rps@min-max-config-loaded:
    - shard-iclb:         NOTRUN -> FAIL [fdo#102250]

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-glk:          FAIL [fdo#107799] -> PASS

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS +1

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          FAIL [fdo#106641] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-iclb:         DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-skl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-b-degamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-glk:          FAIL [fdo#103232] -> PASS +2
    - shard-apl:          FAIL [fdo#103232] -> PASS +3

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-apl:          FAIL [fdo#103060] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +9
    - shard-glk:          FAIL [fdo#103167] -> PASS +5

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +2

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-apl:          FAIL [fdo#108948] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-glk:          FAIL [fdo#108145] -> PASS +1

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +4

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          DMESG-WARN [fdo#105604] -> PASS

  * igt@kms_setmode@basic:
    - shard-hsw:          FAIL [fdo#99912] -> PASS

  * igt@pm_rpm@debugfs-read:
    - shard-iclb:         DMESG-WARN [fdo#108654] -> PASS

  * igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-iclb:         INCOMPLETE [fdo#108840] -> SKIP

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-skl:          DMESG-WARN [fdo#108784] -> INCOMPLETE [fdo#106886]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-iclb:         FAIL [fdo#103232] -> DMESG-FAIL [fdo#103232] / [fdo#107724]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          DMESG-WARN [fdo#105763] / [fdo#106538] -> DMESG-FAIL [fdo#105763] / [fdo#106538]

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108887]: https://bugs.freedesktop.org/show_bug.cgi?id=108887
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5325 -> Patchwork_11113

  CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11113: e60f8a2ea67991c16e4c2d3432dc4d2ce17321aa @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11113/
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