Re: [PATCH 5/6] drm/i915/ringbuffer: Move irq seqno barrier to the GPU for gen5

[Chris Wilson <chris@chris-wilson.co.uk>]

Quoting Tvrtko Ursulin (2018-12-31 10:49:37)
> 
> On 28/12/2018 17:16, Chris Wilson wrote:
> > -static void
> > -gen5_seqno_barrier(struct intel_engine_cs *engine)
> > +#define GEN5_WA_STORES 8 /* must be at least 1! */
> > +static void gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> >   {
> > -     /* MI_STORE are internally buffered by the GPU and not flushed
> > -      * either by MI_FLUSH or SyncFlush or any other combination of
> > -      * MI commands.
> > -      *
> > -      * "Only the submission of the store operation is guaranteed.
> > -      * The write result will be complete (coherent) some time later
> > -      * (this is practically a finite period but there is no guaranteed
> > -      * latency)."
> > -      *
> > -      * Empirically, we observe that we need a delay of at least 75us to
> > -      * be sure that the seqno write is visible by the CPU.
> > -      */
> > -     usleep_range(125, 250);
> 
> How much time for 8 store dw on gen5? I mean, does it have any relation 
> to this sleep?

Throughput measurement puts it at around 1us. So dramatically less (just
every time not after the occasional interrupt). However, given that it
solves, at least one, MI incoherency issue it is required for correct
breadcrumb flushing.
-Chris
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