From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/6] drm/i915/ringbuffer: Move irq seqno barrier to the GPU for gen5
Date: Mon, 31 Dec 2018 11:21:27 +0000 [thread overview]
Message-ID: <19c95bdb-1b12-4579-d47e-6d4cd8b1d242@linux.intel.com> (raw)
In-Reply-To: <154625443401.12016.16721618025518803204@skylake-alporthouse-com>
On 31/12/2018 11:07, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-12-31 10:49:37)
>>
>> On 28/12/2018 17:16, Chris Wilson wrote:
>>> @@ -2191,6 +2193,10 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>>>
>>> engine->emit_breadcrumb = i9xx_emit_breadcrumb;
>>> engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
>>> + if (IS_GEN(dev_priv, 5)) {
>>> + engine->emit_breadcrumb = gen5_emit_breadcrumb;
>>> + engine->emit_breadcrumb_sz = gen5_emit_breadcrumb_sz;
>>
>> I'll only observe in passing that we lost some consistency in this
>> approximate area of the code regarding when we are happy to overwrite
>> the pointers, versus when we do if-ladders-or-so to avoid that.
>
> I hear you, but my thinking was that this was the default for gen5 where
> we use the same function for both classes of engine. And emit_bb_start
> already looked odd there :) You do remember inconsistency is both my
> middle names?
>
> Back to tables? With semaphores gone, we've removed the runtime
> conditionals, so we just have a bunch of common functions (for reset
> handling). The counter point is that some subarches (gen2) only vary in
> a single function pointer, so we end up with a lot of duplicate, but
> const, tables.
>
> I definitely prefer the repetition in tables when it comes to figuring
> out exactly what set of functions are used together for any particular
> setup.
I was also looking at intel_init_bsd_ring_buffer before in the series -
it ends up if gen >= 6, if !gen6, if gen6, if gen5, else, something like
that..
I think for now we apply -EDONTCARE here and someone comes back later if
it bugs them enough.
Regards,
Tvrtko
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next prev parent reply other threads:[~2018-12-31 11:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-28 17:16 [PATCH 1/6] drm/i915: Remove redundant trailing request flush Chris Wilson
2018-12-28 17:16 ` [PATCH 2/6] drm/i915/ringbuffer: Remove irq-seqno w/a for gen6/7 rcs Chris Wilson
2018-12-31 10:28 ` Tvrtko Ursulin
2018-12-28 17:16 ` [PATCH 3/6] drm/i915/ringbuffer: Remove irq-seqno w/a for gen6 xcs Chris Wilson
2018-12-31 10:31 ` Tvrtko Ursulin
2018-12-28 17:16 ` [PATCH 4/6] drm/i915/ringbuffer: Move irq seqno barrier to the GPU for gen7 Chris Wilson
2018-12-31 10:43 ` Tvrtko Ursulin
2018-12-31 10:56 ` Chris Wilson
2018-12-28 17:16 ` [PATCH 5/6] drm/i915/ringbuffer: Move irq seqno barrier to the GPU for gen5 Chris Wilson
2018-12-31 10:49 ` Tvrtko Ursulin
2018-12-31 11:07 ` Chris Wilson
2018-12-31 11:21 ` Tvrtko Ursulin [this message]
2018-12-31 15:25 ` Chris Wilson
2018-12-28 17:16 ` [PATCH 6/6] drm/i915: Drop unused engine->irq_seqno_barrier w/a Chris Wilson
2018-12-31 11:35 ` Tvrtko Ursulin
2018-12-28 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Remove redundant trailing request flush Patchwork
2018-12-28 18:18 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-31 15:38 ` Chris Wilson
2018-12-28 22:00 ` ✓ Fi.CI.IGT: " Patchwork
2018-12-31 10:25 ` [PATCH 1/6] " Tvrtko Ursulin
2018-12-31 10:32 ` Chris Wilson
2018-12-31 11:24 ` Tvrtko Ursulin
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