[PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[S, Shirish]

The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.

"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"

This patch extends the quirk to make it applicable till 7th Generation,
so as to address the below warning at boot:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S <shirish.s@amd.com>
---
 arch/x86/kernel/cpu/mce/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 672c722..051b536 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 		 * they're not supported there.
 		 */
 		if (c->x86 == 0x15 &&
-		    (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
+		    (c->x86_model >= 0x10 && c->x86_model <= 0x7f)) {
 			int i;
 			u64 hwcr;
 			bool need_toggle;
-- 
2.7.4

[PATCH 2/2] x86/mce/amd: Ensure quirks are applied in resume path as well

[S, Shirish]

This patch adds threshold quirk applicable for family 15
in resume path as well, since mce_amd_feature_init()
does not have quirks applied when originating from mce_syscore_resume(),
resulting in the below message at every successful resume:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S <shirish.s@amd.com>
---
 arch/x86/kernel/cpu/mce/amd.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 89298c8..27cbf66 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -545,6 +545,34 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 	return offset;
 }
 
+void disable_err_thresholding(struct cpuinfo_x86 *c)
+{
+	int i;
+	u64 hwcr;
+	bool need_toggle;
+	u32 msrs[] = {
+		0x00000413, /* MC4_MISC0 */
+		0xc0000408, /* MC4_MISC1 */
+	};
+
+	if (c->x86_model >= 0x10 && c->x86_model <= 0x7f) {
+		rdmsrl(MSR_K7_HWCR, hwcr);
+
+		/* McStatusWrEn has to be set */
+		need_toggle = !(hwcr & BIT(18));
+
+		if (need_toggle)
+			wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
+
+		/* Clear CntP bit safely */
+		for (i = 0; i < ARRAY_SIZE(msrs); i++)
+			msr_clear_bit(msrs[i], 62);
+
+		/* restore old settings */
+		if (need_toggle)
+			wrmsrl(MSR_K7_HWCR, hwcr);
+	}
+}
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
@@ -552,6 +580,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 	unsigned int bank, block, cpu = smp_processor_id();
 	int offset = -1;
 
+	/* Disable error thresholding bank in S3 resume path as well,
+	 * for 15h family
+	 */
+	if (c->x86 == 0x15)
+		disable_err_thresholding(c);
+
 	for (bank = 0; bank < mca_cfg.banks; ++bank) {
 		if (mce_flags.smca)
 			smca_configure(bank, cpu);
-- 
2.7.4

Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[Borislav Petkov]

On Thu, Jan 10, 2019 at 08:02:47AM +0000, S wrote:
> I wanted to send the patch with you in recipient field rather than cc, 
> unfortunately --cc remained in the git-send command

Next time look at the manpage:

git send-email --to <recipient> --cc <other recipient> --suppress-cc=all

and the last switch stops git from adding more CCs.

Make sure you add "--dry-run" to check whether it adds the proper
CCs/Tos first and then send it for real.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[S]

Hi Borislav,

On 1/10/2019 3:24 AM, Borislav Petkov wrote:
> On Mon, Jan 07, 2019 at 10:37:17AM +0000, S, Shirish wrote:
>> The below patch added this quirk only for the first generation of family
>> 15 processors, over time its noticed that its required for later
>> generations too.
>>
>> "575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
>> models"
>>
>> This patch extends the quirk to make it applicable till 7th Generation,
> Avoid having "This patch" or "This commit" in the commit message. It is
> tautologically useless.

Agree, have made the changes and re-spun re-spun v2 here: 
https://lkml.org/lkml/2019/1/10/69

I wanted to send the patch with you in recipient field rather than cc, 
unfortunately --cc remained in the git-send command

that i used, let me know i need to re-send it or you can see the patch.

Thanks.

Regards,

Shirish S

> Also, do
>
> $ git grep 'This patch' Documentation/process
>
> for more details.
>
-- 
Regards,
Shirish S

Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[Borislav Petkov]

On Mon, Jan 07, 2019 at 10:37:17AM +0000, S, Shirish wrote:
> The below patch added this quirk only for the first generation of family
> 15 processors, over time its noticed that its required for later
> generations too.
> 
> "575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
> models"
> 
> This patch extends the quirk to make it applicable till 7th Generation,

Avoid having "This patch" or "This commit" in the commit message. It is
tautologically useless.

Also, do

$ git grep 'This patch' Documentation/process

for more details.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

[S, Shirish]

The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.

"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"

This patch extends the quirk to make it applicable till 7th Generation,
so as to address the below warning at boot:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S <shirish.s@amd.com>
---
 arch/x86/kernel/cpu/mce/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 672c722..051b536 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 		 * they're not supported there.
 		 */
 		if (c->x86 == 0x15 &&
-		    (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
+		    (c->x86_model >= 0x10 && c->x86_model <= 0x7f)) {
 			int i;
 			u64 hwcr;
 			bool need_toggle;
-- 
2.7.4