* [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
@ 2019-01-04 17:37 José Roberto de Souza
2019-01-04 17:59 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-01-04 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
According to Workaround database ICL also needs
WaEnablePreemptionGranularityControlByUMD, to allow userspace to do
fine-granularity preemptions per-context.
BSpec: 11348
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 480c53a2ecb5..bbc5a66faa07 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */
whitelist_reg(w, GEN8_CS_CHICKEN1);
/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
@@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+ /* WaEnablePreemptionGranularityControlByUMD:icl */
+ whitelist_reg(w, GEN8_CS_CHICKEN1);
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
@@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
- if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
+ if (IS_GEN_RANGE(i915, 9, 11)) {
+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
GEN9_FFSC_PERCTX_PREEMPT_CTRL);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-04 17:37 [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD José Roberto de Souza @ 2019-01-04 17:59 ` Patchwork 2019-01-04 20:44 ` ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-01-04 17:59 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD URL : https://patchwork.freedesktop.org/series/54751/ State : success == Summary == CI Bug Log - changes from CI_DRM_5363 -> Patchwork_11190 ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_11190 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11190, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/54751/revisions/1/mbox/ Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_11190: ### IGT changes ### #### Warnings #### * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: PASS -> SKIP +36 * igt@pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: PASS -> SKIP Known issues ------------ Here are the changes found in Patchwork_11190 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@pm_rpm@basic-rte: - fi-byt-n2820: NOTRUN -> FAIL [fdo#108800] - fi-bsw-kefka: PASS -> FAIL [fdo#108800] * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: PASS -> FAIL [fdo#103182] #### Possible fixes #### * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 Participating hosts (47 -> 43) ------------------------------ Additional (3): fi-byt-n2820 fi-apl-guc fi-pnv-d510 Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-whl-u Build changes ------------- * Linux: CI_DRM_5363 -> Patchwork_11190 CI_DRM_5363: f141806c68e4cbd56e3a5a582eb1a6f5b7edfc84 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11190: a24b94693a9ce66399d0f32d40bcc18a5e03c2b5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a24b94693a9c drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11190/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-04 17:37 [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD José Roberto de Souza 2019-01-04 17:59 ` ✓ Fi.CI.BAT: success for " Patchwork @ 2019-01-04 20:44 ` Patchwork 2019-01-07 11:01 ` [PATCH] " Joonas Lahtinen 2019-01-09 20:38 ` Sripada, Radhakrishna 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-01-04 20:44 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD URL : https://patchwork.freedesktop.org/series/54751/ State : success == Summary == CI Bug Log - changes from CI_DRM_5363_full -> Patchwork_11190_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_11190_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-skl: NOTRUN -> TIMEOUT [fdo#108039] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-kbl: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-b-crc-sprite-planes-basic: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-glk: PASS -> FAIL [fdo#103232] +4 * igt@kms_cursor_crc@cursor-256x256-sliding: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +3 * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1 * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-glk: PASS -> FAIL [fdo#108948] * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-glk: PASS -> FAIL [fdo#103166] +2 * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-iclb: NOTRUN -> FAIL [fdo#103166] * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538] * igt@kms_sysfs_edid_timing: - shard-skl: NOTRUN -> FAIL [fdo#100047] * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@pm_backlight@fade: - shard-iclb: PASS -> INCOMPLETE [fdo#107820] * igt@pm_rps@min-max-config-loaded: - shard-apl: PASS -> FAIL [fdo#102250] * igt@pm_rps@waitboost: - shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] #### Possible fixes #### * igt@kms_atomic_transition@1x-modeset-transitions-fencing: - shard-skl: FAIL [fdo#107815] / [fdo#108470] -> PASS * igt@kms_available_modes_crc@available_mode_test_crc: - shard-apl: FAIL [fdo#106641] -> PASS * igt@kms_color@pipe-c-ctm-max: - shard-apl: FAIL [fdo#108147] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS +1 * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_cursor_crc@cursor-256x85-random: - shard-apl: FAIL [fdo#103232] -> PASS +3 * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +16 * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled: - shard-iclb: WARN [fdo#108336] -> PASS +1 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: DMESG-FAIL [fdo#107720] / [fdo#107724] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: FAIL [fdo#103167] -> PASS +2 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: DMESG-FAIL [fdo#107724] -> PASS +7 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +13 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff: - shard-iclb: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-apl: FAIL [fdo#108948] -> PASS +1 * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-iclb: INCOMPLETE [fdo#107713] -> PASS * igt@kms_plane@plane-position-covered-pipe-b-planes: - shard-iclb: FAIL [fdo#103166] -> PASS * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-apl: FAIL [fdo#103166] -> PASS * igt@kms_sequence@get-busy: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +27 * igt@pm_rpm@cursor-dpms: - shard-iclb: DMESG-WARN [fdo#108654] -> PASS * igt@pm_rpm@modeset-stress-extra-wait: - shard-skl: INCOMPLETE [fdo#107807] -> PASS * igt@pm_rpm@system-suspend-modeset: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107807] -> PASS * igt@pm_rps@min-max-config-loaded: - shard-glk: FAIL [fdo#102250] -> PASS #### Warnings #### * igt@i915_suspend@shrink: - shard-skl: INCOMPLETE [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#108784] - shard-kbl: DMESG-WARN [fdo#108784] -> INCOMPLETE [fdo#103665] / [fdo#106886] * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232] * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145] -> FAIL [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-apl: DMESG-FAIL [fdo#103166] / [fdo#103558] / [fdo#105602] -> FAIL [fdo#103166] [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538 [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641 [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885 [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107720]: https://bugs.freedesktop.org/show_bug.cgi?id=107720 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815 [fdo#107820]: https://bugs.freedesktop.org/show_bug.cgi?id=107820 [fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882 [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886 [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956 [fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039 [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147 [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336 [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470 [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654 [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784 [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948 Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_5363 -> Patchwork_11190 CI_DRM_5363: f141806c68e4cbd56e3a5a582eb1a6f5b7edfc84 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11190: a24b94693a9ce66399d0f32d40bcc18a5e03c2b5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11190/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-04 17:37 [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD José Roberto de Souza 2019-01-04 17:59 ` ✓ Fi.CI.BAT: success for " Patchwork 2019-01-04 20:44 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-01-07 11:01 ` Joonas Lahtinen 2019-01-07 12:23 ` Michał Winiarski 2019-01-09 20:38 ` Sripada, Radhakrishna 3 siblings, 1 reply; 12+ messages in thread From: Joonas Lahtinen @ 2019-01-07 11:01 UTC (permalink / raw) To: José Roberto de Souza, intel-gfx; +Cc: Oscar Mateo Quoting José Roberto de Souza (2019-01-04 19:37:00) > According to Workaround database ICL also needs > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > fine-granularity preemptions per-context. I must wonder where is the userspace component that needs this, and why it hasn't been noticed earlier? Or is this one more of the cases when no userspace actually uses the register? Regards, Joonas > > BSpec: 11348 > Cc: Oscar Mateo <oscar.mateo@intel.com> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index 480c53a2ecb5..bbc5a66faa07 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */ > whitelist_reg(w, GEN8_CS_CHICKEN1); > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > @@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > /* WaAllowUMDToModifySamplerMode:icl */ > whitelist_reg(w, GEN10_SAMPLER_MODE); > + > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > + whitelist_reg(w, GEN8_CS_CHICKEN1); > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > @@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > GEN7_DISABLE_SAMPLER_PREFETCH); > } > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > + if (IS_GEN_RANGE(i915, 9, 11)) { > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */ > wa_masked_en(wal, > GEN7_FF_SLICE_CS_CHICKEN1, > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-07 11:01 ` [PATCH] " Joonas Lahtinen @ 2019-01-07 12:23 ` Michał Winiarski 2019-01-07 19:19 ` Matt Roper 0 siblings, 1 reply; 12+ messages in thread From: Michał Winiarski @ 2019-01-07 12:23 UTC (permalink / raw) To: Joonas Lahtinen; +Cc: Oscar Mateo, intel-gfx On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > According to Workaround database ICL also needs > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > fine-granularity preemptions per-context. > > I must wonder where is the userspace component that needs this, and why > it hasn't been noticed earlier? > > Or is this one more of the cases when no userspace actually uses the > register? It's used: https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 -Michał > Regards, Joonas > > > > > BSpec: 11348 > > Cc: Oscar Mateo <oscar.mateo@intel.com> > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > > index 480c53a2ecb5..bbc5a66faa07 100644 > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */ > > whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > > @@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > > > /* WaAllowUMDToModifySamplerMode:icl */ > > whitelist_reg(w, GEN10_SAMPLER_MODE); > > + > > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > > + whitelist_reg(w, GEN8_CS_CHICKEN1); > > } > > > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > > @@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > > GEN7_DISABLE_SAMPLER_PREFETCH); > > } > > > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > > + if (IS_GEN_RANGE(i915, 9, 11)) { > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */ > > wa_masked_en(wal, > > GEN7_FF_SLICE_CS_CHICKEN1, > > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > > -- > > 2.20.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-07 12:23 ` Michał Winiarski @ 2019-01-07 19:19 ` Matt Roper 2019-01-08 15:53 ` Joonas Lahtinen 2019-01-09 17:07 ` Michał Winiarski 0 siblings, 2 replies; 12+ messages in thread From: Matt Roper @ 2019-01-07 19:19 UTC (permalink / raw) To: Michał Winiarski; +Cc: Oscar Mateo, intel-gfx On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > According to Workaround database ICL also needs > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > fine-granularity preemptions per-context. > > > > I must wonder where is the userspace component that needs this, and why > > it hasn't been noticed earlier? > > > > Or is this one more of the cases when no userspace actually uses the > > register? > > It's used: > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > -Michał Wasn't this just an artificial i915-only workaround that was added to prevent breakage of pre-preemption UMD's? Initial gen9 driver releases didn't support preemption, so when preemption support did get added to i915, the kernel had to force object-level off by default at context creation to avoid breaking old userspace that didn't build batch buffers with all the necessary preemption workarounds. This CS_CHICKEN1 register was then exposed to userspace so that newer, preemption-aware userspace could opt back in if it properly supported preemption. For gen11, there shouldn't be any "old" userspace around that doesn't support preemption, so shouldn't the kernel just leave object-level preemption enabled by default (meaning there's no need to expose this register to userspace to allow it to explicitly opt-in)? Matt > > > Regards, Joonas > > > > > > > > BSpec: 11348 > > > Cc: Oscar Mateo <oscar.mateo@intel.com> > > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > > > index 480c53a2ecb5..bbc5a66faa07 100644 > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > > > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > > > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */ > > > whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > > > @@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > > > > > /* WaAllowUMDToModifySamplerMode:icl */ > > > whitelist_reg(w, GEN10_SAMPLER_MODE); > > > + > > > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > > > + whitelist_reg(w, GEN8_CS_CHICKEN1); > > > } > > > > > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > > > @@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > > > GEN7_DISABLE_SAMPLER_PREFETCH); > > > } > > > > > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > > > + if (IS_GEN_RANGE(i915, 9, 11)) { > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */ > > > wa_masked_en(wal, > > > GEN7_FF_SLICE_CS_CHICKEN1, > > > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > > > -- > > > 2.20.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-07 19:19 ` Matt Roper @ 2019-01-08 15:53 ` Joonas Lahtinen 2019-01-08 20:32 ` Kenneth Graunke 2019-01-09 17:07 ` Michał Winiarski 1 sibling, 1 reply; 12+ messages in thread From: Joonas Lahtinen @ 2019-01-08 15:53 UTC (permalink / raw) To: Michał Winiarski, Matt Roper; +Cc: intel-gfx, Kenneth Graunke + Ken/Jason for Mesa Quoting Matt Roper (2019-01-07 21:19:31) > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > > According to Workaround database ICL also needs > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > > fine-granularity preemptions per-context. > > > > > > I must wonder where is the userspace component that needs this, and why > > > it hasn't been noticed earlier? > > > > > > Or is this one more of the cases when no userspace actually uses the > > > register? > > > > It's used: > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > > > -Michał > > Wasn't this just an artificial i915-only workaround that was added to > prevent breakage of pre-preemption UMD's? Initial gen9 driver releases > didn't support preemption, so when preemption support did get added to > i915, the kernel had to force object-level off by default at context > creation to avoid breaking old userspace that didn't build batch buffers > with all the necessary preemption workarounds. This CS_CHICKEN1 > register was then exposed to userspace so that newer, preemption-aware > userspace could opt back in if it properly supported preemption. > > For gen11, there shouldn't be any "old" userspace around that doesn't > support preemption, so shouldn't the kernel just leave object-level > preemption enabled by default (meaning there's no need to expose this > register to userspace to allow it to explicitly opt-in)? Makes sense to me. We should have known by know if somebody expects to control the register, because they would be failing to do so. Mesa could also drop the register load for Gen11+ Regards, Joonas > > Matt > > > > > > Regards, Joonas > > > > > > > > > > > BSpec: 11348 > > > > Cc: Oscar Mateo <oscar.mateo@intel.com> > > > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > > > > index 480c53a2ecb5..bbc5a66faa07 100644 > > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > > > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > > > > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > > > > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > > > > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */ > > > > whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > > > > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > > > > @@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > > > > > > > /* WaAllowUMDToModifySamplerMode:icl */ > > > > whitelist_reg(w, GEN10_SAMPLER_MODE); > > > > + > > > > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > > > > + whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > } > > > > > > > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > > > > @@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > > > > GEN7_DISABLE_SAMPLER_PREFETCH); > > > > } > > > > > > > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > > > > + if (IS_GEN_RANGE(i915, 9, 11)) { > > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */ > > > > wa_masked_en(wal, > > > > GEN7_FF_SLICE_CS_CHICKEN1, > > > > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > > > > -- > > > > 2.20.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-08 15:53 ` Joonas Lahtinen @ 2019-01-08 20:32 ` Kenneth Graunke 2019-01-16 0:29 ` Rafael Antognolli 0 siblings, 1 reply; 12+ messages in thread From: Kenneth Graunke @ 2019-01-08 20:32 UTC (permalink / raw) To: Joonas Lahtinen; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 2390 bytes --] On Tuesday, January 8, 2019 7:53:05 AM PST Joonas Lahtinen wrote: > + Ken/Jason for Mesa > Quoting Matt Roper (2019-01-07 21:19:31) > > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > > > According to Workaround database ICL also needs > > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > > > fine-granularity preemptions per-context. > > > > > > > > I must wonder where is the userspace component that needs this, and why > > > > it hasn't been noticed earlier? > > > > > > > > Or is this one more of the cases when no userspace actually uses the > > > > register? > > > > > > It's used: > > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > > > > > -Michał > > > > Wasn't this just an artificial i915-only workaround that was added to > > prevent breakage of pre-preemption UMD's? Initial gen9 driver releases > > didn't support preemption, so when preemption support did get added to > > i915, the kernel had to force object-level off by default at context > > creation to avoid breaking old userspace that didn't build batch buffers > > with all the necessary preemption workarounds. This CS_CHICKEN1 > > register was then exposed to userspace so that newer, preemption-aware > > userspace could opt back in if it properly supported preemption. > > > > For gen11, there shouldn't be any "old" userspace around that doesn't > > support preemption, so shouldn't the kernel just leave object-level > > preemption enabled by default (meaning there's no need to expose this > > register to userspace to allow it to explicitly opt-in)? > > Makes sense to me. We should have known by know if somebody expects to > control the register, because they would be failing to do so. > > Mesa could also drop the register load for Gen11+ > > Regards, Joonas + Rafael, as he's done all the preemption work in Mesa. That seems reasonable to me. It looks like i965 always enables mid-object preemption (sets CS_CHICKEN1 bit 0) on Gen10+, and never disables it. You can probably safely turn it on by default, and we can stop writing the register altogether. Thanks for the heads up! --Ken [-- Attachment #1.2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 833 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-08 20:32 ` Kenneth Graunke @ 2019-01-16 0:29 ` Rafael Antognolli 0 siblings, 0 replies; 12+ messages in thread From: Rafael Antognolli @ 2019-01-16 0:29 UTC (permalink / raw) To: Kenneth Graunke; +Cc: intel-gfx On Tue, Jan 08, 2019 at 12:32:05PM -0800, Kenneth Graunke wrote: > On Tuesday, January 8, 2019 7:53:05 AM PST Joonas Lahtinen wrote: > > + Ken/Jason for Mesa > > Quoting Matt Roper (2019-01-07 21:19:31) > > > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > > > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > > > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > > > > According to Workaround database ICL also needs > > > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > > > > fine-granularity preemptions per-context. > > > > > > > > > > I must wonder where is the userspace component that needs this, and why > > > > > it hasn't been noticed earlier? > > > > > > > > > > Or is this one more of the cases when no userspace actually uses the > > > > > register? > > > > > > > > It's used: > > > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > > > > > > > -Michał > > > > > > Wasn't this just an artificial i915-only workaround that was added to > > > prevent breakage of pre-preemption UMD's? Initial gen9 driver releases > > > didn't support preemption, so when preemption support did get added to > > > i915, the kernel had to force object-level off by default at context > > > creation to avoid breaking old userspace that didn't build batch buffers > > > with all the necessary preemption workarounds. This CS_CHICKEN1 > > > register was then exposed to userspace so that newer, preemption-aware > > > userspace could opt back in if it properly supported preemption. It's not only that userspace didn't build proper batch buffers with the necessary workarounds, but that most of the workarounds required disabling preemption depending on the type of primitive being drawn. So userspace needed access to CS_CHICKEN1 to be able to enable/disable preemption for those. > > > For gen11, there shouldn't be any "old" userspace around that doesn't > > > support preemption, so shouldn't the kernel just leave object-level > > > preemption enabled by default (meaning there's no need to expose this > > > register to userspace to allow it to explicitly opt-in)? > > > > Makes sense to me. We should have known by know if somebody expects to > > control the register, because they would be failing to do so. > > > > Mesa could also drop the register load for Gen11+ > > > > Regards, Joonas > > + Rafael, as he's done all the preemption work in Mesa. > > That seems reasonable to me. It looks like i965 always enables > mid-object preemption (sets CS_CHICKEN1 bit 0) on Gen10+, and never > disables it. You can probably safely turn it on by default, and we > can stop writing the register altogether. Yeah, I noticed this after re-reading some other thread, right after we got the preemption patches merged. On gen11, we have some workarounds but they don't require us to disable preemption through CS_CHICKEN1, so it should be safe for the kernel to not whitelist or disable it. Thanks, Rafael _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-07 19:19 ` Matt Roper 2019-01-08 15:53 ` Joonas Lahtinen @ 2019-01-09 17:07 ` Michał Winiarski 1 sibling, 0 replies; 12+ messages in thread From: Michał Winiarski @ 2019-01-09 17:07 UTC (permalink / raw) To: Matt Roper; +Cc: Oscar Mateo, intel-gfx On Mon, Jan 07, 2019 at 11:19:31AM -0800, Matt Roper wrote: > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > > According to Workaround database ICL also needs > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > > fine-granularity preemptions per-context. > > > > > > I must wonder where is the userspace component that needs this, and why > > > it hasn't been noticed earlier? > > > > > > Or is this one more of the cases when no userspace actually uses the > > > register? > > > > It's used: > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > > > -Michał > > Wasn't this just an artificial i915-only workaround that was added to > prevent breakage of pre-preemption UMD's? Initial gen9 driver releases > didn't support preemption, so when preemption support did get added to > i915, the kernel had to force object-level off by default at context > creation to avoid breaking old userspace that didn't build batch buffers > with all the necessary preemption workarounds. This CS_CHICKEN1 > register was then exposed to userspace so that newer, preemption-aware > userspace could opt back in if it properly supported preemption. It wasn't just old userspace vs preeemption-aware userspace. Even the preemption-aware userspace needs to downgrade its preemption granularity as a WA, see: https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_draw.c#L876 > For gen11, there shouldn't be any "old" userspace around that doesn't > support preemption, so shouldn't the kernel just leave object-level > preemption enabled by default (meaning there's no need to expose this > register to userspace to allow it to explicitly opt-in)? Agreed, as a bonus we don't allow anyone to explicity opt-out - which is great, as long as everything works reliably. -Michał > > Matt > > > > > > Regards, Joonas > > > > > > > > > > > BSpec: 11348 > > > > Cc: Oscar Mateo <oscar.mateo@intel.com> > > > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > > > > index 480c53a2ecb5..bbc5a66faa07 100644 > > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > > > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > > > > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > > > > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > > > > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] */ > > > > whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > > > > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > > > > @@ -1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > > > > > > > /* WaAllowUMDToModifySamplerMode:icl */ > > > > whitelist_reg(w, GEN10_SAMPLER_MODE); > > > > + > > > > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > > > > + whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > } > > > > > > > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > > > > @@ -1186,8 +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > > > > GEN7_DISABLE_SAMPLER_PREFETCH); > > > > } > > > > > > > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > > > > - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > > > > + if (IS_GEN_RANGE(i915, 9, 11)) { > > > > + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl */ > > > > wa_masked_en(wal, > > > > GEN7_FF_SLICE_CS_CHICKEN1, > > > > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > > > > -- > > > > 2.20.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-04 17:37 [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD José Roberto de Souza ` (2 preceding siblings ...) 2019-01-07 11:01 ` [PATCH] " Joonas Lahtinen @ 2019-01-09 20:38 ` Sripada, Radhakrishna 2019-01-15 7:25 ` Joonas Lahtinen 3 siblings, 1 reply; 12+ messages in thread From: Sripada, Radhakrishna @ 2019-01-09 20:38 UTC (permalink / raw) To: Souza, Jose, intel-gfx; +Cc: Oscar Mateo Looks good to me. > -----Original Message----- > From: Souza, Jose > Sent: Friday, January 4, 2019 9:37 AM > To: intel-gfx@lists.freedesktop.org > Cc: Oscar Mateo <oscar.mateo@intel.com>; Sripada, Radhakrishna > <radhakrishna.sripada@intel.com>; Souza, Jose <jose.souza@intel.com> > Subject: [PATCH] drm/i915/icl: Apply > WaEnablePreemptionGranularityControlByUMD > > According to Workaround database ICL also needs > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > fine-granularity preemptions per-context. > > BSpec: 11348 > Cc: Oscar Mateo <oscar.mateo@intel.com> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c > b/drivers/gpu/drm/i915/intel_workarounds.c > index 480c53a2ecb5..bbc5a66faa07 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list > *w) > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > - /* > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > + /* > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] > +*/ > whitelist_reg(w, GEN8_CS_CHICKEN1); > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ @@ - > 1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > /* WaAllowUMDToModifySamplerMode:icl */ > whitelist_reg(w, GEN10_SAMPLER_MODE); > + > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > + whitelist_reg(w, GEN8_CS_CHICKEN1); > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) @@ -1186,8 > +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > GEN7_DISABLE_SAMPLER_PREFETCH); > } > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > - /* > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > + if (IS_GEN_RANGE(i915, 9, 11)) { > + /* > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl > +*/ > wa_masked_en(wal, > GEN7_FF_SLICE_CS_CHICKEN1, > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD 2019-01-09 20:38 ` Sripada, Radhakrishna @ 2019-01-15 7:25 ` Joonas Lahtinen 0 siblings, 0 replies; 12+ messages in thread From: Joonas Lahtinen @ 2019-01-15 7:25 UTC (permalink / raw) To: Souza, Jose, Sripada, Radhakrishna, intel-gfx; +Cc: Oscar Mateo Quoting Sripada, Radhakrishna (2019-01-09 22:38:36) > Looks good to me. There is already conclusion in the other thread that this should NOT be merged. Regards, Joonas > > > -----Original Message----- > > From: Souza, Jose > > Sent: Friday, January 4, 2019 9:37 AM > > To: intel-gfx@lists.freedesktop.org > > Cc: Oscar Mateo <oscar.mateo@intel.com>; Sripada, Radhakrishna > > <radhakrishna.sripada@intel.com>; Souza, Jose <jose.souza@intel.com> > > Subject: [PATCH] drm/i915/icl: Apply > > WaEnablePreemptionGranularityControlByUMD > > > > According to Workaround database ICL also needs > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > fine-granularity preemptions per-context. > > > > BSpec: 11348 > > Cc: Oscar Mateo <oscar.mateo@intel.com> > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > --- > > drivers/gpu/drm/i915/intel_workarounds.c | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c > > b/drivers/gpu/drm/i915/intel_workarounds.c > > index 480c53a2ecb5..bbc5a66faa07 100644 > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > @@ -1014,7 +1014,7 @@ static void gen9_whitelist_build(struct i915_wa_list > > *w) > > /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ > > whitelist_reg(w, GEN9_CTX_PREEMPT_REG); > > > > - /* > > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ > > + /* > > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl,icl] > > +*/ > > whitelist_reg(w, GEN8_CS_CHICKEN1); > > > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ @@ - > > 1068,6 +1068,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > > > /* WaAllowUMDToModifySamplerMode:icl */ > > whitelist_reg(w, GEN10_SAMPLER_MODE); > > + > > + /* WaEnablePreemptionGranularityControlByUMD:icl */ > > + whitelist_reg(w, GEN8_CS_CHICKEN1); > > } > > > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) @@ -1186,8 > > +1189,8 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine) > > GEN7_DISABLE_SAMPLER_PREFETCH); > > } > > > > - if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) { > > - /* > > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ > > + if (IS_GEN_RANGE(i915, 9, 11)) { > > + /* > > WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl,icl > > +*/ > > wa_masked_en(wal, > > GEN7_FF_SLICE_CS_CHICKEN1, > > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > > -- > > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-01-16 0:29 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-01-04 17:37 [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD José Roberto de Souza 2019-01-04 17:59 ` ✓ Fi.CI.BAT: success for " Patchwork 2019-01-04 20:44 ` ✓ Fi.CI.IGT: " Patchwork 2019-01-07 11:01 ` [PATCH] " Joonas Lahtinen 2019-01-07 12:23 ` Michał Winiarski 2019-01-07 19:19 ` Matt Roper 2019-01-08 15:53 ` Joonas Lahtinen 2019-01-08 20:32 ` Kenneth Graunke 2019-01-16 0:29 ` Rafael Antognolli 2019-01-09 17:07 ` Michał Winiarski 2019-01-09 20:38 ` Sripada, Radhakrishna 2019-01-15 7:25 ` Joonas Lahtinen
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