[v6 0/6] Add support for Gen 11 pipe color features

[v6 0/6] Add support for Gen 11 pipe color features

[Uma Shankar]

This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.

CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in
pipe. Also there is a corner case where Lut precision is increased
to 3.16, hence its not possible to accurately represent 1.0 which
will require 17 bits. Support for extending the ABI is already in
discussion in below series:
https://patchwork.freedesktop.org/patch/249771/

ToDo: Support for Multi Segmented Gamma will be added later.

v2: Addressed Maarten's review comments and re-ordered the patch
series.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Matt's, Ville and Jani Nikula's review comments.

v6: Addressed Matt and Ville's review comments. Extended GLK 
degamma function and merged ICL degamma support to that. Handled
pipe output csc separately along with regular pipe csc. Dropped
gamma_mode removal patch as Ville is using that to refactor the
gamma handling. This series may need a rebase on top of Ville's
below series:
https://patchwork.freedesktop.org/series/55081/. 

Uma Shankar (6):
  drm/i915: Sanitize crtc gamma and csc mode
  drm/i915/glk: Fix degamma lut programming
  drm/i915/icl: Add icl pipe degamma and gamma support
  drm/i915/icl: Enable ICL Pipe CSC block
  drm/i915/icl: Enable pipe output csc
  drm/i915/icl: Add degamma and gamma lut size to gen11 caps

 drivers/gpu/drm/i915/i915_pci.c      |   5 +-
 drivers/gpu/drm/i915/i915_reg.h      |  62 +++++++++++++---
 drivers/gpu/drm/i915/intel_color.c   | 133 ++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c |  21 ++++++
 drivers/gpu/drm/i915/intel_drv.h     |   3 +
 5 files changed, 188 insertions(+), 36 deletions(-)

-- 
1.9.1

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[v6 1/6] drm/i915: Sanitize crtc gamma and csc mode

[Uma Shankar]

Sanitize crtc gamma and csc  mode and update the mode in driver
in case BIOS has setup a different mode or gamma luts, csc  with
any other unexpected values than desired. There is restriction on
HSW platform not to read/write color LUT's if ips is enabled.
Handled the same accordingly.

We don't read out the LUT's and CTM that the BIOS setup, so at the
moment they stick around for a while until they get unexpectedly
clobbered by a subsequent modeset or fastset. The change here will
basically force them to be reset to standard/linear values at startup.

Maybe in the future we'll try to actually read out and preserve the
contents of the actual LUT's and CTM that the BIOS had setup, but we
don't do that yet today, so the change here at least makes the behavior
a little bit more consistent than what it has been.

v2: Addressed Matt's review comments.

Credits-to: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af164d7..56fa469 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15434,6 +15434,27 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 		}
 	}
 
+	/*
+	 * Sanitize gamma mode incase BIOS leaves it in SPLIT GAMMA MODE
+	 * or gamma luts, csc  with any other unexpected values than desired.
+	 * We don't read out the LUT's and CTM that the BIOS setup, so at the
+	 * moment they stick around for a while until they get unexpectedly
+	 * clobbered by a subsequent modeset or fastset.
+	 * The change here will basically force them to be reset to
+	 * standard/linear values at startup.
+	 * Workaround HSW : Do not read or write the pipe palette/gamma data
+	 * while GAMMA_MODE is configured for split gamma and IPS_CTL has IPS
+	 * enabled.
+	 */
+	if (IS_HASWELL(dev_priv)) {
+		hsw_disable_ips(crtc_state);
+
+		intel_color_set_csc(crtc_state);
+		intel_color_load_luts(crtc_state);
+
+		hsw_enable_ips(crtc_state);
+	}
+
 	/* Adjust the state of the output pipe according to whether we
 	 * have active connectors/encoders. */
 	if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
-- 
1.9.1

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[v6 2/6] drm/i915/glk: Fix degamma lut programming

[Uma Shankar]

Fixed the glk degamma lut programming which currently
was hard coding a linear lut all the time, making degamma
block of glk basically a pass through.

Currently degamma lut for glk is assigned as 0 in platform
configuration. Updated the same to 33 as per the hardware
capability. IGT tests for degamma were getting skipped due to
this, spotted by Swati.

ToDo: The current gamma/degamm lut ABI has just 16bit for each
color component. This is not enough for GLK+, since input
precision is increased to 3.16 which will need 19bit entries.

Credits-to: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c    |  2 +-
 drivers/gpu/drm/i915/intel_color.c | 36 ++++++++++++++++++++++++++++--------
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dd4aff2..24248d0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -69,7 +69,7 @@
 #define CHV_COLORS \
 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 #define GLK_COLORS \
-	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 
 /* Keep in gen based order, and chronological order within a gen */
 
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 37fd9dd..3712bd0 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -491,7 +491,7 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
-	const uint32_t lut_size = 33;
+	const uint32_t lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	uint32_t i;
 
 	/*
@@ -502,14 +502,34 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
 	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 
-	/*
-	 *  FIXME: The pipe degamma table in geminilake doesn't support
-	 *  different values per channel, so this just loads a linear table.
-	 */
-	for (i = 0; i < lut_size; i++) {
-		uint32_t v = (i * (1 << 16)) / (lut_size - 1);
 
-		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
+	if (crtc_state->base.degamma_lut) {
+		struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
+
+		for (i = 0; i < lut_size; i++) {
+			/*
+			 * First 33 entries represent range from 0 to 1.0
+			 * 34th and 35th entry will represent extended range
+			 * inputs 3.0 and 7.0 respectively, currently clamped
+			 * at 1.0. Since the precision is 16bit, the user
+			 * value can be directly filled to register.
+			 * The pipe degamma table in GLK+ onwards doesn't
+			 * support different values per channel, so this just
+			 * programs green value which will be equal to Red and
+			 * Blue into the lut registers.
+			 * ToDo: Extend to max 7.0. Enable 32 bit input value
+			 * as compared to just 16 to achieve this.
+			 */
+			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
+			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
+		}
+	} else {
+		/* load a linear table. */
+		for (i = 0; i < lut_size; i++) {
+			uint32_t v = (i * (1 << 16)) / (lut_size - 1);
+
+			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
+		}
 	}
 
 	/* Clamp values > 1.0. */
-- 
1.9.1

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[v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

[Uma Shankar]

Add support for icl pipe degamma and gamma.

v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Fixed Matt's review comments.

v5: Corrected macro alignment as per Jani Nikula's comments.
Addressed Ville and Matt's  review comments.

v6: Merged ICL degamma handling with GLK and dropped ICL
degamma function as per Ville and Matt's comments.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
 drivers/gpu/drm/i915/intel_color.c | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fad5a9e..a84200f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7088,11 +7088,13 @@ enum {
 #define _GAMMA_MODE_A		0x4a480
 #define _GAMMA_MODE_B		0x4ac80
 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
-#define GAMMA_MODE_MODE_MASK	(3 << 0)
-#define GAMMA_MODE_MODE_8BIT	(0 << 0)
-#define GAMMA_MODE_MODE_10BIT	(1 << 0)
-#define GAMMA_MODE_MODE_12BIT	(2 << 0)
-#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
+#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
+#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
+#define  GAMMA_MODE_MODE_MASK	(3 << 0)
+#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
+#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
+#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
+#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 3712bd0..494891c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
 	POSTING_READ(GAMMA_MODE(pipe));
 }
 
+static void icl_load_luts(struct intel_crtc_state *crtc_state)
+{
+	struct drm_crtc *crtc = crtc_state->base.crtc;
+	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+	if (crtc_state_is_legacy_gamma(crtc_state)) {
+		haswell_load_luts(crtc_state);
+		return;
+	}
+
+	glk_load_degamma_lut(crtc_state);
+	bdw_load_gamma_lut(crtc_state, 0);
+
+	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
+		   PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE);
+}
+
 /* Loads the palette/gamma unit for the CRTC on CherryView. */
 static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 {
@@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
 	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = glk_load_luts;
+	} else if (IS_ICELAKE(dev_priv)) {
+		dev_priv->display.load_luts = icl_load_luts;
 	} else {
 		dev_priv->display.load_luts = i9xx_load_luts;
 	}
-- 
1.9.1

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[v6 4/6] drm/i915/icl: Enable ICL Pipe CSC block

[Uma Shankar]

Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.

ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.

v2: Addressed Maarten's review comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Ville's review comments.

v6: Separated pipe output csc programming from regular csc.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 9 ++++++---
 drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a84200f..3c3a902 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9861,10 +9861,13 @@ enum skl_power_gate {
 #define _PIPE_A_CSC_COEFF_BU	0x4901c
 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
 #define _PIPE_A_CSC_COEFF_BV	0x49024
+
 #define _PIPE_A_CSC_MODE	0x49028
-#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
-#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
-#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
+#define  ICL_CSC_ENABLE			(1 << 31)
+#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
+#define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
+#define  CSC_MODE_YUV_TO_RGB		(1 << 0)
+
 #define _PIPE_A_CSC_PREOFF_HI	0x49030
 #define _PIPE_A_CSC_PREOFF_ME	0x49034
 #define _PIPE_A_CSC_PREOFF_LO	0x49038
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 494891c..9b8d2de 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -134,6 +134,7 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
 	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
 	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
+
 	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 }
 
@@ -242,7 +243,10 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		if (INTEL_GEN(dev_priv) >= 11)
+			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
+		else
+			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 	} else {
 		uint32_t mode = CSC_MODE_YUV_TO_RGB;
 
@@ -692,6 +696,7 @@ void intel_color_init(struct intel_crtc *crtc)
 		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = glk_load_luts;
 	} else if (IS_ICELAKE(dev_priv)) {
+		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = icl_load_luts;
 	} else {
 		dev_priv->display.load_luts = i9xx_load_luts;
-- 
1.9.1

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[v6 5/6] drm/i915/icl: Enable pipe output csc

[Uma Shankar]

GEN11+ onwards an output csc hardware block has been added.
This is after the pipe gamma block and is in addition to the
legacy pipe CSC block. Primary use case for this block is to
convert RGB to YUV in case sink supports YUV.
This patch adds supports for the same.

v2: This is added after splitting the existing ICL pipe CSC
handling. As per Matt's suggestion, made this to co-exist
with existing pipe CSC, wherein both can be enabled if a
certain usecase arises.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 41 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h   |  3 ++
 3 files changed, 99 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c3a902..edd6b4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9864,6 +9864,7 @@ enum skl_power_gate {
 
 #define _PIPE_A_CSC_MODE	0x49028
 #define  ICL_CSC_ENABLE			(1 << 31)
+#define  ICL_OUTPUT_CSC_ENABLE		(1 << 30)
 #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
 #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
 #define  CSC_MODE_YUV_TO_RGB		(1 << 0)
@@ -9903,6 +9904,46 @@ enum skl_power_gate {
 #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
 #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
+/* Pipe Output CSC */
+#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
+#define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
+#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
+#define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
+#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
+#define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
+#define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
+#define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
+#define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
+
+#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
+#define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
+#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
+#define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
+#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
+#define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
+#define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
+#define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
+#define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
+
+#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RY_GY, _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
+#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BY, _PIPE_B_OUTPUT_CSC_COEFF_BY)
+#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
+#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BU, _PIPE_B_OUTPUT_CSC_COEFF_BU)
+#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
+#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BV, _PIPE_B_OUTPUT_CSC_COEFF_BV)
+#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_HI, _PIPE_B_OUTPUT_CSC_PREOFF_HI)
+#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_ME, _PIPE_B_OUTPUT_CSC_PREOFF_ME)
+#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_LO, _PIPE_B_OUTPUT_CSC_PREOFF_LO)
+#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_HI, _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
+#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_ME, _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
+#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_LO, _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
+
 /* pipe degamma/gamma LUTs on IVB+ */
 #define _PAL_PREC_INDEX_A	0x4A400
 #define _PAL_PREC_INDEX_B	0x4AC00
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 9b8d2de..c95adb9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -113,29 +113,58 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 	return result;
 }
 
-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
+static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc_state
+					     *crtc_state)
 {
-	int pipe = crtc->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int pipe = crtc->pipe;
 
-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+	if (INTEL_GEN(dev_priv) < 11) {
+		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 
-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
+		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
 
-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
+		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
 
-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
+		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
 
-	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
-	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
-	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
 
-	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		crtc_state->csc_mode = 0;
+	} else {
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
+			   CSC_RGB_TO_YUV_RU_GU);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
+			   CSC_RGB_TO_YUV_RY_GY);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
+			   CSC_RGB_TO_YUV_RV_GV);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
+			   POSTOFF_RGB_TO_YUV_HI);
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
+			   POSTOFF_RGB_TO_YUV_ME);
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
+			   POSTOFF_RGB_TO_YUV_LO);
+
+		crtc_state->csc_mode = ICL_OUTPUT_CSC_ENABLE;
+	}
 }
 
 static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
@@ -153,10 +182,14 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
 	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
 		limited_color_range = crtc_state->limited_color_range;
 
+	crtc_state->csc_mode = 0;
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
-		ilk_load_ycbcr_conversion_matrix(crtc);
-		return;
+		ilk_load_ycbcr_conversion_matrix(crtc_state);
+		if (INTEL_GEN(dev_priv) < 11) {
+			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
+			return;
+		}
 	} else if (crtc_state->base.ctm) {
 		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 		const u64 *input;
@@ -243,10 +276,12 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		if (INTEL_GEN(dev_priv) >= 11)
-			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
-		else
+		if (INTEL_GEN(dev_priv) >= 11) {
+			crtc_state->csc_mode |= ICL_CSC_ENABLE;
+			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
+		} else {
 			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		}
 	} else {
 		uint32_t mode = CSC_MODE_YUV_TO_RGB;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e5a436c..320a413 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -930,6 +930,9 @@ struct intel_crtc_state {
 	/* Gamma mode programmed on the pipe */
 	uint32_t gamma_mode;
 
+	/* CSC mode programmed on the pipe */
+	uint32_t csc_mode;
+
 	/* bitmask of visible planes (enum plane_id) */
 	u8 active_planes;
 	u8 nv12_planes;
-- 
1.9.1

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[v6 6/6] drm/i915/icl: Add degamma and gamma lut size to gen11 caps

[Uma Shankar]

Add the degamma and gamma lut sizes to gen11 capability
structure.

Note: Currently this doesn't account for the extended range gamma
entries and this will be addressed with new segmented gamma ABI
in a future patch.

v2: Reorder the patch as per Maarten's suggestion.

v3: Rebase

v4: Updated commit message with a note as per Matt's suggestion.

v5: No Change.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 24248d0..92eb38d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -639,7 +639,8 @@
 	}, \
 	GEN(11), \
 	.ddb_size = 2048, \
-	.has_logical_ring_elsq = 1
+	.has_logical_ring_elsq = 1, \
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 
 static const struct intel_device_info intel_icelake_11_info = {
 	GEN11_FEATURES,
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for Add support for Gen 11 pipe color features (rev6)

[Patchwork]

== Series Details ==

Series: Add support for Gen 11 pipe color features (rev6)
URL   : https://patchwork.freedesktop.org/series/51408/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d8b97dc07080 drm/i915: Sanitize crtc gamma and csc mode
30347710fc21 drm/i915/glk: Fix degamma lut programming
80c225a0100d drm/i915/icl: Add icl pipe degamma and gamma support
7af2f0ab6a8d drm/i915/icl: Enable ICL Pipe CSC block
ebeb64818cc5 drm/i915/icl: Enable pipe output csc
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:9934:
+#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RY_GY, _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)

-:63: WARNING:LONG_LINE: line over 100 characters
#63: FILE: drivers/gpu/drm/i915/i915_reg.h:9935:
+#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BY, _PIPE_B_OUTPUT_CSC_COEFF_BY)

-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/i915_reg.h:9936:
+#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)

-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/i915/i915_reg.h:9937:
+#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BU, _PIPE_B_OUTPUT_CSC_COEFF_BU)

-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:9938:
+#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)

-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:9939:
+#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BV, _PIPE_B_OUTPUT_CSC_COEFF_BV)

-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/i915/i915_reg.h:9940:
+#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_HI, _PIPE_B_OUTPUT_CSC_PREOFF_HI)

-:69: WARNING:LONG_LINE: line over 100 characters
#69: FILE: drivers/gpu/drm/i915/i915_reg.h:9941:
+#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_ME, _PIPE_B_OUTPUT_CSC_PREOFF_ME)

-:70: WARNING:LONG_LINE: line over 100 characters
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:9942:
+#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_LO, _PIPE_B_OUTPUT_CSC_PREOFF_LO)

-:71: WARNING:LONG_LINE: line over 100 characters
#71: FILE: drivers/gpu/drm/i915/i915_reg.h:9943:
+#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_HI, _PIPE_B_OUTPUT_CSC_POSTOFF_HI)

-:72: WARNING:LONG_LINE: line over 100 characters
#72: FILE: drivers/gpu/drm/i915/i915_reg.h:9944:
+#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_ME, _PIPE_B_OUTPUT_CSC_POSTOFF_ME)

-:73: WARNING:LONG_LINE: line over 100 characters
#73: FILE: drivers/gpu/drm/i915/i915_reg.h:9945:
+#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_LO, _PIPE_B_OUTPUT_CSC_POSTOFF_LO)

total: 0 errors, 12 warnings, 0 checks, 166 lines checked
b880acec10d4 drm/i915/icl: Add degamma and gamma lut size to gen11 caps

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✓ Fi.CI.BAT: success for Add support for Gen 11 pipe color features (rev6)

[Patchwork]

== Series Details ==

Series: Add support for Gen 11 pipe color features (rev6)
URL   : https://patchwork.freedesktop.org/series/51408/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5438 -> Patchwork_11965
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51408/revisions/6/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11965 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_basic@gtt-bsd2:
    - fi-skl-6770hq:      PASS -> DMESG-WARN [fdo#105541]

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278


Participating hosts (46 -> 43)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (4): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-kbl-7500u 


Build changes
-------------

    * Linux: CI_DRM_5438 -> Patchwork_11965

  CI_DRM_5438: 30c69ebc8e033d471bf006cb0ef49227edb6c4f7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4776: a76fa4d02cc806e30ed72ba1b8233c694ab1727b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11965: b880acec10d42bc78e46aeeab3a7068c0d284e59 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b880acec10d4 drm/i915/icl: Add degamma and gamma lut size to gen11 caps
ebeb64818cc5 drm/i915/icl: Enable pipe output csc
7af2f0ab6a8d drm/i915/icl: Enable ICL Pipe CSC block
80c225a0100d drm/i915/icl: Add icl pipe degamma and gamma support
30347710fc21 drm/i915/glk: Fix degamma lut programming
d8b97dc07080 drm/i915: Sanitize crtc gamma and csc mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11965/
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✓ Fi.CI.IGT: success for Add support for Gen 11 pipe color features (rev6)

[Patchwork]

== Series Details ==

Series: Add support for Gen 11 pipe color features (rev6)
URL   : https://patchwork.freedesktop.org/series/51408/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5438_full -> Patchwork_11965_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11965_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11965_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11965_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_color@pipe-b-ctm-green-to-red:
    - shard-glk:          {SKIP} [fdo#109271] -> FAIL +25

  * igt@kms_color@pipe-b-gamma:
    - shard-iclb:         {SKIP} [fdo#109286] -> FAIL +26

  
Known issues
------------

  Here are the changes found in Patchwork_11965_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#108901]

  * igt@gem_exec_schedule@pi-ringfull-render:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]

  * igt@i915_selftest@live_contexts:
    - shard-iclb:         NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@i915_selftest@live_workarounds:
    - shard-iclb:         NOTRUN -> DMESG-FAIL [fdo#108954]

  * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#109225]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_chv_cursor_fail@pipe-c-256x256-top-edge:
    - shard-skl:          NOTRUN -> FAIL [fdo#104671] +1

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +5

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled:
    - shard-skl:          PASS -> FAIL [fdo#103184]

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
    - shard-skl:          NOTRUN -> FAIL [fdo#108472]

  * igt@kms_fbcon_fbt@psr:
    - shard-skl:          NOTRUN -> FAIL [fdo#107882]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#107724] +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +3
    - shard-apl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-glk:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105682] +1

  * igt@kms_frontbuffer_tracking@psr-1p-rte:
    - shard-skl:          NOTRUN -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#103167] / [fdo#107724]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - shard-skl:          NOTRUN -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885] +1

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713]

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-skl:          NOTRUN -> FAIL [fdo#103166]

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-iclb:         PASS -> FAIL [fdo#103166]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-apl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-glk:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
    - shard-skl:          NOTRUN -> FAIL [fdo#103166] / [fdo#107815]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          PASS -> DMESG-WARN [fdo#105763] / [fdo#106538]

  * igt@kms_setmode@basic:
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@perf_pmu@event-wait-rcs0:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +7

  * igt@pm_backlight@fade_with_suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#107847]

  * igt@pm_rpm@gem-execbuf-stress:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#108840]

  * igt@pm_rpm@reg-read-ioctl:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#108654]

  * igt@vgem_slow@nohang:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  
#### Possible fixes ####

  * igt@kms_atomic_transition@1x-modeset-transitions:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +3

  * igt@kms_atomic_transition@plane-all-transition-nonblocking:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#109225] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-snb:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_busy@extended-pageflip-hang-newfb-render-a:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-a-legacy-gamma-reset:
    - shard-iclb:         {SKIP} [fdo#109286] -> PASS +1

  * igt@kms_color@pipe-c-gamma:
    - shard-glk:          {SKIP} [fdo#109271] -> PASS +8

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-iclb:         FAIL [fdo#103232] -> PASS +17

  * igt@kms_cursor_crc@cursor-64x21-onscreen:
    - shard-glk:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> PASS +3

  * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled:
    - shard-iclb:         WARN [fdo#108336] -> PASS +1

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +4

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
    - shard-glk:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-apl:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-iclb:         FAIL [fdo#103166] -> PASS

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +6

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          DMESG-FAIL [fdo#108950] -> PASS

  * igt@kms_setmode@basic:
    - shard-hsw:          FAIL [fdo#99912] -> PASS

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-apl:          INCOMPLETE [fdo#103927] / [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#109244]

  * igt@kms_color@pipe-a-degamma:
    - shard-glk:          {SKIP} [fdo#109271] -> FAIL [fdo#108145]

  * igt@kms_cursor_crc@cursor-128x42-random:
    - shard-iclb:         FAIL [fdo#103232] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-iclb:         FAIL [fdo#103166] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@pm_rpm@gem-execbuf-stress-pc8:
    - shard-iclb:         {SKIP} [fdo#109293] -> INCOMPLETE [fdo#107713] / [fdo#108840]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
  [fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
  [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#108756]: https://bugs.freedesktop.org/show_bug.cgi?id=108756
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108901]: https://bugs.freedesktop.org/show_bug.cgi?id=108901
  [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
  [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
  [fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109286]: https://bugs.freedesktop.org/show_bug.cgi?id=109286
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5438 -> Patchwork_11965

  CI_DRM_5438: 30c69ebc8e033d471bf006cb0ef49227edb6c4f7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4776: a76fa4d02cc806e30ed72ba1b8233c694ab1727b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11965: b880acec10d42bc78e46aeeab3a7068c0d284e59 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11965/
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Re: [v6 0/6] Add support for Gen 11 pipe color features

[Shankar, Uma]

>-----Original Message-----
>From: Shankar, Uma
>Sent: Wednesday, January 16, 2019 9:52 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lankhorst, Maarten <maarten.lankhorst@intel.com>; Syrjala, Ville
><ville.syrjala@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>;
>Roper, Matthew D <matthew.d.roper@intel.com>; Shankar, Uma
><uma.shankar@intel.com>
>Subject: [v6 0/6] Add support for Gen 11 pipe color features
>
>This patch series adds support for Gen11 pipe degamma, CSC and gamma
>hardware blocks.

Ping !!!

>CRC checks are not working for 10bit gamma but works for 8bit pallete modes
>which seems to be due to some rounding errors in pipe. Also there is a corner
>case where Lut precision is increased to 3.16, hence its not possible to accurately
>represent 1.0 which will require 17 bits. Support for extending the ABI is already in
>discussion in below series:
>https://patchwork.freedesktop.org/patch/249771/
>
>ToDo: Support for Multi Segmented Gamma will be added later.
>
>v2: Addressed Maarten's review comments and re-ordered the patch series.
>
>v3: Addressed Matt's review comments. Removed rmw patterns as suggested by
>Matt.
>
>v4: Addressed Matt's review comments.
>
>v5: Addressed Matt's, Ville and Jani Nikula's review comments.
>
>v6: Addressed Matt and Ville's review comments. Extended GLK degamma
>function and merged ICL degamma support to that. Handled pipe output csc
>separately along with regular pipe csc. Dropped gamma_mode removal patch as
>Ville is using that to refactor the gamma handling. This series may need a rebase
>on top of Ville's below series:
>https://patchwork.freedesktop.org/series/55081/.
>
>Uma Shankar (6):
>  drm/i915: Sanitize crtc gamma and csc mode
>  drm/i915/glk: Fix degamma lut programming
>  drm/i915/icl: Add icl pipe degamma and gamma support
>  drm/i915/icl: Enable ICL Pipe CSC block
>  drm/i915/icl: Enable pipe output csc
>  drm/i915/icl: Add degamma and gamma lut size to gen11 caps
>
> drivers/gpu/drm/i915/i915_pci.c      |   5 +-
> drivers/gpu/drm/i915/i915_reg.h      |  62 +++++++++++++---
> drivers/gpu/drm/i915/intel_color.c   | 133 ++++++++++++++++++++++++++++----
>---
> drivers/gpu/drm/i915/intel_display.c |  21 ++++++
> drivers/gpu/drm/i915/intel_drv.h     |   3 +
> 5 files changed, 188 insertions(+), 36 deletions(-)
>
>--
>1.9.1

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Re: [v6 2/6] drm/i915/glk: Fix degamma lut programming

[Matt Roper]

On Wed, Jan 16, 2019 at 09:51:33PM +0530, Uma Shankar wrote:
> Fixed the glk degamma lut programming which currently
> was hard coding a linear lut all the time, making degamma
> block of glk basically a pass through.
> 
> Currently degamma lut for glk is assigned as 0 in platform
> configuration. Updated the same to 33 as per the hardware
> capability. IGT tests for degamma were getting skipped due to
> this, spotted by Swati.
> 
> ToDo: The current gamma/degamm lut ABI has just 16bit for each
> color component. This is not enough for GLK+, since input
> precision is increased to 3.16 which will need 19bit entries.
> 
> Credits-to: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c    |  2 +-
>  drivers/gpu/drm/i915/intel_color.c | 36 ++++++++++++++++++++++++++++--------
>  2 files changed, 29 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd4aff2..24248d0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -69,7 +69,7 @@
>  #define CHV_COLORS \
>  	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
>  #define GLK_COLORS \
> -	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
> +	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>  
>  /* Keep in gen based order, and chronological order within a gen */
>  
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9dd..3712bd0 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -491,7 +491,7 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> -	const uint32_t lut_size = 33;
> +	const uint32_t lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	uint32_t i;
>  
>  	/*
> @@ -502,14 +502,34 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
>  	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
>  	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
>  
> -	/*
> -	 *  FIXME: The pipe degamma table in geminilake doesn't support
> -	 *  different values per channel, so this just loads a linear table.
> -	 */
> -	for (i = 0; i < lut_size; i++) {
> -		uint32_t v = (i * (1 << 16)) / (lut_size - 1);
>  
> -		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> +	if (crtc_state->base.degamma_lut) {
> +		struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> +
> +		for (i = 0; i < lut_size; i++) {
> +			/*
> +			 * First 33 entries represent range from 0 to 1.0
> +			 * 34th and 35th entry will represent extended range
> +			 * inputs 3.0 and 7.0 respectively, currently clamped
> +			 * at 1.0. Since the precision is 16bit, the user
> +			 * value can be directly filled to register.
> +			 * The pipe degamma table in GLK+ onwards doesn't
> +			 * support different values per channel, so this just
> +			 * programs green value which will be equal to Red and
> +			 * Blue into the lut registers.
> +			 * ToDo: Extend to max 7.0. Enable 32 bit input value
> +			 * as compared to just 16 to achieve this.
> +			 */
> +			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
> +			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);

I don't think the double-write here was intentional (and would probably
cause more problems than usual due to the index auto increment).

Other than that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +		}
> +	} else {
> +		/* load a linear table. */
> +		for (i = 0; i < lut_size; i++) {
> +			uint32_t v = (i * (1 << 16)) / (lut_size - 1);
> +
> +			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> +		}
>  	}
>  
>  	/* Clamp values > 1.0. */
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

[Matt Roper]

On Wed, Jan 16, 2019 at 09:51:34PM +0530, Uma Shankar wrote:
> Add support for icl pipe degamma and gamma.
> 
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
> 
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
> 
> v4: Fixed Matt's review comments.
> 
> v5: Corrected macro alignment as per Jani Nikula's comments.
> Addressed Ville and Matt's  review comments.
> 
> v6: Merged ICL degamma handling with GLK and dropped ICL
> degamma function as per Ville and Matt's comments.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

The general changes and direction here look good, but this will need a
rebase after Ville's series lands, so I'll wait on that to give the
final r-b.


Matt

> ---
>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>  drivers/gpu/drm/i915/intel_color.c | 21 +++++++++++++++++++++
>  2 files changed, 28 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fad5a9e..a84200f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7088,11 +7088,13 @@ enum {
>  #define _GAMMA_MODE_A		0x4a480
>  #define _GAMMA_MODE_B		0x4ac80
>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
>  /* DMC/CSR */
>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 3712bd0..494891c 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
>  	POSTING_READ(GAMMA_MODE(pipe));
>  }
>  
> +static void icl_load_luts(struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_crtc *crtc = crtc_state->base.crtc;
> +	struct drm_device *dev = crtc_state->base.crtc->dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
> +		haswell_load_luts(crtc_state);
> +		return;
> +	}
> +
> +	glk_load_degamma_lut(crtc_state);
> +	bdw_load_gamma_lut(crtc_state, 0);
> +
> +	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
> +		   PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE);
> +}
> +
>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
>  static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>  {
> @@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = glk_load_luts;
> +	} else if (IS_ICELAKE(dev_priv)) {
> +		dev_priv->display.load_luts = icl_load_luts;
>  	} else {
>  		dev_priv->display.load_luts = i9xx_load_luts;
>  	}
> -- 
> 1.9.1
> 

-- 
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Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [v6 4/6] drm/i915/icl: Enable ICL Pipe CSC block

[Matt Roper]

On Wed, Jan 16, 2019 at 09:51:35PM +0530, Uma Shankar wrote:
> Enable ICL pipe csc hardware. CSC block is enabled
> in CSC_MODE register instead of PLANE_COLOR_CTL.
> 
> ToDO: Extend the ABI to accept 32 bit coefficient values
> instead of 16bit for future platforms.
> 
> v2: Addressed Maarten's review comments.
> 
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
> 
> v4: Addressed Matt's review comments.
> 
> v5: Addressed Ville's review comments.
> 
> v6: Separated pipe output csc programming from regular csc.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    | 9 ++++++---
>  drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a84200f..3c3a902 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9861,10 +9861,13 @@ enum skl_power_gate {
>  #define _PIPE_A_CSC_COEFF_BU	0x4901c
>  #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
>  #define _PIPE_A_CSC_COEFF_BV	0x49024
> +
>  #define _PIPE_A_CSC_MODE	0x49028
> -#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
> -#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
> -#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
> +#define  ICL_CSC_ENABLE			(1 << 31)
> +#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
> +#define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
> +#define  CSC_MODE_YUV_TO_RGB		(1 << 0)
> +
>  #define _PIPE_A_CSC_PREOFF_HI	0x49030
>  #define _PIPE_A_CSC_PREOFF_ME	0x49034
>  #define _PIPE_A_CSC_PREOFF_LO	0x49038
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 494891c..9b8d2de 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -134,6 +134,7 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>  	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
>  	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
>  	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
> +
>  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>  }

Seems like an unintentional change?

Otherwise, this looks good now that the output csc for rgb->yuv is moved
to the next patch.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  
> @@ -242,7 +243,10 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>  		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>  		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>  
> -		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> +		if (INTEL_GEN(dev_priv) >= 11)
> +			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
> +		else
> +			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>  	} else {
>  		uint32_t mode = CSC_MODE_YUV_TO_RGB;
>  
> @@ -692,6 +696,7 @@ void intel_color_init(struct intel_crtc *crtc)
>  		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = glk_load_luts;
>  	} else if (IS_ICELAKE(dev_priv)) {
> +		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = icl_load_luts;
>  	} else {
>  		dev_priv->display.load_luts = i9xx_load_luts;
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v6 5/6] drm/i915/icl: Enable pipe output csc

[Matt Roper]

On Wed, Jan 16, 2019 at 09:51:36PM +0530, Uma Shankar wrote:
> GEN11+ onwards an output csc hardware block has been added.
> This is after the pipe gamma block and is in addition to the
> legacy pipe CSC block. Primary use case for this block is to
> convert RGB to YUV in case sink supports YUV.
> This patch adds supports for the same.
> 
> v2: This is added after splitting the existing ICL pipe CSC
> handling. As per Matt's suggestion, made this to co-exist
> with existing pipe CSC, wherein both can be enabled if a
> certain usecase arises.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    | 41 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_drv.h   |  3 ++
>  3 files changed, 99 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c3a902..edd6b4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9864,6 +9864,7 @@ enum skl_power_gate {
>  
>  #define _PIPE_A_CSC_MODE	0x49028
>  #define  ICL_CSC_ENABLE			(1 << 31)
> +#define  ICL_OUTPUT_CSC_ENABLE		(1 << 30)
>  #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
>  #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
>  #define  CSC_MODE_YUV_TO_RGB		(1 << 0)
> @@ -9903,6 +9904,46 @@ enum skl_power_gate {
>  #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
>  #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>  
> +/* Pipe Output CSC */
> +#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
> +#define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
> +#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
> +#define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
> +#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
> +#define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
> +#define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
> +#define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
> +#define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
> +
> +#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
> +#define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
> +#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
> +#define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
> +#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
> +#define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
> +#define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
> +#define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
> +#define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
> +
> +#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RY_GY, _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
> +#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BY, _PIPE_B_OUTPUT_CSC_COEFF_BY)
> +#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
> +#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BU, _PIPE_B_OUTPUT_CSC_COEFF_BU)
> +#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
> +#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_COEFF_BV, _PIPE_B_OUTPUT_CSC_COEFF_BV)
> +#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_HI, _PIPE_B_OUTPUT_CSC_PREOFF_HI)
> +#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_ME, _PIPE_B_OUTPUT_CSC_PREOFF_ME)
> +#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_LO, _PIPE_B_OUTPUT_CSC_PREOFF_LO)
> +#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_HI, _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
> +#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_ME, _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
> +#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_POSTOFF_LO, _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
> +
>  /* pipe degamma/gamma LUTs on IVB+ */
>  #define _PAL_PREC_INDEX_A	0x4A400
>  #define _PAL_PREC_INDEX_B	0x4AC00
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 9b8d2de..c95adb9 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -113,29 +113,58 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
>  	return result;
>  }
>  
> -static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
> +static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc_state
> +					     *crtc_state)
>  {
> -	int pipe = crtc->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int pipe = crtc->pipe;
>  
> -	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> -	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> -	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
> +	if (INTEL_GEN(dev_priv) < 11) {
> +		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> +		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> +		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>  
> -	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
> -	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
> +		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
> +		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
>  
> -	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
> -	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
> +		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
> +		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
>  
> -	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
> -	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
> +		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
> +		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
>  
> -	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
> -	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
> -	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
> +		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
> +		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
> +		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
>  
> -	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> +		crtc_state->csc_mode = 0;

This should be set during the atomic check phase rather than during the
commit.  But I suspect that will happen anyway once Ville's series lands
and you rebase.

> +	} else {
> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
> +
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
> +			   CSC_RGB_TO_YUV_RU_GU);
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
> +
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
> +			   CSC_RGB_TO_YUV_RY_GY);
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
> +
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
> +			   CSC_RGB_TO_YUV_RV_GV);
> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
> +
> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
> +			   POSTOFF_RGB_TO_YUV_HI);
> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
> +			   POSTOFF_RGB_TO_YUV_ME);
> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
> +			   POSTOFF_RGB_TO_YUV_LO);
> +
> +		crtc_state->csc_mode = ICL_OUTPUT_CSC_ENABLE;
> +	}
>  }
>  
>  static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
> @@ -153,10 +182,14 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>  	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>  		limited_color_range = crtc_state->limited_color_range;
>  
> +	crtc_state->csc_mode = 0;
>  	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>  	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> -		ilk_load_ycbcr_conversion_matrix(crtc);
> -		return;
> +		ilk_load_ycbcr_conversion_matrix(crtc_state);
> +		if (INTEL_GEN(dev_priv) < 11) {
> +			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> +			return;
> +		}

Isn't this going to lead us to still exit immediately after programming
the output CSC?  I.e., we'll never program the userspace matrix into the
first CSC because that only happens in the 'else if (crtc_state->base.ctm)'
branch below.  We probably need to remove the RGB->YUV logic from
the if/else check that figures out what to program in the first CSC.


Matt

>  	} else if (crtc_state->base.ctm) {
>  		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>  		const u64 *input;
> @@ -243,10 +276,12 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>  		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>  		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>  
> -		if (INTEL_GEN(dev_priv) >= 11)
> -			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
> -		else
> +		if (INTEL_GEN(dev_priv) >= 11) {
> +			crtc_state->csc_mode |= ICL_CSC_ENABLE;
> +			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> +		} else {
>  			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> +		}
>  	} else {
>  		uint32_t mode = CSC_MODE_YUV_TO_RGB;
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e5a436c..320a413 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -930,6 +930,9 @@ struct intel_crtc_state {
>  	/* Gamma mode programmed on the pipe */
>  	uint32_t gamma_mode;
>  
> +	/* CSC mode programmed on the pipe */
> +	uint32_t csc_mode;
> +
>  	/* bitmask of visible planes (enum plane_id) */
>  	u8 active_planes;
>  	u8 nv12_planes;
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

[Shankar, Uma]

>-----Original Message-----
>From: Roper, Matthew D
>Sent: Tuesday, January 29, 2019 3:49 AM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
><maarten.lankhorst@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Sharma,
>Shashank <shashank.sharma@intel.com>
>Subject: Re: [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support
>
>On Wed, Jan 16, 2019 at 09:51:34PM +0530, Uma Shankar wrote:
>> Add support for icl pipe degamma and gamma.
>>
>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>> Maarten's comments.
>>
>> v3: Addressed Matt's review comments. Removed rmw patterns as
>> suggested by Matt.
>>
>> v4: Fixed Matt's review comments.
>>
>> v5: Corrected macro alignment as per Jani Nikula's comments.
>> Addressed Ville and Matt's  review comments.
>>
>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>> function as per Ville and Matt's comments.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
>The general changes and direction here look good, but this will need a rebase
>after Ville's series lands, so I'll wait on that to give the final r-b.

Ok, sure. Thanks Matt.

Regards,
Uma Shankar

>
>Matt
>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>>  drivers/gpu/drm/i915/intel_color.c | 21 +++++++++++++++++++++
>>  2 files changed, 28 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index fad5a9e..a84200f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7088,11 +7088,13 @@ enum {
>>  #define _GAMMA_MODE_A		0x4a480
>>  #define _GAMMA_MODE_B		0x4ac80
>>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>_GAMMA_MODE_B)
>> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
>> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
>> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
>> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
>> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
>> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
>> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
>> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
>> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
>> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
>> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>
>>  /* DMC/CSR */
>>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 3712bd0..494891c 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state
>*crtc_state)
>>  	POSTING_READ(GAMMA_MODE(pipe));
>>  }
>>
>> +static void icl_load_luts(struct intel_crtc_state *crtc_state) {
>> +	struct drm_crtc *crtc = crtc_state->base.crtc;
>> +	struct drm_device *dev = crtc_state->base.crtc->dev;
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +
>> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> +		haswell_load_luts(crtc_state);
>> +		return;
>> +	}
>> +
>> +	glk_load_degamma_lut(crtc_state);
>> +	bdw_load_gamma_lut(crtc_state, 0);
>> +
>> +	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
>> +		   PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE); }
>> +
>>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
>> static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>> { @@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
>>  	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>  		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = glk_load_luts;
>> +	} else if (IS_ICELAKE(dev_priv)) {
>> +		dev_priv->display.load_luts = icl_load_luts;
>>  	} else {
>>  		dev_priv->display.load_luts = i9xx_load_luts;
>>  	}
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v6 4/6] drm/i915/icl: Enable ICL Pipe CSC block

[Shankar, Uma]

>-----Original Message-----
>From: Roper, Matthew D
>Sent: Tuesday, January 29, 2019 3:50 AM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
><maarten.lankhorst@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Sharma,
>Shashank <shashank.sharma@intel.com>
>Subject: Re: [v6 4/6] drm/i915/icl: Enable ICL Pipe CSC block
>
>On Wed, Jan 16, 2019 at 09:51:35PM +0530, Uma Shankar wrote:
>> Enable ICL pipe csc hardware. CSC block is enabled in CSC_MODE
>> register instead of PLANE_COLOR_CTL.
>>
>> ToDO: Extend the ABI to accept 32 bit coefficient values instead of
>> 16bit for future platforms.
>>
>> v2: Addressed Maarten's review comments.
>>
>> v3: Addressed Matt's review comments. Removed rmw patterns as
>> suggested by Matt.
>>
>> v4: Addressed Matt's review comments.
>>
>> v5: Addressed Ville's review comments.
>>
>> v6: Separated pipe output csc programming from regular csc.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h    | 9 ++++++---
>>  drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
>>  2 files changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index a84200f..3c3a902 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9861,10 +9861,13 @@ enum skl_power_gate {
>>  #define _PIPE_A_CSC_COEFF_BU	0x4901c
>>  #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
>>  #define _PIPE_A_CSC_COEFF_BV	0x49024
>> +
>>  #define _PIPE_A_CSC_MODE	0x49028
>> -#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
>> -#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
>> -#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
>> +#define  ICL_CSC_ENABLE			(1 << 31)
>> +#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
>> +#define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
>> +#define  CSC_MODE_YUV_TO_RGB		(1 << 0)
>> +
>>  #define _PIPE_A_CSC_PREOFF_HI	0x49030
>>  #define _PIPE_A_CSC_PREOFF_ME	0x49034
>>  #define _PIPE_A_CSC_PREOFF_LO	0x49038
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 494891c..9b8d2de 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -134,6 +134,7 @@ static void ilk_load_ycbcr_conversion_matrix(struct
>intel_crtc *crtc)
>>  	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
>>  	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
>POSTOFF_RGB_TO_YUV_ME);
>>  	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
>> +
>>  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>>  }
>
>Seems like an unintentional change?

Ok, will drop this extra line. Did it intentionally though as wanted to separate the
co-efficients programming from the mode. It's not related to this patch.

Thanks Matt for the review.

Regards,
Uma Shankar

>Otherwise, this looks good now that the output csc for rgb->yuv is moved to the
>next patch.
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>
>> @@ -242,7 +243,10 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
>*crtc_state)
>>  		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>>  		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>>
>> -		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> +		if (INTEL_GEN(dev_priv) >= 11)
>> +			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
>> +		else
>> +			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>>  	} else {
>>  		uint32_t mode = CSC_MODE_YUV_TO_RGB;
>>
>> @@ -692,6 +696,7 @@ void intel_color_init(struct intel_crtc *crtc)
>>  		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = glk_load_luts;
>>  	} else if (IS_ICELAKE(dev_priv)) {
>> +		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = icl_load_luts;
>>  	} else {
>>  		dev_priv->display.load_luts = i9xx_load_luts;
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
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Intel-gfx mailing list
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Re: [v6 5/6] drm/i915/icl: Enable pipe output csc

[Shankar, Uma]

>-----Original Message-----
>From: Roper, Matthew D
>Sent: Tuesday, January 29, 2019 3:50 AM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
><maarten.lankhorst@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Sharma,
>Shashank <shashank.sharma@intel.com>
>Subject: Re: [v6 5/6] drm/i915/icl: Enable pipe output csc
>
>On Wed, Jan 16, 2019 at 09:51:36PM +0530, Uma Shankar wrote:
>> GEN11+ onwards an output csc hardware block has been added.
>> This is after the pipe gamma block and is in addition to the legacy
>> pipe CSC block. Primary use case for this block is to convert RGB to
>> YUV in case sink supports YUV.
>> This patch adds supports for the same.
>>
>> v2: This is added after splitting the existing ICL pipe CSC handling.
>> As per Matt's suggestion, made this to co-exist with existing pipe
>> CSC, wherein both can be enabled if a certain usecase arises.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h    | 41 +++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++-----
>-----
>>  drivers/gpu/drm/i915/intel_drv.h   |  3 ++
>>  3 files changed, 99 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 3c3a902..edd6b4d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9864,6 +9864,7 @@ enum skl_power_gate {
>>
>>  #define _PIPE_A_CSC_MODE	0x49028
>>  #define  ICL_CSC_ENABLE			(1 << 31)
>> +#define  ICL_OUTPUT_CSC_ENABLE		(1 << 30)
>>  #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
>>  #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
>>  #define  CSC_MODE_YUV_TO_RGB		(1 << 0)
>> @@ -9903,6 +9904,46 @@ enum skl_power_gate {
>>  #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
>>  #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>>
>> +/* Pipe Output CSC */
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
>> +#define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
>> +#define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
>> +#define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
>> +#define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
>> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
>> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
>> +#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
>> +
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
>> +#define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
>> +#define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
>> +#define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
>> +#define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
>> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
>> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
>> +#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
>> +
>> +#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_RY_GY, _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
>> +#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_BY, _PIPE_B_OUTPUT_CSC_COEFF_BY)
>> +#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_RU_GU, _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
>> +#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_BU, _PIPE_B_OUTPUT_CSC_COEFF_BU)
>> +#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_RV_GV, _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
>> +#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_COEFF_BV, _PIPE_B_OUTPUT_CSC_COEFF_BV)
>> +#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_PREOFF_HI, _PIPE_B_OUTPUT_CSC_PREOFF_HI)
>> +#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)
>	_MMIO_PIPE(pipe, _PIPE_A_OUTPUT_CSC_PREOFF_ME,
>_PIPE_B_OUTPUT_CSC_PREOFF_ME)
>> +#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_PREOFF_LO, _PIPE_B_OUTPUT_CSC_PREOFF_LO)
>> +#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_POSTOFF_HI, _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
>> +#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_POSTOFF_ME, _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
>> +#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe,
>_PIPE_A_OUTPUT_CSC_POSTOFF_LO, _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
>> +
>>  /* pipe degamma/gamma LUTs on IVB+ */
>>  #define _PAL_PREC_INDEX_A	0x4A400
>>  #define _PAL_PREC_INDEX_B	0x4AC00
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 9b8d2de..c95adb9 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -113,29 +113,58 @@ static u64 *ctm_mult_by_limited(u64 *result, const
>u64 *input)
>>  	return result;
>>  }
>>
>> -static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>> +static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc_state
>> +					     *crtc_state)
>>  {
>> -	int pipe = crtc->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	int pipe = crtc->pipe;
>>
>> -	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>> -	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>> -	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>> +	if (INTEL_GEN(dev_priv) < 11) {
>> +		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>> +		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>> +		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>>
>> -	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe),
>CSC_RGB_TO_YUV_RU_GU);
>> -	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
>> +		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe),
>CSC_RGB_TO_YUV_RU_GU);
>> +		I915_WRITE(PIPE_CSC_COEFF_BU(pipe),
>CSC_RGB_TO_YUV_BU);
>>
>> -	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
>> -	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
>> +		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe),
>CSC_RGB_TO_YUV_RY_GY);
>> +		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
>>
>> -	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
>> -	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
>> +		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe),
>CSC_RGB_TO_YUV_RV_GV);
>> +		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
>>
>> -	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
>> -	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
>POSTOFF_RGB_TO_YUV_ME);
>> -	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
>> +		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe),
>POSTOFF_RGB_TO_YUV_HI);
>> +		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
>POSTOFF_RGB_TO_YUV_ME);
>> +		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe),
>POSTOFF_RGB_TO_YUV_LO);
>>
>> -	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> +		crtc_state->csc_mode = 0;
>
>This should be set during the atomic check phase rather than during the commit.
>But I suspect that will happen anyway once Ville's series lands and you rebase.

Yes, will rebase this on top of Ville's series and take care.

>> +	} else {
>> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
>> +
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
>> +			   CSC_RGB_TO_YUV_RU_GU);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe),
>CSC_RGB_TO_YUV_BU);
>> +
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
>> +			   CSC_RGB_TO_YUV_RY_GY);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe),
>CSC_RGB_TO_YUV_BY);
>> +
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
>> +			   CSC_RGB_TO_YUV_RV_GV);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe),
>CSC_RGB_TO_YUV_BV);
>> +
>> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
>> +			   POSTOFF_RGB_TO_YUV_HI);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
>> +			   POSTOFF_RGB_TO_YUV_ME);
>> +		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
>> +			   POSTOFF_RGB_TO_YUV_LO);
>> +
>> +		crtc_state->csc_mode = ICL_OUTPUT_CSC_ENABLE;
>> +	}
>>  }
>>
>>  static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>> @@ -153,10 +182,14 @@ static void ilk_load_csc_matrix(struct
>intel_crtc_state *crtc_state)
>>  	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>>  		limited_color_range = crtc_state->limited_color_range;
>>
>> +	crtc_state->csc_mode = 0;
>>  	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>>  	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>> -		ilk_load_ycbcr_conversion_matrix(crtc);
>> -		return;
>> +		ilk_load_ycbcr_conversion_matrix(crtc_state);
>> +		if (INTEL_GEN(dev_priv) < 11) {
>> +			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state-
>>csc_mode);
>> +			return;
>> +		}
>
>Isn't this going to lead us to still exit immediately after programming the output
>CSC?  I.e., we'll never program the userspace matrix into the first CSC because
>that only happens in the 'else if (crtc_state->base.ctm)'
>branch below.  We probably need to remove the RGB->YUV logic from the if/else
>check that figures out what to program in the first CSC.

Yes you are right. I will de-couple this making sure both output csc for RGB-YUV and
user controlled normal pipe csc co-work together.

Regards,
Uma Shankar

>
>Matt
>
>>  	} else if (crtc_state->base.ctm) {
>>  		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>>  		const u64 *input;
>> @@ -243,10 +276,12 @@ static void ilk_load_csc_matrix(struct
>intel_crtc_state *crtc_state)
>>  		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>>  		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>>
>> -		if (INTEL_GEN(dev_priv) >= 11)
>> -			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
>> -		else
>> +		if (INTEL_GEN(dev_priv) >= 11) {
>> +			crtc_state->csc_mode |= ICL_CSC_ENABLE;
>> +			I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state-
>>csc_mode);
>> +		} else {
>>  			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> +		}
>>  	} else {
>>  		uint32_t mode = CSC_MODE_YUV_TO_RGB;
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index e5a436c..320a413 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -930,6 +930,9 @@ struct intel_crtc_state {
>>  	/* Gamma mode programmed on the pipe */
>>  	uint32_t gamma_mode;
>>
>> +	/* CSC mode programmed on the pipe */
>> +	uint32_t csc_mode;
>> +
>>  	/* bitmask of visible planes (enum plane_id) */
>>  	u8 active_planes;
>>  	u8 nv12_planes;
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
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