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From: Andrew Jeffery <andrew@aj.id.au>
To: Stefan Schaeckeler <schaecsn@gmx.net>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Joel Stanley <joel@jms.id.au>, Borislav Petkov <bp@alien8.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org
Cc: Stefan M Schaeckeler <sschaeck@cisco.com>
Subject: Re: [PATCH v2 2/2] dt-bindings: edac: Aspeed AST2500
Date: Fri, 18 Jan 2019 15:43:54 +1030	[thread overview]
Message-ID: <1547788434.2065387.1637728584.1098F843@webmail.messagingengine.com> (raw)
In-Reply-To: <1547743097-5236-3-git-send-email-schaecsn@gmx.net>

On Fri, 18 Jan 2019, at 03:08, Stefan Schaeckeler wrote:
> From: Stefan M Schaeckeler <sschaeck@cisco.com>
> 
> Add support for EDAC on the Aspeed AST2500 SoC.
> 
> Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

> ---
>  .../bindings/edac/aspeed-sdram-edac.txt       | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> 
> diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-
> edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> new file mode 100644
> index 000000000000..6a0f3d90d682
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> @@ -0,0 +1,25 @@
> +Aspeed AST2500 SoC EDAC node
> +
> +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without 
> ECC (error
> +correction check).
> +
> +The memory controller supports SECDED (single bit error correction, 
> double bit
> +error detection) and single bit error auto scrubbing by reserving 8 
> bits for
> +every 64 bit word (effectively reducing available memory to 8/9).
> +
> +Note, the bootloader must configure ECC mode in the memory controller.
> +
> +
> +Required properties:
> +- compatible: should be "aspeed,ast2500-sdram-edac"
> +- reg:        sdram controller register set should be <0x1e6e0000 
> 0x174>
> +- interrupts: should be AVIC interrupt #0
> +
> +
> +Example:
> +
> +	edac: sdram@1e6e0000 {
> +		compatible = "aspeed,ast2500-sdram-edac";
> +		reg = <0x1e6e0000 0x174>;
> +		interrupts = <0>;
> +	};
> -- 
> 2.19.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jeffery <andrew@aj.id.au>
To: Stefan Schaeckeler <schaecsn@gmx.net>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Joel Stanley <joel@jms.id.au>, Borislav Petkov <bp@alien8.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org
Cc: Stefan M Schaeckeler <sschaeck@cisco.com>
Subject: [v2,2/2] dt-bindings: edac: Aspeed AST2500
Date: Fri, 18 Jan 2019 15:43:54 +1030	[thread overview]
Message-ID: <1547788434.2065387.1637728584.1098F843@webmail.messagingengine.com> (raw)

On Fri, 18 Jan 2019, at 03:08, Stefan Schaeckeler wrote:
> From: Stefan M Schaeckeler <sschaeck@cisco.com>
> 
> Add support for EDAC on the Aspeed AST2500 SoC.
> 
> Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

> ---
>  .../bindings/edac/aspeed-sdram-edac.txt       | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> 
> diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-
> edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> new file mode 100644
> index 000000000000..6a0f3d90d682
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> @@ -0,0 +1,25 @@
> +Aspeed AST2500 SoC EDAC node
> +
> +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without 
> ECC (error
> +correction check).
> +
> +The memory controller supports SECDED (single bit error correction, 
> double bit
> +error detection) and single bit error auto scrubbing by reserving 8 
> bits for
> +every 64 bit word (effectively reducing available memory to 8/9).
> +
> +Note, the bootloader must configure ECC mode in the memory controller.
> +
> +
> +Required properties:
> +- compatible: should be "aspeed,ast2500-sdram-edac"
> +- reg:        sdram controller register set should be <0x1e6e0000 
> 0x174>
> +- interrupts: should be AVIC interrupt #0
> +
> +
> +Example:
> +
> +	edac: sdram@1e6e0000 {
> +		compatible = "aspeed,ast2500-sdram-edac";
> +		reg = <0x1e6e0000 0x174>;
> +		interrupts = <0>;
> +	};
> -- 
> 2.19.1
>

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jeffery <andrew@aj.id.au>
To: Stefan Schaeckeler <schaecsn@gmx.net>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Joel Stanley <joel@jms.id.au>, Borislav Petkov <bp@alien8.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org
Cc: Stefan M Schaeckeler <sschaeck@cisco.com>
Subject: Re: [PATCH v2 2/2] dt-bindings: edac: Aspeed AST2500
Date: Fri, 18 Jan 2019 15:43:54 +1030	[thread overview]
Message-ID: <1547788434.2065387.1637728584.1098F843@webmail.messagingengine.com> (raw)
In-Reply-To: <1547743097-5236-3-git-send-email-schaecsn@gmx.net>

On Fri, 18 Jan 2019, at 03:08, Stefan Schaeckeler wrote:
> From: Stefan M Schaeckeler <sschaeck@cisco.com>
> 
> Add support for EDAC on the Aspeed AST2500 SoC.
> 
> Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

> ---
>  .../bindings/edac/aspeed-sdram-edac.txt       | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> 
> diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-
> edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> new file mode 100644
> index 000000000000..6a0f3d90d682
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> @@ -0,0 +1,25 @@
> +Aspeed AST2500 SoC EDAC node
> +
> +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without 
> ECC (error
> +correction check).
> +
> +The memory controller supports SECDED (single bit error correction, 
> double bit
> +error detection) and single bit error auto scrubbing by reserving 8 
> bits for
> +every 64 bit word (effectively reducing available memory to 8/9).
> +
> +Note, the bootloader must configure ECC mode in the memory controller.
> +
> +
> +Required properties:
> +- compatible: should be "aspeed,ast2500-sdram-edac"
> +- reg:        sdram controller register set should be <0x1e6e0000 
> 0x174>
> +- interrupts: should be AVIC interrupt #0
> +
> +
> +Example:
> +
> +	edac: sdram@1e6e0000 {
> +		compatible = "aspeed,ast2500-sdram-edac";
> +		reg = <0x1e6e0000 0x174>;
> +		interrupts = <0>;
> +	};
> -- 
> 2.19.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-01-18  5:14 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-17 16:38 [PATCH v2 0/2] Add support for the Aspeed AST2500 SoC EDAC driver Stefan Schaeckeler
2019-01-17 16:38 ` Stefan Schaeckeler
2019-01-17 16:38 ` [PATCH v2 1/2] EDAC: Add Aspeed AST2500 " Stefan Schaeckeler
2019-01-17 16:38   ` Stefan Schaeckeler
2019-01-17 16:38   ` [v2,1/2] " Stefan Schaeckeler
2019-01-17 16:38 ` [PATCH v2 2/2] dt-bindings: edac: Aspeed AST2500 Stefan Schaeckeler
2019-01-17 16:38   ` Stefan Schaeckeler
2019-01-17 16:38   ` [v2,2/2] " Stefan Schaeckeler
2019-01-18  5:13   ` Andrew Jeffery [this message]
2019-01-18  5:13     ` [PATCH v2 2/2] " Andrew Jeffery
2019-01-18  5:13     ` [v2,2/2] " Andrew Jeffery
2019-01-18 14:28 ` [PATCH v2 0/2] Add support for the Aspeed AST2500 SoC EDAC driver Borislav Petkov
2019-01-18 14:28   ` Borislav Petkov

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