* [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
@ 2019-01-23 15:39 Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for " Horatiu Vultur
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
This patch series adds support for MSCC Serval SoC family. In this
family there are the following boards: pcb105 and pcb106.
This is based off the patch series[1].
[1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
Horatiu Vultur (5):
pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
MSCC: Add support for Serval SoC family.
MSCC: add device tree for Serval pcb105 board
MSCC: Add device tree for Serval pcb106 board
MSCC: Add board support for Serval SoC family.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mscc,serval.dtsi | 149 ++++++++++
arch/mips/dts/serval_pcb105.dts | 56 ++++
arch/mips/dts/serval_pcb106.dts | 56 ++++
arch/mips/mach-mscc/Kconfig | 9 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 2 +-
arch/mips/mach-mscc/dram.c | 2 +-
arch/mips/mach-mscc/include/mach/common.h | 5 +
arch/mips/mach-mscc/include/mach/ddr.h | 20 +-
arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++
.../include/mach/serval/serval_devcpu_gcb.h | 21 ++
.../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++
.../include/mach/serval/serval_icpu_cfg.h | 314 +++++++++++++++++++++
arch/mips/mach-mscc/reset.c | 25 +-
board/mscc/serval/Kconfig | 14 +
board/mscc/serval/Makefile | 3 +
board/mscc/serval/serval.c | 74 +++++
configs/mscc_serval_defconfig | 62 ++++
drivers/pinctrl/mscc/Kconfig | 10 +
drivers/pinctrl/mscc/Makefile | 1 +
drivers/pinctrl/mscc/pinctrl-serval.c | 233 +++++++++++++++
include/configs/vcoreiii.h | 5 +-
23 files changed, 1098 insertions(+), 14 deletions(-)
create mode 100644 arch/mips/dts/mscc,serval.dtsi
create mode 100644 arch/mips/dts/serval_pcb105.dts
create mode 100644 arch/mips/dts/serval_pcb106.dts
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
create mode 100644 board/mscc/serval/Kconfig
create mode 100644 board/mscc/serval/Makefile
create mode 100644 board/mscc/serval/serval.c
create mode 100644 configs/mscc_serval_defconfig
create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c
--
2.7.4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
@ 2019-01-23 15:39 ` Horatiu Vultur
2019-01-23 17:01 ` Daniel Schwierzeck
2019-01-23 15:39 ` [U-Boot] [PATCH 2/5] MSCC: Add support " Horatiu Vultur
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
drivers/pinctrl/mscc/Kconfig | 10 ++
drivers/pinctrl/mscc/Makefile | 1 +
drivers/pinctrl/mscc/pinctrl-serval.c | 233 ++++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+)
create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
index 0269565..aab67fa 100644
--- a/drivers/pinctrl/mscc/Kconfig
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -38,3 +38,13 @@ config PINCTRL_MSCC_SERVALT
help
Support pin multiplexing and pin configuration control on
Microsemi servalt SoCs.
+
+config PINCTRL_MSCC_SERVAL
+ depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi serval family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi serval SoCs.
+
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
index c6b0373..fd7eba2 100644
--- a/drivers/pinctrl/mscc/Makefile
+++ b/drivers/pinctrl/mscc/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVAL) += pinctrl-serval.o
diff --git a/drivers/pinctrl/mscc/pinctrl-serval.c b/drivers/pinctrl/mscc/pinctrl-serval.c
new file mode 100644
index 0000000..d59f08d
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-serval.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0,
+ FUNC_IRQ1,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SIO,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MD,
+ FUNC_PTP1588,
+ FUNC_MAX
+};
+
+static char * const serval_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
+ [FUNC_IRQ1] = "irq1",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SIO] = "sio",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+ [FUNC_MD] = "md",
+ [FUNC_PTP1588] = "1588",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, PWM, NONE, NONE);
+MSCC_P(6, TWI, NONE, NONE);
+MSCC_P(7, TWI, NONE, NONE);
+MSCC_P(8, SI, NONE, NONE);
+MSCC_P(9, SI, MD, NONE);
+MSCC_P(10, SI, MD, NONE);
+MSCC_P(11, SFP0, MD, TWI_SCL_M);
+MSCC_P(12, SFP1, MD, TWI_SCL_M);
+MSCC_P(13, SFP2, UART2, TWI_SCL_M);
+MSCC_P(14, SFP3, UART2, TWI_SCL_M);
+MSCC_P(15, SFP4, PTP1588, TWI_SCL_M);
+MSCC_P(16, SFP5, PTP1588, TWI_SCL_M);
+MSCC_P(17, SFP6, PCI_WAKE, TWI_SCL_M);
+MSCC_P(18, SFP7, NONE, TWI_SCL_M);
+MSCC_P(19, SFP8, NONE, TWI_SCL_M);
+MSCC_P(20, SFP9, NONE, TWI_SCL_M);
+MSCC_P(21, SFP10, NONE, TWI_SCL_M);
+MSCC_P(22, NONE, NONE, NONE);
+MSCC_P(23, NONE, NONE, NONE);
+MSCC_P(24, NONE, NONE, NONE);
+MSCC_P(25, NONE, NONE, NONE);
+MSCC_P(26, UART, NONE, NONE);
+MSCC_P(27, UART, NONE, NONE);
+MSCC_P(28, IRQ0, NONE, NONE);
+MSCC_P(29, IRQ1, NONE, NONE);
+MSCC_P(30, PTP1588, NONE, NONE);
+MSCC_P(31, PTP1588, NONE, NONE);
+
+#define SERVAL_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data serval_pins[] = {
+ SERVAL_PIN(0),
+ SERVAL_PIN(1),
+ SERVAL_PIN(2),
+ SERVAL_PIN(3),
+ SERVAL_PIN(4),
+ SERVAL_PIN(5),
+ SERVAL_PIN(6),
+ SERVAL_PIN(7),
+ SERVAL_PIN(8),
+ SERVAL_PIN(9),
+ SERVAL_PIN(10),
+ SERVAL_PIN(11),
+ SERVAL_PIN(12),
+ SERVAL_PIN(13),
+ SERVAL_PIN(14),
+ SERVAL_PIN(15),
+ SERVAL_PIN(16),
+ SERVAL_PIN(17),
+ SERVAL_PIN(18),
+ SERVAL_PIN(19),
+ SERVAL_PIN(20),
+ SERVAL_PIN(21),
+ SERVAL_PIN(22),
+ SERVAL_PIN(23),
+ SERVAL_PIN(24),
+ SERVAL_PIN(25),
+ SERVAL_PIN(26),
+ SERVAL_PIN(27),
+ SERVAL_PIN(28),
+ SERVAL_PIN(29),
+ SERVAL_PIN(30),
+ SERVAL_PIN(31),
+};
+
+static const unsigned long serval_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x04,
+ [MSCC_GPIO_OUT] = 0x08,
+ [MSCC_GPIO_IN] = 0x0c,
+ [MSCC_GPIO_OE] = 0x10,
+ [MSCC_GPIO_INTR] = 0x14,
+ [MSCC_GPIO_INTR_ENA] = 0x18,
+ [MSCC_GPIO_INTR_IDENT] = 0x1c,
+ [MSCC_GPIO_ALT0] = 0x20,
+ [MSCC_GPIO_ALT1] = 0x24,
+};
+
+static int serval_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "serval-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(serval_pins);
+
+ return 0;
+}
+
+static struct driver serval_gpio_driver = {
+ .name = "serval-gpio",
+ .id = UCLASS_GPIO,
+ .probe = serval_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int serval_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, serval_pins,
+ ARRAY_SIZE(serval_pins),
+ serval_function_names,
+ serval_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
+ dev_of_offset(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id serval_pinctrl_of_match[] = {
+ { .compatible = "mscc,serval-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(serval_pinctrl) = {
+ .name = "serval-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(serval_pinctrl_of_match),
+ .probe = serval_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/5] MSCC: Add support for Serval SoC family.
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for " Horatiu Vultur
@ 2019-01-23 15:39 ` Horatiu Vultur
2019-01-23 17:04 ` Daniel Schwierzeck
2019-01-23 15:39 ` [U-Boot] [PATCH 3/5] MSCC: add device tree for Serval pcb105 board Horatiu Vultur
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
arch/mips/mach-mscc/Kconfig | 9 +
arch/mips/mach-mscc/cpu.c | 2 +-
arch/mips/mach-mscc/dram.c | 2 +-
arch/mips/mach-mscc/include/mach/common.h | 5 +
arch/mips/mach-mscc/include/mach/ddr.h | 20 +-
arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++
.../include/mach/serval/serval_devcpu_gcb.h | 21 ++
.../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++
.../include/mach/serval/serval_icpu_cfg.h | 314 +++++++++++++++++++++
arch/mips/mach-mscc/reset.c | 25 +-
include/configs/vcoreiii.h | 5 +-
11 files changed, 438 insertions(+), 14 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 80e4b44..34584a1 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -47,6 +47,13 @@ config SOC_SERVALT
help
This supports MSCC Servalt family of SOCs.
+config SOC_SERVAL
+ bool "Serval SOC Family"
+ select SOC_VCOREIII
+ select MSCC_BB_SPI
+ help
+ This supports MSCC Serval family of SOCs.
+
endchoice
config SYS_CONFIG_NAME
@@ -82,4 +89,6 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
source "board/mscc/servalt/Kconfig"
+
+source "board/mscc/serval/Kconfig"
endmenu
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 1bfd636..ac75d51 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -87,7 +87,7 @@ int mach_cpu_init(void)
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#else
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 2073821..c43f7a5 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -20,7 +20,7 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
index 97b3f82..8f9a9c2 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -26,6 +26,11 @@
#include <mach/servalt/servalt_devcpu_gcb.h>
#include <mach/servalt/servalt_devcpu_gcb_miim_regs.h>
#include <mach/servalt/servalt_icpu_cfg.h>
+#elif defined(CONFIG_SOC_SERVAL)
+#include <mach/serval/serval.h>
+#include <mach/serval/serval_devcpu_gcb.h>
+#include <mach/serval/serval_devcpu_gcb_miim_regs.h>
+#include <mach/serval/serval_icpu_cfg.h>
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index ff32f22..84ecfbd 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -25,7 +25,7 @@
#define VC3_MPAR_CL 6
#define VC3_MPAR_tWTR 4
#define VC3_MPAR_tRC 16
-#define VC3_MPR_tFAW 16
+#define VC3_MPAR_tFAW 16
#define VC3_MPAR_tRP 5
#define VC3_MPAR_tRRD 4
#define VC3_MPAR_tRCD 5
@@ -162,7 +162,7 @@
#endif
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
@@ -241,7 +241,7 @@
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MSCC_MEMPARM_PERIOD \
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
@@ -381,7 +381,7 @@ static inline void memphy_soft_reset(void)
}
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
@@ -452,7 +452,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
-#else /* JR2 || ServalT */
+#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* Ensure the memory controller physical iface is forced reset */
@@ -471,7 +471,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
-#endif
+#endif /* JR2 || ServalT || Serval */
/*
* DDR memory sanity checking done, possibly enable ECC.
@@ -778,7 +778,7 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
#else /* Luton */
clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
@@ -793,7 +793,7 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
-#if defined(CONFIG_SOC_OCELOT)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/* Termination setup - enable ODT */
writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
/* Assert ODT0 for any write */
@@ -801,7 +801,9 @@ static inline void hal_vcoreiii_init_memctl(void)
BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
/* Release Reset from DDR */
+#if defined(CONFIG_SOC_OCELOT)
hal_vcoreiii_ddr_reset_release();
+#endif
writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
#elif defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
@@ -826,7 +828,7 @@ static inline void hal_vcoreiii_wait_memctl(void)
/* Settle...? */
sleep_100ns(10000);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
/* Establish data contents in DDR RAM for training */
__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
diff --git a/arch/mips/mach-mscc/include/mach/serval/serval.h b/arch/mips/mach-mscc/include/mach/serval/serval.h
new file mode 100644
index 0000000..763d18f
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/serval/serval.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Serval Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_H_
+#define _MSCC_SERVAL_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN1_SIZE 0x00200000
+#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
+#define MSCC_IO_ORIGIN2_SIZE 0x01000000
+#define BASE_CFG ((void __iomem *)0x70000000)
+#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
new file mode 100644
index 0000000..9b80fdb
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_DEVCPU_GCB_H_
+#define _MSCC_SERVAL_DEVCPU_GCB_H_
+
+#define CHIP_ID 0x0
+
+#define PERF_GPR 0x4
+
+#define PERF_SOFT_RST 0x8
+
+#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
+#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+
+#define GPIO_ALT(x) (0x54 + 4 * (x))
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
new file mode 100644
index 0000000..a3abbc40
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
+#define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0x5c + (gi * 36))
+#define MIIM_MII_CMD(gi) (0x64 + (gi * 36))
+#define MIIM_MII_DATA(gi) (0x68 + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
+#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
new file mode 100644
index 0000000..b8c9d5c
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
@@ -0,0 +1,314 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_ICPU_CFG_H_
+#define _MSCC_SERVAL_ICPU_CFG_H_
+
+#define ICPU_GPR(x) (0x4 * (x))
+#define ICPU_GPR_RSZ 0x8
+
+#define ICPU_RESET 0x20
+
+#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
+#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
+#define ICPU_RESET_CORE_RST_FORCE BIT(1)
+#define ICPU_RESET_MEM_RST_FORCE BIT(0)
+
+#define ICPU_GENERAL_CTRL 0x24
+
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
+#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
+#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(6)
+#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(5)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(4)
+#define ICPU_GENERAL_CTRL_IF_SI_MST_ENA BIT(3)
+#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
+#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
+#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
+
+#define ICPU_SPI_MST_CFG 0x3c
+
+#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
+#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SW_MODE 0x50
+
+#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
+#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
+#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
+#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
+#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
+#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
+#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
+
+#define ICPU_INTR_ENA 0x84
+
+#define ICPU_DST_INTR_MAP(x) (0x94 + 0x4 * (x))
+#define ICPU_DST_INTR_MAP_RSZ 0x4
+
+#define ICPU_TIMER_TICK_DIV 0xe0
+
+#define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x))
+#define ICPU_TIMER_VALUE_RSZ 0x2
+
+#define ICPU_TIMER_CTRL(x) (0xfc + 0x4 * (x))
+#define ICPU_TIMER_CTRL_RSZ 0x2
+
+#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
+#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
+#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
+#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
+
+#define ICPU_MEMCTRL_CTRL 0x108
+
+#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
+#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
+#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
+#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
+
+#define ICPU_MEMCTRL_CFG 0x10c
+
+#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
+#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
+#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
+#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
+#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
+#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_STAT 0x110
+
+#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
+#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
+#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
+#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
+
+#define ICPU_MEMCTRL_REF_PERIOD 0x114
+
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_ZQCAL 0x118
+
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
+
+#define ICPU_MEMCTRL_TIMING0 0x11c
+
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING1 0x120
+
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING2 0x124
+
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING3 0x128
+
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING4 0x12c
+
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
+
+#define ICPU_MEMCTRL_MR0_VAL 0x130
+
+#define ICPU_MEMCTRL_MR1_VAL 0x134
+
+#define ICPU_MEMCTRL_MR2_VAL 0x138
+
+#define ICPU_MEMCTRL_MR3_VAL 0x13c
+
+#define ICPU_MEMCTRL_TERMRES_CTRL 0x140
+
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DFT 0x144
+
+#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
+#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
+#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
+#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
+#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DQS_DLY(x) (0x148 + 0x4 * (x))
+#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
+
+#define ICPU_MEMCTRL_DQS_AUTO 0x150
+#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
+
+#define ICPU_MEMPHY_CFG 0x158
+
+#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
+#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
+#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
+#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
+#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
+#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
+#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
+#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
+#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
+#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
+#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
+
+#define ICPU_MEMPHY_ZCAL 0x180
+
+#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
+
+#define ICPU_MEMPHY_ZCAL_STAT 0x184
+
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
+
+#endif
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index 3740225..a555fc9 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -27,7 +27,30 @@ void _machine_restart(void)
ICPU_RESET_CORE_RST_CPU_ONLY |
ICPU_RESET_CORE_RST_FORCE,
BASE_CFG + ICPU_RESET);
-#else
+#elif defined(CONFIG_SOC_SERVAL)
+ register unsigned long i;
+
+ /* Prevent VCore-III from being reset with a global reset */
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+
+ /* Do global reset */
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ for (i = 0; i < 1000; i++)
+ ;
+
+ /* Power down DDR for clean DDR re-training */
+ writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
+ ICPU_MEMCTRL_CTRL_PWR_DOWN,
+ BASE_CFG + ICPU_MEMCTRL_CTRL);
+
+ while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
+ ICPU_MEMCTRL_STAT_PWR_DOWN_ACK))
+ ;
+
+ /* Reset VCore-III, only. */
+ writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET);
+#else /* Luton || Ocelot */
register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index 4ea5f40..8c30c6f 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h
@@ -14,10 +14,11 @@
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
-#ifdef CONFIG_SOC_LUTON
+#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
+#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
#else
+#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 3/5] MSCC: add device tree for Serval pcb105 board
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for " Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 2/5] MSCC: Add support " Horatiu Vultur
@ 2019-01-23 15:39 ` Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 4/5] MSCC: Add device tree for Serval pcb106 board Horatiu Vultur
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
Add device tree based on evaluation board pcb105.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
arch/mips/dts/mscc,serval.dtsi | 149 ++++++++++++++++++++++++++++++++++++++++
arch/mips/dts/serval_pcb105.dts | 56 +++++++++++++++
2 files changed, 205 insertions(+)
create mode 100644 arch/mips/dts/mscc,serval.dtsi
create mode 100644 arch/mips/dts/serval_pcb105.dts
diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi
new file mode 100644
index 0000000..bd60051
--- /dev/null
+++ b/arch/mips/dts/mscc,serval.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller at 0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon at 0 {
+ compatible = "mscc,serval-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller at 70 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial at 100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial at 100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset at 1070008 {
+ compatible = "mscc,serval-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl at 1070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sio";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_13", "GPIO_14";
+ function = "uart2";
+ };
+ };
+
+ spi0: spi-bitbang {
+ compatible = "mscc,luton-bb-spi";
+ status = "okay";
+ reg = <0x50 0x4>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sgpio: gpio at 10700b4 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700b4 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&sgpio 0 0 64>;
+ };
+ };
+};
diff --git a/arch/mips/dts/serval_pcb105.dts b/arch/mips/dts/serval_pcb105.dts
new file mode 100644
index 0000000..d0d6fac
--- /dev/null
+++ b/arch/mips/dts/serval_pcb105.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB105 Reference Board";
+ compatible = "mscc,serval-pcb105", "mscc,serval";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb105:green:status";
+ gpios = <&sgpio 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb105:red:status";
+ gpios = <&sgpio 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash at 0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x00FFFFFF>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/5] MSCC: Add device tree for Serval pcb106 board
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
` (2 preceding siblings ...)
2019-01-23 15:39 ` [U-Boot] [PATCH 3/5] MSCC: add device tree for Serval pcb105 board Horatiu Vultur
@ 2019-01-23 15:39 ` Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family Horatiu Vultur
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
Add device tree based on evaluation board pcb106.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
arch/mips/dts/serval_pcb106.dts | 56 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 arch/mips/dts/serval_pcb106.dts
diff --git a/arch/mips/dts/serval_pcb106.dts b/arch/mips/dts/serval_pcb106.dts
new file mode 100644
index 0000000..1198249
--- /dev/null
+++ b/arch/mips/dts/serval_pcb106.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB106 Reference Board";
+ compatible = "mscc,serval-pcb106", "mscc,serval";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb106:green:status";
+ gpios = <&sgpio 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb106:red:status";
+ gpios = <&sgpio 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash at 0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x00FFFFFF>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family.
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
` (3 preceding siblings ...)
2019-01-23 15:39 ` [U-Boot] [PATCH 4/5] MSCC: Add device tree for Serval pcb106 board Horatiu Vultur
@ 2019-01-23 15:39 ` Horatiu Vultur
2019-01-23 17:06 ` Daniel Schwierzeck
2019-01-23 16:38 ` [U-Boot] [PATCH 0/5] MSCC: Add " Daniel Schwierzeck
2019-01-23 20:12 ` Daniel Schwierzeck
6 siblings, 1 reply; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 15:39 UTC (permalink / raw)
To: u-boot
Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
arch/mips/dts/Makefile | 1 +
arch/mips/mach-mscc/Makefile | 1 +
board/mscc/serval/Kconfig | 14 ++++++++
board/mscc/serval/Makefile | 3 ++
board/mscc/serval/serval.c | 74 +++++++++++++++++++++++++++++++++++++++++++
configs/mscc_serval_defconfig | 62 ++++++++++++++++++++++++++++++++++++
6 files changed, 155 insertions(+)
create mode 100644 board/mscc/serval/Kconfig
create mode 100644 board/mscc/serval/Makefile
create mode 100644 board/mscc/serval/serval.c
create mode 100644 configs/mscc_serval_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index af264ff..b94b582 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
+dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
targets += $(dtb-y)
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index f5b6968..6d60020 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -5,3 +5,4 @@ CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
obj-$(CONFIG_SOC_OCELOT) += gpio.o
+obj-$(CONFIG_SOC_SERVAL) += gpio.o
diff --git a/board/mscc/serval/Kconfig b/board/mscc/serval/Kconfig
new file mode 100644
index 0000000..64f1c68
--- /dev/null
+++ b/board/mscc/serval/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVAL
+
+config SYS_BOARD
+ default "serval"
+
+config SYS_CONFIG_NAME
+ default "serval"
+
+endif
diff --git a/board/mscc/serval/Makefile b/board/mscc/serval/Makefile
new file mode 100644
index 0000000..c7ba56e
--- /dev/null
+++ b/board/mscc/serval/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVAL) := serval.o
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
new file mode 100644
index 0000000..24ee5e5
--- /dev/null
+++ b/board/mscc/serval/serval.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+ BOARD_TYPE_PCB106 = 0xAABBCD00,
+ BOARD_TYPE_PCB105,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ u16 gpio_in_reg;
+
+ /* Set MDIO and MDC */
+ mscc_gpio_set_alternate(9, 2);
+ mscc_gpio_set_alternate(10, 2);
+
+ /* Set GPIO page */
+ mscc_phy_wr(1, 16, 31, 0x10);
+ if (!mscc_phy_rd(1, 16, 15, &gpio_in_reg)) {
+ if (gpio_in_reg & 0x200)
+ gd->board_type = BOARD_TYPE_PCB106;
+ else
+ gd->board_type = BOARD_TYPE_PCB105;
+ mscc_phy_wr(1, 16, 15, 0);
+ } else {
+ gd->board_type = BOARD_TYPE_PCB105;
+ }
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB106 &&
+ strcmp(name, "serval_pcb106") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB105 &&
+ strcmp(name, "serval_pcb105") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
new file mode 100644
index 0000000..263e37d
--- /dev/null
+++ b/configs/mscc_serval_defconfig
@@ -0,0 +1,62 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_SOC_SERVAL=y
+CONFIG_DDRTYPE_H5TQ1G63BFA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="serval # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106"
+CONFIG_OF_LIST="serval_pcb106 serval_pcb105"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MSCC_BB_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
` (4 preceding siblings ...)
2019-01-23 15:39 ` [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family Horatiu Vultur
@ 2019-01-23 16:38 ` Daniel Schwierzeck
2019-01-23 16:47 ` Horatiu Vultur
2019-01-23 20:12 ` Daniel Schwierzeck
6 siblings, 1 reply; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 16:38 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> This patch series adds support for MSCC Serval SoC family. In this
> family there are the following boards: pcb105 and pcb106.
>
> This is based off the patch series[1].
>
> [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
>
> Horatiu Vultur (5):
> pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
> MSCC: Add support for Serval SoC family.
> MSCC: add device tree for Serval pcb105 board
> MSCC: Add device tree for Serval pcb106 board
> MSCC: Add board support for Serval SoC family.
>
is this a resend or an extension of your v2 series?
Normally a resend is not necessary and should be annotated accordingly.
If this is an update, then you should have sent it as a v3 with a proper
changelog.
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
2019-01-23 16:38 ` [U-Boot] [PATCH 0/5] MSCC: Add " Daniel Schwierzeck
@ 2019-01-23 16:47 ` Horatiu Vultur
2019-01-23 16:58 ` Daniel Schwierzeck
0 siblings, 1 reply; 13+ messages in thread
From: Horatiu Vultur @ 2019-01-23 16:47 UTC (permalink / raw)
To: u-boot
Hi Daniel,
The 01/23/2019 17:38, Daniel Schwierzeck wrote:
>
>
> Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> > This patch series adds support for MSCC Serval SoC family. In this
> > family there are the following boards: pcb105 and pcb106.
> >
> > This is based off the patch series[1].
> >
> > [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
> >
> > Horatiu Vultur (5):
> > pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
> > MSCC: Add support for Serval SoC family.
> > MSCC: add device tree for Serval pcb105 board
> > MSCC: Add device tree for Serval pcb106 board
> > MSCC: Add board support for Serval SoC family.
> >
>
> is this a resend or an extension of your v2 series?
>
> Normally a resend is not necessary and should be annotated accordingly.
> If this is an update, then you should have sent it as a v3 with a proper
> changelog.
Well, it is none, it is a new patch series.
The one in [1] is for ServalT while this patch series is for Serval.
There are 2 different SoC families.
[1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
>
> --
> - Daniel
--
/Horatiu
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
2019-01-23 16:47 ` Horatiu Vultur
@ 2019-01-23 16:58 ` Daniel Schwierzeck
0 siblings, 0 replies; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 16:58 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 17:47 schrieb Horatiu Vultur:
> Hi Daniel,
>
> The 01/23/2019 17:38, Daniel Schwierzeck wrote:
>>
>>
>> Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
>>> This patch series adds support for MSCC Serval SoC family. In this
>>> family there are the following boards: pcb105 and pcb106.
>>>
>>> This is based off the patch series[1].
>>>
>>> [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
>>>
>>> Horatiu Vultur (5):
>>> pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
>>> MSCC: Add support for Serval SoC family.
>>> MSCC: add device tree for Serval pcb105 board
>>> MSCC: Add device tree for Serval pcb106 board
>>> MSCC: Add board support for Serval SoC family.
>>>
>>
>> is this a resend or an extension of your v2 series?
>>
>> Normally a resend is not necessary and should be annotated accordingly.
>> If this is an update, then you should have sent it as a v3 with a proper
>> changelog.
>
> Well, it is none, it is a new patch series.
> The one in [1] is for ServalT while this patch series is for Serval.
> There are 2 different SoC families.
>
> [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
>>
>> --
>> - Daniel
>
ah sorry, but with the Patchwork font it's hard to note the difference
between "MSCC: Add Servalt SoC family" and "MSCC: Add Serval SoC family" ;)
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
2019-01-23 15:39 ` [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for " Horatiu Vultur
@ 2019-01-23 17:01 ` Daniel Schwierzeck
0 siblings, 0 replies; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 17:01 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> The Serval SoC family has 32 pins. Currently there is no
> support for Serval in Linux kernel.
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> ---
> drivers/pinctrl/mscc/Kconfig | 10 ++
> drivers/pinctrl/mscc/Makefile | 1 +
> drivers/pinctrl/mscc/pinctrl-serval.c | 233 ++++++++++++++++++++++++++++++++++
> 3 files changed, 244 insertions(+)
> create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c
>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/5] MSCC: Add support for Serval SoC family.
2019-01-23 15:39 ` [U-Boot] [PATCH 2/5] MSCC: Add support " Horatiu Vultur
@ 2019-01-23 17:04 ` Daniel Schwierzeck
0 siblings, 0 replies; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 17:04 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
> found in Microsemi Switches solution.
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> ---
> arch/mips/mach-mscc/Kconfig | 9 +
> arch/mips/mach-mscc/cpu.c | 2 +-
> arch/mips/mach-mscc/dram.c | 2 +-
> arch/mips/mach-mscc/include/mach/common.h | 5 +
> arch/mips/mach-mscc/include/mach/ddr.h | 20 +-
> arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++
> .../include/mach/serval/serval_devcpu_gcb.h | 21 ++
> .../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++
> .../include/mach/serval/serval_icpu_cfg.h | 314 +++++++++++++++++++++
> arch/mips/mach-mscc/reset.c | 25 +-
> include/configs/vcoreiii.h | 5 +-
> 11 files changed, 438 insertions(+), 14 deletions(-)
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family.
2019-01-23 15:39 ` [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family Horatiu Vultur
@ 2019-01-23 17:06 ` Daniel Schwierzeck
0 siblings, 0 replies; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 17:06 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> Add board support and configuration for Jaguar2 SoC family.
> The detection of the board type is based on the phy ids.
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> ---
> arch/mips/dts/Makefile | 1 +
> arch/mips/mach-mscc/Makefile | 1 +
> board/mscc/serval/Kconfig | 14 ++++++++
> board/mscc/serval/Makefile | 3 ++
> board/mscc/serval/serval.c | 74 +++++++++++++++++++++++++++++++++++++++++++
> configs/mscc_serval_defconfig | 62 ++++++++++++++++++++++++++++++++++++
> 6 files changed, 155 insertions(+)
> create mode 100644 board/mscc/serval/Kconfig
> create mode 100644 board/mscc/serval/Makefile
> create mode 100644 board/mscc/serval/serval.c
> create mode 100644 configs/mscc_serval_defconfig
>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
` (5 preceding siblings ...)
2019-01-23 16:38 ` [U-Boot] [PATCH 0/5] MSCC: Add " Daniel Schwierzeck
@ 2019-01-23 20:12 ` Daniel Schwierzeck
6 siblings, 0 replies; 13+ messages in thread
From: Daniel Schwierzeck @ 2019-01-23 20:12 UTC (permalink / raw)
To: u-boot
Am 23.01.19 um 16:39 schrieb Horatiu Vultur:
> This patch series adds support for MSCC Serval SoC family. In this
> family there are the following boards: pcb105 and pcb106.
>
> This is based off the patch series[1].
>
> [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html
>
> Horatiu Vultur (5):
> pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
> MSCC: Add support for Serval SoC family.
> MSCC: add device tree for Serval pcb105 board
> MSCC: Add device tree for Serval pcb106 board
> MSCC: Add board support for Serval SoC family.
>
> arch/mips/dts/Makefile | 1 +
> arch/mips/dts/mscc,serval.dtsi | 149 ++++++++++
> arch/mips/dts/serval_pcb105.dts | 56 ++++
> arch/mips/dts/serval_pcb106.dts | 56 ++++
> arch/mips/mach-mscc/Kconfig | 9 +
> arch/mips/mach-mscc/Makefile | 1 +
> arch/mips/mach-mscc/cpu.c | 2 +-
> arch/mips/mach-mscc/dram.c | 2 +-
> arch/mips/mach-mscc/include/mach/common.h | 5 +
> arch/mips/mach-mscc/include/mach/ddr.h | 20 +-
> arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++
> .../include/mach/serval/serval_devcpu_gcb.h | 21 ++
> .../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++
> .../include/mach/serval/serval_icpu_cfg.h | 314 +++++++++++++++++++++
> arch/mips/mach-mscc/reset.c | 25 +-
> board/mscc/serval/Kconfig | 14 +
> board/mscc/serval/Makefile | 3 +
> board/mscc/serval/serval.c | 74 +++++
> configs/mscc_serval_defconfig | 62 ++++
> drivers/pinctrl/mscc/Kconfig | 10 +
> drivers/pinctrl/mscc/Makefile | 1 +
> drivers/pinctrl/mscc/pinctrl-serval.c | 233 +++++++++++++++
> include/configs/vcoreiii.h | 5 +-
> 23 files changed, 1098 insertions(+), 14 deletions(-)
> create mode 100644 arch/mips/dts/mscc,serval.dtsi
> create mode 100644 arch/mips/dts/serval_pcb105.dts
> create mode 100644 arch/mips/dts/serval_pcb106.dts
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
> create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
> create mode 100644 board/mscc/serval/Kconfig
> create mode 100644 board/mscc/serval/Makefile
> create mode 100644 board/mscc/serval/serval.c
> create mode 100644 configs/mscc_serval_defconfig
> create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c
>
series applied to u-boot-mips, thanks.
--
- Daniel
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-01-23 20:12 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-23 15:39 [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for " Horatiu Vultur
2019-01-23 17:01 ` Daniel Schwierzeck
2019-01-23 15:39 ` [U-Boot] [PATCH 2/5] MSCC: Add support " Horatiu Vultur
2019-01-23 17:04 ` Daniel Schwierzeck
2019-01-23 15:39 ` [U-Boot] [PATCH 3/5] MSCC: add device tree for Serval pcb105 board Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 4/5] MSCC: Add device tree for Serval pcb106 board Horatiu Vultur
2019-01-23 15:39 ` [U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family Horatiu Vultur
2019-01-23 17:06 ` Daniel Schwierzeck
2019-01-23 16:38 ` [U-Boot] [PATCH 0/5] MSCC: Add " Daniel Schwierzeck
2019-01-23 16:47 ` Horatiu Vultur
2019-01-23 16:58 ` Daniel Schwierzeck
2019-01-23 20:12 ` Daniel Schwierzeck
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