From: Lukasz Luba <l.luba@partner.samsung.com> To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba <l.luba@partner.samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 1 Feb 2019 17:46:47 +0100 [thread overview] Message-ID: <1549039612-28905-4-git-send-email-l.luba@partner.samsung.com> (raw) In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f1a4f56..1fc5152 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1323,6 +1323,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1465,7 +1476,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Lukasz Luba <l.luba@partner.samsung.com> To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, krzk@kernel.org, Lukasz Luba <l.luba@partner.samsung.com>, cw00.choi@samsung.com, kyungmin.park@samsung.com, kgene@kernel.org, myungjoo.ham@samsung.com, s.nawrocki@samsung.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com Subject: [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 1 Feb 2019 17:46:47 +0100 [thread overview] Message-ID: <1549039612-28905-4-git-send-email-l.luba@partner.samsung.com> (raw) In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f1a4f56..1fc5152 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1323,6 +1323,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1465,7 +1476,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-01 16:47 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20190201164717eucas1p2ddf83cd5b7a5f53fdb866eeb8e991c71@eucas1p2.samsung.com> 2019-02-01 16:46 ` [PATCH v4 0/8] Exynos5 Dynamic Memory Controller driver Lukasz Luba [not found] ` <CGME20190201164718eucas1p1bca3a199d60e109e1da654d8afff2a47@eucas1p1.samsung.com> 2019-02-01 16:46 ` [PATCH v4 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-13 21:07 ` Rob Herring 2019-02-13 21:07 ` Rob Herring [not found] ` <CGME20190201164719eucas1p2091c6d41a6cc21a3d36081daf4bc8267@eucas1p2.samsung.com> 2019-02-01 16:46 ` [PATCH v4 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-03 9:56 ` Chanwoo Choi 2019-02-03 9:56 ` Chanwoo Choi 2019-02-11 11:11 ` Lukasz Luba 2019-02-11 11:11 ` Lukasz Luba 2019-02-12 6:04 ` Chanwoo Choi 2019-02-12 6:04 ` Chanwoo Choi [not found] ` <CGME20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5@eucas1p1.samsung.com> 2019-02-01 16:46 ` Lukasz Luba [this message] 2019-02-01 16:46 ` [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba [not found] ` <CGME20190201164720eucas1p13aac6550399d240b261a2cbe489d3dfc@eucas1p1.samsung.com> 2019-02-01 16:46 ` [PATCH v4 4/8] drivers: devfreq: add DMC driver for Exynos5422 Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-03 12:23 ` Chanwoo Choi 2019-02-03 12:23 ` Chanwoo Choi 2019-03-06 13:44 ` Sylwester Nawrocki 2019-03-06 13:44 ` Sylwester Nawrocki 2019-03-07 1:10 ` Chanwoo Choi 2019-03-07 1:10 ` Chanwoo Choi 2019-03-07 8:41 ` Sylwester Nawrocki 2019-03-07 8:41 ` Sylwester Nawrocki [not found] ` <CGME20190201164720eucas1p1ae770f7981fa09016b69ca7265e820c7@eucas1p1.samsung.com> 2019-02-01 16:46 ` [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-03 12:28 ` Chanwoo Choi 2019-02-03 12:28 ` Chanwoo Choi [not found] ` <CGME20190201164721eucas1p286976bab0cc9e06c2cf74a0eaa20144e@eucas1p2.samsung.com> 2019-02-01 16:46 ` [PATCH v4 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-08 8:14 ` Krzysztof Kozlowski 2019-02-08 8:14 ` Krzysztof Kozlowski [not found] ` <CGME20190201164722eucas1p1b619d939e0f93ddb9ee1af7306e7cf67@eucas1p1.samsung.com> 2019-02-01 16:46 ` [PATCH v4 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba [not found] ` <CGME20190201164723eucas1p1ec009489584e1c85fd0d62270796e003@eucas1p1.samsung.com> 2019-02-01 16:46 ` [PATCH v4 8/8] ARM: exynos_defconfig: enable DMC driver Lukasz Luba 2019-02-01 16:46 ` Lukasz Luba 2019-02-08 8:15 ` Krzysztof Kozlowski 2019-02-08 8:15 ` Krzysztof Kozlowski
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