* [PATCH v2 RESEND 0/2] Support 64 bpp half float formats
@ 2019-02-01 17:43 Kevin Strasser
2019-02-01 17:43 ` [PATCH v2 RESEND 1/2] drm/fourcc: Add " Kevin Strasser
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Kevin Strasser @ 2019-02-01 17:43 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
This series defines new formats and adds implementation to the i915 driver.
Since posting v1 I have removed the pixel normalize property, as it's not needed
for basic functionality. Also, I have been working on adding support to
userspace, but we can't land any patches until drm_fourcc.h has been updated
here.
I have submitted a series to Mesa to make use of the RGBA ordered formats:
https://patchwork.freedesktop.org/series/54759/
My igt branch is reworked to drop usage of pixel normalize and includes use
of f16c intrinsics to speed up conversion:
https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16
I also have a libdrm branch with fp16 coverage added to modetest:
https://gitlab.freedesktop.org/strassek/drm/commits/fp16
To serve as a smoke test of the whole stack I have a modified version of
kmscube:
https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16
Kevin Strasser (2):
drm/fourcc: Add 64 bpp half float formats
drm/i915/icl: Implement half float formats
drivers/gpu/drm/drm_fourcc.c | 4 +++
drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 67 ++++++++++++++++++++++++++++++++----
include/uapi/drm/drm_fourcc.h | 11 ++++++
4 files changed, 98 insertions(+), 6 deletions(-)
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 RESEND 1/2] drm/fourcc: Add 64 bpp half float formats
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
@ 2019-02-01 17:43 ` Kevin Strasser
2019-02-01 20:26 ` Ville Syrjälä
2019-02-01 17:43 ` [PATCH v2 RESEND 2/2] drm/i915/icl: Implement " Kevin Strasser
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Kevin Strasser @ 2019-02-01 17:43 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter, Tina Zhang, Uma Shankar
Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.
This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
https://patchwork.kernel.org/patch/10072545/
v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..c866452 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 91d08a2..c516b40 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
2019-02-01 17:43 ` [PATCH v2 RESEND 1/2] drm/fourcc: Add " Kevin Strasser
@ 2019-02-01 17:43 ` Kevin Strasser
2019-02-01 20:40 ` Ville Syrjälä
2019-02-01 17:59 ` ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev3) Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Kevin Strasser @ 2019-02-01 17:43 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter, Uma Shankar
64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
* 90/270 rotation not supported
* Yf Tiling not supported
* Frame Buffer Compression not supported
* Color Keying not supported
v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 67 ++++++++++++++++++++++++++++++++----
2 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a6d8985..f413ccd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR16161616F;
+ else
+ return DRM_FORMAT_XBGR16161616F;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB16161616F;
+ else
+ return DRM_FORMAT_XRGB16161616F;
+ }
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F;
default:
MISSING_CASE(pixel_format);
}
@@ -5069,6 +5087,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index cd42e81..97f9d05 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
/*
* 90/270 is not allowed with RGB64 16:16:16:16 and
* Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
- * TBD: Add RGB64 case once its added in supported format
- * list.
*/
switch (fb->format->format) {
case DRM_FORMAT_RGB565:
@@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
break;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
drm_get_format_name(fb->format->format,
&format_name));
@@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t icl_hdr_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
+static const uint32_t icl_hdr_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
return true;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
- formats = skl_planar_formats;
- num_formats = ARRAY_SIZE(skl_planar_formats);
+ if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
+ formats = icl_hdr_planar_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+ } else {
+ formats = skl_planar_formats;
+ num_formats = ARRAY_SIZE(skl_planar_formats);
+ }
} else {
- formats = skl_plane_formats;
- num_formats = ARRAY_SIZE(skl_plane_formats);
+ if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
+ formats = icl_hdr_plane_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+ } else {
+ formats = skl_plane_formats;
+ num_formats = ARRAY_SIZE(skl_plane_formats);
+ }
}
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev3)
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
2019-02-01 17:43 ` [PATCH v2 RESEND 1/2] drm/fourcc: Add " Kevin Strasser
2019-02-01 17:43 ` [PATCH v2 RESEND 2/2] drm/i915/icl: Implement " Kevin Strasser
@ 2019-02-01 17:59 ` Patchwork
2019-02-01 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-02-01 19:59 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-02-01 17:59 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb513dd0a6fe drm/fourcc: Add 64 bpp half float formats
-:39: WARNING:LONG_LINE: line over 100 characters
#39: FILE: drivers/gpu/drm/drm_fourcc.c:201:
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:40: WARNING:LONG_LINE: line over 100 characters
#40: FILE: drivers/gpu/drm/drm_fourcc.c:202:
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/drm_fourcc.c:203:
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:42: WARNING:LONG_LINE: line over 100 characters
#42: FILE: drivers/gpu/drm/drm_fourcc.c:204:
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:59: WARNING:LONG_LINE_COMMENT: line over 100 characters
#59: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
-:60: WARNING:LONG_LINE_COMMENT: line over 100 characters
#60: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
-:62: WARNING:LONG_LINE_COMMENT: line over 100 characters
#62: FILE: include/uapi/drm/drm_fourcc.h:155:
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
-:63: WARNING:LONG_LINE_COMMENT: line over 100 characters
#63: FILE: include/uapi/drm/drm_fourcc.h:156:
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
total: 0 errors, 8 warnings, 0 checks, 27 lines checked
076507575eff drm/i915/icl: Implement half float formats
-:103: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#103: FILE: drivers/gpu/drm/i915/intel_sprite.c:1779:
+static const uint32_t icl_hdr_plane_formats[] = {
-:122: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#122: FILE: drivers/gpu/drm/i915/intel_sprite.c:1798:
+static const uint32_t icl_hdr_planar_formats[] = {
total: 0 errors, 0 warnings, 2 checks, 138 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for Support 64 bpp half float formats (rev3)
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
` (2 preceding siblings ...)
2019-02-01 17:59 ` ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev3) Patchwork
@ 2019-02-01 18:20 ` Patchwork
2019-02-01 19:59 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-02-01 18:20 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526 -> Patchwork_12120
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53212/revisions/3/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12120:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-y}: NOTRUN -> {SKIP} +1
Known issues
------------
Here are the changes found in Patchwork_12120 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
Participating hosts (48 -> 44)
------------------------------
Additional (2): fi-icl-y fi-ivb-3520m
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-snb-2600
Build changes
-------------
* Linux: CI_DRM_5526 -> Patchwork_12120
CI_DRM_5526: 482f9674140cbe8fddb18714bb95028cd9bfc1d1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12120: 076507575effcb745ac8e08f84601405fe1a2915 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
076507575eff drm/i915/icl: Implement half float formats
bb513dd0a6fe drm/fourcc: Add 64 bpp half float formats
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12120/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for Support 64 bpp half float formats (rev3)
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
` (3 preceding siblings ...)
2019-02-01 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-02-01 19:59 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-02-01 19:59 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526_full -> Patchwork_12120_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12120_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] / [fdo#105602]
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: NOTRUN -> FAIL [fdo#103166] +2
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +7
* igt@kms_vblank@pipe-b-query-forked-hang:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
#### Possible fixes ####
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: FAIL [fdo#105454] / [fdo#106509] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
#### Warnings ####
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-apl: DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145] -> FAIL [fdo#108145]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5526 -> Patchwork_12120
CI_DRM_5526: 482f9674140cbe8fddb18714bb95028cd9bfc1d1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12120: 076507575effcb745ac8e08f84601405fe1a2915 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12120/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 RESEND 1/2] drm/fourcc: Add 64 bpp half float formats
2019-02-01 17:43 ` [PATCH v2 RESEND 1/2] drm/fourcc: Add " Kevin Strasser
@ 2019-02-01 20:26 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2019-02-01 20:26 UTC (permalink / raw)
To: Kevin Strasser; +Cc: David Airlie, Daniel Vetter, intel-gfx, dri-devel
On Fri, Feb 01, 2019 at 09:43:39AM -0800, Kevin Strasser wrote:
> Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
> formatted in IEEE-754 half-precision float (binary16) 1:5:10
> MSb-sign:exponent:fraction form.
>
> This patch attempts to address the feedback provided when 2 of these
> formats were previosly proposed:
> https://patchwork.kernel.org/patch/10072545/
>
> v2:
> - Fixed cpp (Ville)
> - Added detail pixel formatting (Ville)
> - Ordered formats in header (Ville)
>
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> Cc: Tina Zhang <tina.zhang@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
This lgtm:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03..c866452 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 91d08a2..c516b40 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -144,6 +144,17 @@ extern "C" {
> #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
> #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
>
> +/*
> + * Floating point 64bpp RGB
> + * IEEE 754-2008 binary16 half-precision float
> + * [15:0] sign:exponent:mantissa 1:5:10
> + */
> +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
> +
> +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
> +
> /* packed YCbCr */
> #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
> #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
> --
> 2.7.4
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
2019-02-01 17:43 ` [PATCH v2 RESEND 2/2] drm/i915/icl: Implement " Kevin Strasser
@ 2019-02-01 20:40 ` Ville Syrjälä
2019-02-01 21:38 ` Strasser, Kevin
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2019-02-01 20:40 UTC (permalink / raw)
To: Kevin Strasser
Cc: David Airlie, Daniel Vetter, intel-gfx, dri-devel, Uma Shankar
On Fri, Feb 01, 2019 at 09:43:40AM -0800, Kevin Strasser wrote:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
> * 90/270 rotation not supported
> * Yf Tiling not supported
> * Frame Buffer Compression not supported
> * Color Keying not supported
>
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
>
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 67 ++++++++++++++++++++++++++++++++----
> 2 files changed, 83 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a6d8985..f413ccd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XRGB_16161616F:
> + if (rgb_order) {
> + if (alpha)
> + return DRM_FORMAT_ABGR16161616F;
> + else
> + return DRM_FORMAT_XBGR16161616F;
> + } else {
> + if (alpha)
> + return DRM_FORMAT_ARGB16161616F;
> + else
> + return DRM_FORMAT_XRGB16161616F;
> + }
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -5069,6 +5087,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index cd42e81..97f9d05 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> /*
> * 90/270 is not allowed with RGB64 16:16:16:16 and
> * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
> - * TBD: Add RGB64 case once its added in supported format
> - * list.
> */
> switch (fb->format->format) {
> case DRM_FORMAT_RGB565:
> @@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> break;
> /* fall through */
> case DRM_FORMAT_C8:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
> drm_get_format_name(fb->format->format,
> &format_name));
> @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
> DRM_FORMAT_NV12,
> };
>
> +static const uint32_t icl_hdr_plane_formats[] = {
Please switch to u32 & co. We recently had a mass conversion in the
driver.
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
I just noticed that icl should also support alpha for 10bpc. But that's
not relevant for this patch.
> + DRM_FORMAT_XRGB16161616F,
> + DRM_FORMAT_XBGR16161616F,
> + DRM_FORMAT_ARGB16161616F,
> + DRM_FORMAT_ABGR16161616F,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> +};
> +
> +static const uint32_t icl_hdr_planar_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XRGB16161616F,
> + DRM_FORMAT_XBGR16161616F,
> + DRM_FORMAT_ARGB16161616F,
> + DRM_FORMAT_ABGR16161616F,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
> +
> static const u64 skl_plane_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> return true;
> /* fall through */
> case DRM_FORMAT_C8:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> if (modifier == DRM_FORMAT_MOD_LINEAR ||
> modifier == I915_FORMAT_MOD_X_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED)
> @@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->update_slave = icl_update_slave;
>
> if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> - formats = skl_planar_formats;
> - num_formats = ARRAY_SIZE(skl_planar_formats);
> + if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
is_hdr_plane() is around now, please use it.
With that and the u32 this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + formats = icl_hdr_planar_formats;
> + num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
> + } else {
> + formats = skl_planar_formats;
> + num_formats = ARRAY_SIZE(skl_planar_formats);
> + }
> } else {
> - formats = skl_plane_formats;
> - num_formats = ARRAY_SIZE(skl_plane_formats);
> + if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
> + formats = icl_hdr_plane_formats;
> + num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
> + } else {
> + formats = skl_plane_formats;
> + num_formats = ARRAY_SIZE(skl_plane_formats);
> + }
> }
>
> plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> --
> 2.7.4
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
2019-02-01 20:40 ` Ville Syrjälä
@ 2019-02-01 21:38 ` Strasser, Kevin
2019-02-04 21:24 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: Strasser, Kevin @ 2019-02-01 21:38 UTC (permalink / raw)
To: Ville Syrjälä
Cc: David Airlie, Daniel Vetter, intel-gfx, dri-devel, Shankar, Uma
Ville Syrjälä wrote:
> > @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
> > DRM_FORMAT_NV12,
> > };
> >
> > +static const uint32_t icl_hdr_plane_formats[] = {
>
> Please switch to u32 & co. We recently had a mass conversion in the
> driver.
Will do. Looks like the CI caught that too.
> > static const u64 skl_plane_format_modifiers_noccs[] = {
> > I915_FORMAT_MOD_Yf_TILED,
> > I915_FORMAT_MOD_Y_TILED,
> > @@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct
> > drm_plane *_plane,
> > return true;
> > /* fall through */
> > case DRM_FORMAT_C8:
> > + case DRM_FORMAT_XBGR16161616F:
> > + case DRM_FORMAT_ABGR16161616F:
> > + case DRM_FORMAT_XRGB16161616F:
> > + case DRM_FORMAT_ARGB16161616F:
> > if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > modifier == I915_FORMAT_MOD_X_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED)
> > @@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private
> > *dev_priv,
> > plane->update_slave = icl_update_slave;
> >
> > if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> > - formats = skl_planar_formats;
> > - num_formats = ARRAY_SIZE(skl_planar_formats);
> > + if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
>
> is_hdr_plane() is around now, please use it.
I don't think I can use icl_is_hdr_plane here without some refactoring. It
requires the plane->base to be initialized through drm_universal_plane_init,
which depends on formats/num_formats pointers to be already set.
Thanks,
Kevin
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
2019-02-01 21:38 ` Strasser, Kevin
@ 2019-02-04 21:24 ` Ville Syrjälä
2019-02-04 22:16 ` Strasser, Kevin
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2019-02-04 21:24 UTC (permalink / raw)
To: Strasser, Kevin; +Cc: David Airlie, Daniel Vetter, intel-gfx, dri-devel
On Fri, Feb 01, 2019 at 09:38:57PM +0000, Strasser, Kevin wrote:
> Ville Syrjälä wrote:
> > > @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
> > > DRM_FORMAT_NV12,
> > > };
> > >
> > > +static const uint32_t icl_hdr_plane_formats[] = {
> >
> > Please switch to u32 & co. We recently had a mass conversion in the
> > driver.
>
> Will do. Looks like the CI caught that too.
>
> > > static const u64 skl_plane_format_modifiers_noccs[] = {
> > > I915_FORMAT_MOD_Yf_TILED,
> > > I915_FORMAT_MOD_Y_TILED,
> > > @@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct
> > > drm_plane *_plane,
> > > return true;
> > > /* fall through */
> > > case DRM_FORMAT_C8:
> > > + case DRM_FORMAT_XBGR16161616F:
> > > + case DRM_FORMAT_ABGR16161616F:
> > > + case DRM_FORMAT_XRGB16161616F:
> > > + case DRM_FORMAT_ARGB16161616F:
> > > if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > modifier == I915_FORMAT_MOD_X_TILED ||
> > > modifier == I915_FORMAT_MOD_Y_TILED)
> > > @@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private
> > > *dev_priv,
> > > plane->update_slave = icl_update_slave;
> > >
> > > if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> > > - formats = skl_planar_formats;
> > > - num_formats = ARRAY_SIZE(skl_planar_formats);
> > > + if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
> >
> > is_hdr_plane() is around now, please use it.
>
> I don't think I can use icl_is_hdr_plane here without some refactoring. It
> requires the plane->base to be initialized through drm_universal_plane_init,
> which depends on formats/num_formats pointers to be already set.
Hmm. We should probably just convert it into
icl_is_hdr_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id);
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
2019-02-04 21:24 ` Ville Syrjälä
@ 2019-02-04 22:16 ` Strasser, Kevin
0 siblings, 0 replies; 11+ messages in thread
From: Strasser, Kevin @ 2019-02-04 22:16 UTC (permalink / raw)
To: Ville Syrjälä
Cc: David Airlie, Daniel Vetter, intel-gfx, dri-devel, Shankar, Uma
Ville Syrjälä wrote:
> Kevin Strasser wrote:
> > Ville Syrjälä wrote:
> > > is_hdr_plane() is around now, please use it.
> >
> > I don't think I can use icl_is_hdr_plane here without some refactoring. It
> > requires the plane->base to be initialized through drm_universal_plane_init,
> > which depends on formats/num_formats pointers to be already set.
>
> Hmm. We should probably just convert it into
>
> icl_is_hdr_plane(struct drm_i915_private *dev_priv,
> enum plane_id plane_id);
That sounds reasonable, I'll include this in v3.
Thanks,
Kevin
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-02-04 22:16 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-01 17:43 [PATCH v2 RESEND 0/2] Support 64 bpp half float formats Kevin Strasser
2019-02-01 17:43 ` [PATCH v2 RESEND 1/2] drm/fourcc: Add " Kevin Strasser
2019-02-01 20:26 ` Ville Syrjälä
2019-02-01 17:43 ` [PATCH v2 RESEND 2/2] drm/i915/icl: Implement " Kevin Strasser
2019-02-01 20:40 ` Ville Syrjälä
2019-02-01 21:38 ` Strasser, Kevin
2019-02-04 21:24 ` Ville Syrjälä
2019-02-04 22:16 ` Strasser, Kevin
2019-02-01 17:59 ` ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev3) Patchwork
2019-02-01 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-02-01 19:59 ` ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.