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* [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs
@ 2019-02-04 10:58 Fabien Parent
  2019-02-04 10:58 ` [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support Fabien Parent
                   ` (5 more replies)
  0 siblings, 6 replies; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

This patch series adds basic boot support on eMMC for the MediaTek MT8516 SoC
based boards. This series adds the clock, pinctrl drivers and the SoC
initialization code.

Fabien Parent (6):
  mmc: mtk-sd: add source_cg clock support
  mmc: mtk-sd: add support for MT8516
  clk: mediatek: add support for CLK_GATE_SETCLR_INV flag
  clk: mediatek: add driver for MT8516
  pinctrl: add driver for MT8516
  ARM: MediaTek: Add support for MT8516 SoC

 arch/arm/dts/mt8516.dtsi                  | 142 ++++
 arch/arm/mach-mediatek/Kconfig            |  10 +
 arch/arm/mach-mediatek/Makefile           |   1 +
 arch/arm/mach-mediatek/mt8516/Makefile    |   3 +
 arch/arm/mach-mediatek/mt8516/init.c      | 112 +++
 drivers/clk/mediatek/Makefile             |   1 +
 drivers/clk/mediatek/clk-mt8516.c         | 802 ++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.c            |   3 +
 drivers/mmc/mtk-sd.c                      |  18 +
 drivers/pinctrl/mediatek/Kconfig          |   4 +
 drivers/pinctrl/mediatek/Makefile         |   1 +
 drivers/pinctrl/mediatek/pinctrl-mt8516.c | 391 +++++++++++
 include/dt-bindings/clock/mt8516-clk.h    | 251 +++++++
 13 files changed, 1739 insertions(+)
 create mode 100644 arch/arm/dts/mt8516.dtsi
 create mode 100644 arch/arm/mach-mediatek/mt8516/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt8516/init.c
 create mode 100644 drivers/clk/mediatek/clk-mt8516.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
 create mode 100644 include/dt-bindings/clock/mt8516-clk.h

-- 
2.20.1

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-11  3:46   ` Ryder Lee
  2019-02-04 10:58 ` [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516 Fabien Parent
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/mmc/mtk-sd.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index d3f0778368..8573ea7430 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -247,7 +247,9 @@ struct msdc_host {
 	struct msdc_compatible *dev_comp;
 
 	struct clk src_clk;	/* for SD/MMC bus clock */
+	struct clk src_clk_cg;	/* optional, MSDC source clock control gate */
 	struct clk h_clk;	/* MSDC core clock */
+	bool has_src_clk_cg;
 
 	u32 src_clk_freq;	/* source clock */
 	u32 mclk;		/* mmc framework required bus clock */
@@ -1269,6 +1271,8 @@ static void msdc_ungate_clock(struct msdc_host *host)
 {
 	clk_enable(&host->src_clk);
 	clk_enable(&host->h_clk);
+	if (host->has_src_clk_cg)
+		clk_enable(&host->src_clk_cg);
 }
 
 static int msdc_drv_probe(struct udevice *dev)
@@ -1332,6 +1336,10 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
+	ret = clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
+	if (!ret)
+		host->has_src_clk_cg = true;
+
 #if IS_ENABLED(DM_GPIO)
 	gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
 	gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
  2019-02-04 10:58 ` [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-11  2:52   ` Ryder Lee
  2019-02-04 10:58 ` [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag Fabien Parent
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Add config for handling MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/mmc/mtk-sd.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 8573ea7430..9373481f50 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1384,8 +1384,18 @@ static const struct msdc_compatible mt7623_compat = {
 	.enhance_rx = false
 };
 
+static const struct msdc_compatible mt8516_compat = {
+	.clk_div_bits = 12,
+	.pad_tune0 = true,
+	.async_fifo = true,
+	.data_tune = true,
+	.busy_check = true,
+	.stop_clk_fix = true,
+};
+
 static const struct udevice_id msdc_ids[] = {
 	{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
+	{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
 	{}
 };
 
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
  2019-02-04 10:58 ` [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support Fabien Parent
  2019-02-04 10:58 ` [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516 Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-11  2:54   ` Ryder Lee
  2019-02-04 10:58 ` [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516 Fabien Parent
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Add the implementation for the CLK_GATE_SETCLR_INV flag.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/clk/mediatek/clk-mtk.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 870b14ed8b..725be031b8 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -390,6 +390,9 @@ static int mtk_clk_gate_enable(struct clk *clk)
 	case CLK_GATE_SETCLR:
 		writel(bit, priv->base + gate->regs->clr_ofs);
 		break;
+	case CLK_GATE_SETCLR_INV:
+		writel(bit, priv->base + gate->regs->set_ofs);
+		break;
 	case CLK_GATE_NO_SETCLR_INV:
 		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
 		break;
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
                   ` (2 preceding siblings ...)
  2019-02-04 10:58 ` [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-11  3:20   ` Ryder Lee
  2019-02-04 10:58 ` [U-Boot] [PATCH 5/6] pinctrl: " Fabien Parent
  2019-02-04 10:58 ` [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8516.c      | 802 +++++++++++++++++++++++++
 include/dt-bindings/clock/mt8516-clk.h | 251 ++++++++
 3 files changed, 1054 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8516.c
 create mode 100644 include/dt-bindings/clock/mt8516-clk.h

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0632dc87b6..a47a5bdbc2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
 # SoC Drivers
 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 0000000000..8963449bb9
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX			(1502UL * MHZ)
+#define MT8516_CON0_RST_BAR		BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT8516_CON0_RST_BAR,			\
+		.fmax = MT8516_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+		21, 0x0104, 24, 0x0104, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+		HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+	PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+		HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+	PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+		21, 0x0164, 24, 0x0164, 0),
+	PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+		31, 0x0180, 1, 0x0184, 0),
+	PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+		31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+	FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+	FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+	FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+	FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+	FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+	FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+	FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+	FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+	FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+	FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+	FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+	FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+	FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+	FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+	FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+	FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+	FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+	FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+	FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+	FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+	FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+	FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+	FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+	FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+	FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+	FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+	FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+	CLK_TOP_GFMUX_EMI1X_SEL,
+	CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D10,
+};
+
+static const int csw_mux_mfg_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MMPLL380M,
+};
+
+static const int msdc0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2,
+};
+
+static const int pwm_mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+};
+
+static const int uart1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2,
+};
+
+static const int spm_52m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int pmicspi_parents[] = {
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_USB_PHY48M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D22,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+	CLK_TOP_AHB_INFRA_SEL,
+	CLK_TOP_NFI1X,
+};
+
+static const int mfg_mm_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CSW_MUX_MFG_SEL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D3,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D14
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int axi_mfg_in_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MMPLL380M,
+};
+
+static const int slow_mfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int aud1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_RG_APLL1_D2_EN,
+	CLK_TOP_RG_APLL1_D4_EN,
+	CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_RG_APLL2_D2_EN,
+	CLK_TOP_RG_APLL2_D4_EN,
+	CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+	CLK_TOP_RG_AUD1,
+	CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_NFI2X_PAD_SEL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_MUX_SEL0 */
+	MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+	MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+	MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+	MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+	MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+	MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+	MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+	MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+	MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+	MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+	MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+	MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+	MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+	/* CLK_MUX_SEL1 */
+	MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+	MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+	MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+	MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+	MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+	/* CLK_MUX_SEL8 */
+	MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+	MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+	MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+	MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+	MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+	MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+	MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+	MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+	MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+	MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+	/* CLK_MUX_SEL9 */
+	MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+	MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+	MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+	MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+	MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+	MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+	MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+	/* CLK_MUX_SEL13 */
+	MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+	MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+	MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+	MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+	MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+	MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+	MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+	MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x80,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x54,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+	.set_ofs = 0x6c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xb0,
+	.sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xb4,
+	.sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+	.set_ofs = 0x44,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x44,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top0_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP1(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top1_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top2_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2_I(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top2_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP3(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top3_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP4_I(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top4_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5(_id, _parent, _shift) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &top5_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+	GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
+	GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+	GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+	GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+	GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+	GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+	GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+	GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+	GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+	GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+	GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+	GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+	GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+	GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+	GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+	GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+	GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+	GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+	GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+	GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+	GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+	GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+	GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+	GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+	GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+	GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+	GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+	GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+	GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+	/* TOP2 */
+	GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+	GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+	GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+	GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
+	GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+	GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+	GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+	GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+	GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+	GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+	GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+	GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+	GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+	GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+	GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+	GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+	GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+	GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+	GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+	GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+	GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+	GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+	GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+	GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+	GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+	GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+	/* TOP3 */
+	GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+	GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+	GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+	GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
+	GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
+	GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+	GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+	GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+	GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+	GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+	GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+	GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+	GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+	/* TOP4 */
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+	/* TOP5 */
+	GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+	GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+	GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+	GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+	GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_DMPLL,
+	.muxes_offs = CLK_TOP_UART0_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8516-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8516-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+	{ .compatible = "mediatek,mt8516-topckgen-cg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8516-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_apmixed_compat,
+	.probe = mt8516_apmixedsys_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8516-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_topckgen_compat,
+	.probe = mt8516_topckgen_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+	.name = "mt8516-topckgen-cg",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_topckgen_cg_compat,
+	.probe = mt8516_topckgen_cg_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000000..b62a971c59
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIVPLL		2
+#define CLK_APMIXED_MMPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_NR_CLK		6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL		0
+#define CLK_TOP_I2S_INFRA_BCK		1
+#define CLK_TOP_MEMPLL			2
+#define CLK_TOP_DMPLL			3
+#define CLK_TOP_MAINPLL_D2		4
+#define CLK_TOP_MAINPLL_D4		5
+#define CLK_TOP_MAINPLL_D8		6
+#define CLK_TOP_MAINPLL_D16		7
+#define CLK_TOP_MAINPLL_D11		8
+#define CLK_TOP_MAINPLL_D22		9
+#define CLK_TOP_MAINPLL_D3		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D12		12
+#define CLK_TOP_MAINPLL_D5		13
+#define CLK_TOP_MAINPLL_D10		14
+#define CLK_TOP_MAINPLL_D20		15
+#define CLK_TOP_MAINPLL_D40		16
+#define CLK_TOP_MAINPLL_D7		17
+#define CLK_TOP_MAINPLL_D14		18
+#define CLK_TOP_UNIVPLL_D2		19
+#define CLK_TOP_UNIVPLL_D4		20
+#define CLK_TOP_UNIVPLL_D8		21
+#define CLK_TOP_UNIVPLL_D16		22
+#define CLK_TOP_UNIVPLL_D3		23
+#define CLK_TOP_UNIVPLL_D6		24
+#define CLK_TOP_UNIVPLL_D12		25
+#define CLK_TOP_UNIVPLL_D24		26
+#define CLK_TOP_UNIVPLL_D5		27
+#define CLK_TOP_UNIVPLL_D20		28
+#define CLK_TOP_MMPLL380M		29
+#define CLK_TOP_MMPLL_D2		30
+#define CLK_TOP_MMPLL_200M		31
+#define CLK_TOP_USB_PHY48M		32
+#define CLK_TOP_APLL1			33
+#define CLK_TOP_APLL1_D2		34
+#define CLK_TOP_APLL1_D4		35
+#define CLK_TOP_APLL1_D8		36
+#define CLK_TOP_APLL2			37
+#define CLK_TOP_APLL2_D2		38
+#define CLK_TOP_APLL2_D4		39
+#define CLK_TOP_APLL2_D8		40
+#define CLK_TOP_CLK26M			41
+#define CLK_TOP_CLK26M_D2		42
+#define CLK_TOP_AHB_INFRA_D2		43
+#define CLK_TOP_NFI1X			44
+#define CLK_TOP_ETH_D2			45
+#define CLK_TOP_UART0_SEL		46
+#define CLK_TOP_GFMUX_EMI1X_SEL		47
+#define CLK_TOP_EMI_DDRPHY_SEL		48
+#define CLK_TOP_AHB_INFRA_SEL		49
+#define CLK_TOP_CSW_MUX_MFG_SEL		50
+#define CLK_TOP_MSDC0_SEL		51
+#define CLK_TOP_PWM_MM_SEL		52
+#define CLK_TOP_UART1_SEL		53
+#define CLK_TOP_MSDC1_SEL		54
+#define CLK_TOP_SPM_52M_SEL		55
+#define CLK_TOP_PMICSPI_SEL		56
+#define CLK_TOP_QAXI_AUD26M_SEL		57
+#define CLK_TOP_AUD_INTBUS_SEL		58
+#define CLK_TOP_NFI2X_PAD_SEL		59
+#define CLK_TOP_NFI1X_PAD_SEL		60
+#define CLK_TOP_MFG_MM_SEL		61
+#define CLK_TOP_DDRPHYCFG_SEL		62
+#define CLK_TOP_USB_78M_SEL		63
+#define CLK_TOP_SPINOR_SEL		64
+#define CLK_TOP_MSDC2_SEL		65
+#define CLK_TOP_ETH_SEL			66
+#define CLK_TOP_AXI_MFG_IN_SEL		67
+#define CLK_TOP_SLOW_MFG_SEL		68
+#define CLK_TOP_AUD1_SEL		69
+#define CLK_TOP_AUD2_SEL		70
+#define CLK_TOP_AUD_ENGEN1_SEL		71
+#define CLK_TOP_AUD_ENGEN2_SEL		72
+#define CLK_TOP_I2C_SEL			73
+#define CLK_TOP_AUD_I2S0_M_SEL		74
+#define CLK_TOP_AUD_I2S1_M_SEL		75
+#define CLK_TOP_AUD_I2S2_M_SEL		76
+#define CLK_TOP_AUD_I2S3_M_SEL		77
+#define CLK_TOP_AUD_I2S4_M_SEL		78
+#define CLK_TOP_AUD_I2S5_M_SEL		79
+#define CLK_TOP_AUD_SPDIF_B_SEL		80
+#define CLK_TOP_PWM_SEL			81
+#define CLK_TOP_SPI_SEL			82
+#define CLK_TOP_AUD_SPDIFIN_SEL		83
+#define CLK_TOP_UART2_SEL		84
+#define CLK_TOP_BSI_SEL			85
+#define CLK_TOP_DBG_ATCLK_SEL		86
+#define CLK_TOP_CSW_NFIECC_SEL		87
+#define CLK_TOP_NFIECC_SEL		88
+#define CLK_TOP_APLL12_CK_DIV0		89
+#define CLK_TOP_APLL12_CK_DIV1		90
+#define CLK_TOP_APLL12_CK_DIV2		91
+#define CLK_TOP_APLL12_CK_DIV3		92
+#define CLK_TOP_APLL12_CK_DIV4		93
+#define CLK_TOP_APLL12_CK_DIV4B		94
+#define CLK_TOP_APLL12_CK_DIV5		95
+#define CLK_TOP_APLL12_CK_DIV5B		96
+#define CLK_TOP_APLL12_CK_DIV6		97
+#define CLK_TOP_NR_CLK			98
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM			0
+#define CLK_TOP_MFG_MM			1
+#define CLK_TOP_SPM_52M			2
+#define CLK_TOP_THEM			3
+#define CLK_TOP_APDMA			4
+#define CLK_TOP_I2C0			5
+#define CLK_TOP_I2C1			6
+#define CLK_TOP_AUXADC1			7
+#define CLK_TOP_NFI			8
+#define CLK_TOP_NFIECC			9
+#define CLK_TOP_DEBUGSYS		10
+#define CLK_TOP_PWM			11
+#define CLK_TOP_UART0			12
+#define CLK_TOP_UART1			13
+#define CLK_TOP_BTIF			14
+#define CLK_TOP_USB			15
+#define CLK_TOP_FLASHIF_26M		16
+#define CLK_TOP_AUXADC2			17
+#define CLK_TOP_I2C2			18
+#define CLK_TOP_MSDC0			19
+#define CLK_TOP_MSDC1			20
+#define CLK_TOP_NFI2X			21
+#define CLK_TOP_PMICWRAP_AP		22
+#define CLK_TOP_SEJ			23
+#define CLK_TOP_MEMSLP_DLYER		24
+#define CLK_TOP_SPI			25
+#define CLK_TOP_APXGPT			26
+#define CLK_TOP_AUDIO			27
+#define CLK_TOP_PMICWRAP_MD		28
+#define CLK_TOP_PMICWRAP_CONN		29
+#define CLK_TOP_PMICWRAP_26M		30
+#define CLK_TOP_AUX_ADC			31
+#define CLK_TOP_AUX_TP			32
+#define CLK_TOP_MSDC2			33
+#define CLK_TOP_RBIST			34
+#define CLK_TOP_NFI_BUS			35
+#define CLK_TOP_GCE			36
+#define CLK_TOP_TRNG			37
+#define CLK_TOP_SEJ_13M			38
+#define CLK_TOP_AES			39
+#define CLK_TOP_PWM_B			40
+#define CLK_TOP_PWM1_FB			41
+#define CLK_TOP_PWM2_FB			42
+#define CLK_TOP_PWM3_FB			43
+#define CLK_TOP_PWM4_FB			44
+#define CLK_TOP_PWM5_FB			45
+#define CLK_TOP_USB_1P			46
+#define CLK_TOP_FLASHIF_FREERUN		47
+#define CLK_TOP_66M_ETH			48
+#define CLK_TOP_133M_ETH		49
+#define CLK_TOP_FETH_25M		50
+#define CLK_TOP_FETH_50M		51
+#define CLK_TOP_FLASHIF_AXI		52
+#define CLK_TOP_USBIF			53
+#define CLK_TOP_UART2			54
+#define CLK_TOP_BSI			55
+#define CLK_TOP_MSDC0_INFRA		56
+#define CLK_TOP_MSDC1_INFRA		57
+#define CLK_TOP_MSDC2_INFRA		58
+#define CLK_TOP_USB_78M			59
+#define CLK_TOP_RG_SPINOR		60
+#define CLK_TOP_RG_MSDC2		61
+#define CLK_TOP_RG_ETH			62
+#define CLK_TOP_RG_AXI_MFG		63
+#define CLK_TOP_RG_SLOW_MFG		64
+#define CLK_TOP_RG_AUD1			65
+#define CLK_TOP_RG_AUD2			66
+#define CLK_TOP_RG_AUD_ENGEN1		67
+#define CLK_TOP_RG_AUD_ENGEN2		68
+#define CLK_TOP_RG_I2C			69
+#define CLK_TOP_RG_PWM_INFRA		70
+#define CLK_TOP_RG_AUD_SPDIF_IN		71
+#define CLK_TOP_RG_UART2		72
+#define CLK_TOP_RG_BSI			73
+#define CLK_TOP_RG_DBG_ATCLK		74
+#define CLK_TOP_RG_NFIECC		75
+#define CLK_TOP_RG_APLL1_D2_EN		76
+#define CLK_TOP_RG_APLL1_D4_EN		77
+#define CLK_TOP_RG_APLL1_D8_EN		78
+#define CLK_TOP_RG_APLL2_D2_EN		79
+#define CLK_TOP_RG_APLL2_D4_EN		80
+#define CLK_TOP_RG_APLL2_D8_EN		81
+#define CLK_TOP_APLL12_DIV0		82
+#define CLK_TOP_APLL12_DIV1		83
+#define CLK_TOP_APLL12_DIV2		84
+#define CLK_TOP_APLL12_DIV3		85
+#define CLK_TOP_APLL12_DIV4		86
+#define CLK_TOP_APLL12_DIV4B		87
+#define CLK_TOP_APLL12_DIV5		88
+#define CLK_TOP_APLL12_DIV5B		89
+#define CLK_TOP_APLL12_DIV6		90
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL		0
+#define CLK_IFR_ETH_25M_SEL		1
+#define CLK_IFR_I2C0_SEL		2
+#define CLK_IFR_I2C1_SEL		3
+#define CLK_IFR_I2C2_SEL		4
+#define CLK_IFR_NR_CLK			5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE			0
+#define CLK_AUD_I2S			1
+#define CLK_AUD_22M			2
+#define CLK_AUD_24M			3
+#define CLK_AUD_INTDIR			4
+#define CLK_AUD_APLL2_TUNER		5
+#define CLK_AUD_APLL_TUNER		6
+#define CLK_AUD_HDMI			7
+#define CLK_AUD_SPDF			8
+#define CLK_AUD_ADC			9
+#define CLK_AUD_DAC			10
+#define CLK_AUD_DAC_PREDIS		11
+#define CLK_AUD_TML			12
+#define CLK_AUD_NR_CLK			13
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI			0
+#define CLK_MFG_BMEM			1
+#define CLK_MFG_BG3D			2
+#define CLK_MFG_B26M			3
+#define CLK_MFG_NR_CLK			4
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 5/6] pinctrl: add driver for MT8516
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
                   ` (3 preceding siblings ...)
  2019-02-04 10:58 ` [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516 Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-11  2:51   ` Ryder Lee
  2019-02-04 10:58 ` [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/Kconfig          |   4 +
 drivers/pinctrl/mediatek/Makefile         |   1 +
 drivers/pinctrl/mediatek/pinctrl-mt8516.c | 391 ++++++++++++++++++++++
 3 files changed, 396 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 1bd9a925a5..9930ca1faf 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,4 +12,8 @@ config PINCTRL_MT7629
 	bool "MT7629 SoC pinctrl driver"
 	select PINCTRL_MTK
 
+config PINCTRL_MT8516
+	bool "MT8516 SoC pinctrl driver"
+	select PINCTRL_MTK
+
 endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index f6ef3627e8..c4f29088d2 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
 # SoC Drivers
 obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
 obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
new file mode 100644
index 0000000000..17083e9aa3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)	\
+	PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit,	\
+		       _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
+	PIN_FIELD(0, 124, 0x300, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
+	PIN_FIELD(0, 124, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
+	PIN_FIELD(0, 124, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
+	PIN_FIELD(0, 124, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
+	PIN_FIELD(0, 6, 0x900, 0x10, 2, 1),
+	PIN_FIELD(7, 10, 0x900, 0x10, 3, 1),
+	PIN_FIELD(11, 13, 0x900, 0x10, 12, 1),
+	PIN_FIELD(14, 17, 0x900, 0x10, 13, 1),
+	PIN_FIELD(18, 20, 0x910, 0x10, 10, 1),
+	PIN_FIELD(21, 23, 0x900, 0x10, 13, 1),
+	PIN_FIELD(24, 25, 0x900, 0x10, 12, 1),
+	PIN_FIELD(26, 30, 0x900, 0x10, 0, 1),
+	PIN_FIELD(31, 33, 0x900, 0x10, 1, 1),
+	PIN_FIELD(34, 39, 0x900, 0x10, 2, 1),
+	PIN_FIELD(40, 40, 0x910, 0x10, 11, 1),
+	PIN_FIELD(41, 43, 0x900, 0x10, 10, 1),
+	PIN_FIELD(44, 47, 0x900, 0x10, 11, 1),
+	PIN_FIELD(48, 51, 0x900, 0x10, 14, 1),
+	PIN_FIELD(52, 53, 0x910, 0x10, 0, 1),
+	PIN_FIELD(54, 54, 0x910, 0x10, 2, 1),
+	PIN_FIELD(55, 57, 0x910, 0x10, 4, 1),
+	PIN_FIELD(58, 59, 0x900, 0x10, 15, 1),
+	PIN_FIELD(60, 61, 0x910, 0x10, 1, 1),
+	PIN_FIELD(62, 65, 0x910, 0x10, 5, 1),
+	PIN_FIELD(66, 67, 0x910, 0x10, 6, 1),
+	PIN_FIELD(68, 68, 0x930, 0x10, 2, 1),
+	PIN_FIELD(69, 69, 0x930, 0x10, 1, 1),
+	PIN_FIELD(70, 70, 0x930, 0x10, 6, 1),
+	PIN_FIELD(71, 71, 0x930, 0x10, 5, 1),
+	PIN_FIELD(72, 72, 0x930, 0x10, 4, 1),
+	PIN_FIELD(73, 73, 0x930, 0x10, 3, 1),
+
+	PIN_FIELD(100, 103, 0x910, 0x10, 7, 1),
+	PIN_FIELD(104, 104, 0x920, 0x10, 12, 1),
+	PIN_FIELD(105, 105, 0x920, 0x10, 11, 1),
+	PIN_FIELD(106, 106, 0x930, 0x10, 0, 1),
+	PIN_FIELD(107, 107, 0x920, 0x10, 15, 1),
+	PIN_FIELD(108, 108, 0x920, 0x10, 14, 1),
+	PIN_FIELD(109, 109, 0x920, 0x10, 13, 1),
+	PIN_FIELD(110, 110, 0x920, 0x10, 9, 1),
+	PIN_FIELD(111, 111, 0x920, 0x10, 8, 1),
+	PIN_FIELD(112, 112, 0x920, 0x10, 7, 1),
+	PIN_FIELD(113, 113, 0x920, 0x10, 6, 1),
+	PIN_FIELD(114, 114, 0x920, 0x10, 10, 1),
+	PIN_FIELD(115, 115, 0x920, 0x10, 1, 1),
+	PIN_FIELD(116, 116, 0x920, 0x10, 0, 1),
+	PIN_FIELD(117, 117, 0x920, 0x10, 5, 1),
+	PIN_FIELD(118, 118, 0x920, 0x10, 4, 1),
+	PIN_FIELD(119, 119, 0x920, 0x10, 3, 1),
+	PIN_FIELD(120, 120, 0x920, 0x10, 2, 1),
+	PIN_FIELD(121, 124, 0x910, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
+	PIN_FIELD(0, 6, 0xA00, 0x10, 2, 1),
+	PIN_FIELD(7, 10, 0xA00, 0x10, 3, 1),
+	PIN_FIELD(11, 13, 0xA00, 0x10, 12, 1),
+	PIN_FIELD(14, 17, 0xA00, 0x10, 13, 1),
+	PIN_FIELD(18, 20, 0xA10, 0x10, 10, 1),
+	PIN_FIELD(21, 23, 0xA00, 0x10, 13, 1),
+	PIN_FIELD(24, 25, 0xA00, 0x10, 12, 1),
+	PIN_FIELD(26, 30, 0xA00, 0x10, 0, 1),
+	PIN_FIELD(31, 33, 0xA00, 0x10, 1, 1),
+	PIN_FIELD(40, 40, 0xA10, 0x10, 11, 1),
+	PIN_FIELD(41, 43, 0xA00, 0x10, 10, 1),
+	PIN_FIELD(44, 47, 0xA00, 0x10, 11, 1),
+	PIN_FIELD(48, 51, 0xA00, 0x10, 14, 1),
+	PIN_FIELD(52, 53, 0xA10, 0x10, 0, 1),
+	PIN_FIELD(54, 54, 0xA10, 0x10, 2, 1),
+	PIN_FIELD(55, 57, 0xA10, 0x10, 4, 1),
+	PIN_FIELD(58, 59, 0xA00, 0x10, 15, 1),
+	PIN_FIELD(60, 61, 0xA10, 0x10, 1, 1),
+	PIN_FIELD(62, 65, 0xA10, 0x10, 5, 1),
+	PIN_FIELD(66, 67, 0xA10, 0x10, 6, 1),
+	PIN_FIELD(68, 68, 0xA30, 0x10, 2, 1),
+	PIN_FIELD(69, 69, 0xA30, 0x10, 1, 1),
+	PIN_FIELD(70, 70, 0xA30, 0x10, 3, 1),
+	PIN_FIELD(71, 71, 0xA30, 0x10, 4, 1),
+	PIN_FIELD(72, 72, 0xA30, 0x10, 5, 1),
+	PIN_FIELD(73, 73, 0xA30, 0x10, 6, 1),
+
+	PIN_FIELD(100, 103, 0xA10, 0x10, 7, 1),
+	PIN_FIELD(104, 104, 0xA20, 0x10, 12, 1),
+	PIN_FIELD(105, 105, 0xA20, 0x10, 11, 1),
+	PIN_FIELD(106, 106, 0xA30, 0x10, 13, 1),
+	PIN_FIELD(107, 107, 0xA20, 0x10, 14, 1),
+	PIN_FIELD(108, 108, 0xA20, 0x10, 15, 1),
+	PIN_FIELD(109, 109, 0xA30, 0x10, 0, 1),
+	PIN_FIELD(110, 110, 0xA20, 0x10, 9, 1),
+	PIN_FIELD(111, 111, 0xA20, 0x10, 8, 1),
+	PIN_FIELD(112, 112, 0xA20, 0x10, 7, 1),
+	PIN_FIELD(113, 113, 0xA20, 0x10, 6, 1),
+	PIN_FIELD(114, 114, 0xA20, 0x10, 10, 1),
+	PIN_FIELD(115, 115, 0xA20, 0x10, 1, 1),
+	PIN_FIELD(116, 116, 0xA20, 0x10, 0, 1),
+	PIN_FIELD(117, 117, 0xA20, 0x10, 5, 1),
+	PIN_FIELD(118, 118, 0xA20, 0x10, 4, 1),
+	PIN_FIELD(119, 119, 0xA20, 0x10, 3, 1),
+	PIN_FIELD(120, 120, 0xA20, 0x10, 2, 1),
+	PIN_FIELD(121, 124, 0xA10, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
+	PIN_FIELD(0, 13, 0x500, 0x10, 0, 1),
+	PIN_FIELD(18, 20, 0x510, 0x10, 2, 1),
+	PIN_FIELD(24, 31, 0x510, 0x10, 8, 1),
+	PIN_FIELD(32, 39, 0x520, 0x10, 0, 1),
+	PIN_FIELD(44, 47, 0x520, 0x10, 12, 1),
+	PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+	PIN_FIELD(64, 67, 0x540, 0x10, 0, 1),
+	PIN_FIELD(100, 103, 0x560, 0x10, 4, 1),
+	PIN_FIELD(121, 124, 0x570, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
+	PIN_FIELD(0, 13, 0x600, 0x10, 0, 1),
+	PIN_FIELD(18, 20, 0x610, 0x10, 2, 1),
+	PIN_FIELD(24, 31, 0x610, 0x10, 8, 1),
+	PIN_FIELD(32, 39, 0x620, 0x10, 0, 1),
+	PIN_FIELD(44, 47, 0x620, 0x10, 12, 1),
+	PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+	PIN_FIELD(64, 67, 0x640, 0x10, 0, 1),
+	PIN_FIELD(100, 103, 0x660, 0x10, 4, 1),
+	PIN_FIELD(121, 124, 0x670, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
+	PIN_FIELD(0, 4, 0xd00, 0x10, 0, 4),
+	PIN_FIELD(5, 10, 0xd00, 0x10, 4, 4),
+	PIN_FIELD(11, 13, 0xd00, 0x10, 8, 4),
+	PIN_FIELD(14, 17, 0xd00, 0x10, 12, 4),
+	PIN_FIELD(18, 20, 0xd10, 0x10, 0, 4),
+	PIN_FIELD(21, 23, 0xd00, 0x10, 12, 4),
+	PIN_FIELD(24, 25, 0xd00, 0x10, 8, 4),
+	PIN_FIELD(26, 30, 0xd10, 0x10, 4, 4),
+	PIN_FIELD(31, 33, 0xd10, 0x10, 8, 4),
+	PIN_FIELD(34, 35, 0xd10, 0x10, 12, 4),
+	PIN_FIELD(36, 39, 0xd20, 0x10, 0, 4),
+	PIN_FIELD(40, 40, 0xd20, 0x10, 4, 4),
+	PIN_FIELD(41, 43, 0xd20, 0x10, 8, 4),
+	PIN_FIELD(44, 47, 0xd20, 0x10, 12, 4),
+	PIN_FIELD(48, 51, 0xd30, 0x10, 0, 4),
+	PIN_FIELD(54, 54, 0xd30, 0x10, 8, 4),
+	PIN_FIELD(55, 57, 0xd30, 0x10, 12, 4),
+	PIN_FIELD(62, 67, 0xd40, 0x10, 8, 4),
+	PIN_FIELD(68, 68, 0xd40, 0x10, 12, 4),
+	PIN_FIELD(69, 69, 0xd50, 0x10, 0, 4),
+	PIN_FIELD(70, 73, 0xd50, 0x10, 4, 4),
+	PIN_FIELD(100, 103, 0xd50, 0x10, 8, 4),
+	PIN_FIELD(104, 104, 0xd50, 0x10, 12, 4),
+	PIN_FIELD(105, 105, 0xd60, 0x10, 0, 4),
+	PIN_FIELD(106, 109, 0xd60, 0x10, 4, 4),
+	PIN_FIELD(110, 113, 0xd70, 0x10, 0, 4),
+	PIN_FIELD(114, 114, 0xd70, 0x10, 4, 4),
+	PIN_FIELD(115, 115, 0xd60, 0x10, 12, 4),
+	PIN_FIELD(116, 116, 0xd60, 0x10, 8, 4),
+	PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
+	[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
+	[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8516_pins[] = {
+	MTK_PIN(0, "EINT0", DRV_GRP0),
+	MTK_PIN(1, "EINT1", DRV_GRP0),
+	MTK_PIN(2, "EINT2", DRV_GRP0),
+	MTK_PIN(3, "EINT3", DRV_GRP0),
+	MTK_PIN(4, "EINT4", DRV_GRP0),
+	MTK_PIN(5, "EINT5", DRV_GRP0),
+	MTK_PIN(6, "EINT6", DRV_GRP0),
+	MTK_PIN(7, "EINT7", DRV_GRP0),
+	MTK_PIN(8, "EINT8", DRV_GRP0),
+	MTK_PIN(9, "EINT9", DRV_GRP0),
+	MTK_PIN(10, "EINT10", DRV_GRP0),
+	MTK_PIN(11, "EINT11", DRV_GRP0),
+	MTK_PIN(12, "EINT12", DRV_GRP0),
+	MTK_PIN(13, "EINT13", DRV_GRP0),
+	MTK_PIN(14, "EINT14", DRV_GRP2),
+	MTK_PIN(15, "EINT15", DRV_GRP2),
+	MTK_PIN(16, "EINT16", DRV_GRP2),
+	MTK_PIN(17, "EINT17", DRV_GRP2),
+	MTK_PIN(18, "EINT18", DRV_GRP0),
+	MTK_PIN(19, "EINT19", DRV_GRP0),
+	MTK_PIN(20, "EINT20", DRV_GRP0),
+	MTK_PIN(21, "EINT21", DRV_GRP2),
+	MTK_PIN(22, "EINT22", DRV_GRP2),
+	MTK_PIN(23, "EINT23", DRV_GRP2),
+	MTK_PIN(24, "EINT24", DRV_GRP0),
+	MTK_PIN(25, "EINT25", DRV_GRP0),
+	MTK_PIN(26, "PWRAP_SPI0_MI", DRV_GRP4),
+	MTK_PIN(27, "PWRAP_SPI0_MO", DRV_GRP4),
+	MTK_PIN(28, "PWRAP_INT", DRV_GRP4),
+	MTK_PIN(29, "PWRAP_SPIO0_CK", DRV_GRP4),
+	MTK_PIN(30, "PWARP_SPI0_CSN", DRV_GRP4),
+	MTK_PIN(31, "RTC32K_CK", DRV_GRP4),
+	MTK_PIN(32, "WATCHDOG", DRV_GRP4),
+	MTK_PIN(33, "SRCLKENA0", DRV_GRP4),
+	MTK_PIN(34, "URXD2", DRV_GRP0),
+	MTK_PIN(35, "UTXD2", DRV_GRP0),
+	MTK_PIN(36, "MRG_CLK", DRV_GRP0),
+	MTK_PIN(37, "MRG_SYNC", DRV_GRP0),
+	MTK_PIN(38, "MRG_DI", DRV_GRP0),
+	MTK_PIN(39, "MRG_DO", DRV_GRP0),
+	MTK_PIN(40, "KPROW0", DRV_GRP2),
+	MTK_PIN(41, "KPROW1", DRV_GRP2),
+	MTK_PIN(42, "KPCOL0", DRV_GRP2),
+	MTK_PIN(43, "KPCOL1", DRV_GRP2),
+	MTK_PIN(44, "JMTS", DRV_GRP2),
+	MTK_PIN(45, "JTCK", DRV_GRP2),
+	MTK_PIN(46, "JTDI", DRV_GRP2),
+	MTK_PIN(47, "JTDO", DRV_GRP2),
+	MTK_PIN(48, "SPI_CS", DRV_GRP2),
+	MTK_PIN(49, "SPI_CK", DRV_GRP2),
+	MTK_PIN(50, "SPI_MI", DRV_GRP2),
+	MTK_PIN(51, "SPI_MO", DRV_GRP2),
+	MTK_PIN(52, "SDA1", DRV_GRP2),
+	MTK_PIN(53, "SCL1", DRV_GRP2),
+	MTK_PIN(54, "DISP_PWM", DRV_GRP2),
+	MTK_PIN(55, "I2S_DATA_IN", DRV_GRP2),
+	MTK_PIN(56, "I2S_LRCK", DRV_GRP2),
+	MTK_PIN(57, "I2S_BCK", DRV_GRP2),
+	MTK_PIN(58, "SDA0", DRV_GRP2),
+	MTK_PIN(59, "SCL0", DRV_GRP2),
+	MTK_PIN(60, "SDA2", DRV_GRP2),
+	MTK_PIN(61, "SCL2", DRV_GRP2),
+	MTK_PIN(62, "URXD0", DRV_GRP2),
+	MTK_PIN(63, "UTXD0", DRV_GRP2),
+	MTK_PIN(64, "URXD1", DRV_GRP2),
+	MTK_PIN(65, "UTXD1", DRV_GRP2),
+	MTK_PIN(66, "LCM_RST", DRV_GRP2),
+	MTK_PIN(67, "DSI_TE", DRV_GRP2),
+	MTK_PIN(68, "MSDC2_CMD", DRV_GRP4),
+	MTK_PIN(69, "MSDC2_CLK", DRV_GRP4),
+	MTK_PIN(70, "MSDC2_DAT0", DRV_GRP4),
+	MTK_PIN(71, "MSDC2_DAT1", DRV_GRP4),
+	MTK_PIN(72, "MSDC2_DAT2", DRV_GRP4),
+	MTK_PIN(73, "MSDC2_DAT3", DRV_GRP4),
+	MTK_PIN(74, "TDN3", DRV_GRP0),
+	MTK_PIN(75, "TDP3", DRV_GRP0),
+	MTK_PIN(76, "TDN2", DRV_GRP0),
+	MTK_PIN(77, "TDP2", DRV_GRP0),
+	MTK_PIN(78, "TCN", DRV_GRP0),
+	MTK_PIN(79, "TCP", DRV_GRP0),
+	MTK_PIN(80, "TDN1", DRV_GRP0),
+	MTK_PIN(81, "TDP1", DRV_GRP0),
+	MTK_PIN(82, "TDN0", DRV_GRP0),
+	MTK_PIN(83, "TDP0", DRV_GRP0),
+	MTK_PIN(84, "RDN0", DRV_GRP0),
+	MTK_PIN(85, "RDP0", DRV_GRP0),
+	MTK_PIN(86, "RDN1", DRV_GRP0),
+	MTK_PIN(87, "RDP1", DRV_GRP0),
+	MTK_PIN(88, "RCN", DRV_GRP0),
+	MTK_PIN(89, "RCP", DRV_GRP0),
+	MTK_PIN(90, "RDN2", DRV_GRP0),
+	MTK_PIN(91, "RDP2", DRV_GRP0),
+	MTK_PIN(92, "RDN3", DRV_GRP0),
+	MTK_PIN(93, "RDP3", DRV_GRP0),
+	MTK_PIN(94, "RCN_A", DRV_GRP0),
+	MTK_PIN(95, "RCP_A", DRV_GRP0),
+	MTK_PIN(96, "RDN1_A", DRV_GRP0),
+	MTK_PIN(97, "RDP1_A", DRV_GRP0),
+	MTK_PIN(98, "RDN0_A", DRV_GRP0),
+	MTK_PIN(99, "RDP0_A", DRV_GRP0),
+	MTK_PIN(100, "CMDDAT0", DRV_GRP2),
+	MTK_PIN(101, "CMDDAT1", DRV_GRP2),
+	MTK_PIN(102, "CMMCLK", DRV_GRP2),
+	MTK_PIN(103, "CMPCLK", DRV_GRP2),
+	MTK_PIN(104, "MSDC1_CMD", DRV_GRP4),
+	MTK_PIN(105, "MSDC1_CLK", DRV_GRP4),
+	MTK_PIN(106, "MSDC1_DAT0", DRV_GRP4),
+	MTK_PIN(107, "MSDC1_DAT1", DRV_GRP4),
+	MTK_PIN(108, "MSDC1_DAT2", DRV_GRP4),
+	MTK_PIN(109, "MSDC1_DAT3", DRV_GRP4),
+	MTK_PIN(110, "MSDC0_DAT7", DRV_GRP4),
+	MTK_PIN(111, "MSDC0_DAT6", DRV_GRP4),
+	MTK_PIN(112, "MSDC0_DAT5", DRV_GRP4),
+	MTK_PIN(113, "MSDC0_DAT4", DRV_GRP4),
+	MTK_PIN(114, "MSDC0_RSTB", DRV_GRP4),
+	MTK_PIN(115, "MSDC0_CMD", DRV_GRP4),
+	MTK_PIN(116, "MSDC0_CLK", DRV_GRP4),
+	MTK_PIN(117, "MSDC0_DAT3", DRV_GRP4),
+	MTK_PIN(118, "MSDC0_DAT2", DRV_GRP4),
+	MTK_PIN(119, "MSDC0_DAT1", DRV_GRP4),
+	MTK_PIN(120, "MSDC0_DAT0", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
+static int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
+static int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
+static int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
+static int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
+static int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd",
+						"uart1_0_rxd_txd",
+						"uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
+				   119, 120, };
+static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8516_groups[] = {
+	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
+	PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8516_uart1_0_rxd_txd),
+	PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8516_uart2_0_rxd_txd),
+
+	PINCTRL_PIN_GROUP("msdc0", mt8516_msdc0),
+};
+
+static const char *const mt8516_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8516_functions[] = {
+	{"uart", mt8516_uart_groups, ARRAY_SIZE(mt8516_uart_groups)},
+	{"msdc", mt8516_msdc_groups, ARRAY_SIZE(mt8516_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8516_data = {
+	.name = "mt8516_pinctrl",
+	.reg_cal = mt8516_reg_cals,
+	.pins = mt8516_pins,
+	.npins = ARRAY_SIZE(mt8516_pins),
+	.grps = mt8516_groups,
+	.ngrps = ARRAY_SIZE(mt8516_groups),
+	.funcs = mt8516_functions,
+	.nfuncs = ARRAY_SIZE(mt8516_functions),
+};
+
+static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
+{
+	return mtk_pinctrl_common_probe(dev, &mt8516_data);
+}
+
+static const struct udevice_id mt8516_pctrl_match[] = {
+	{ .compatible = "mediatek,mt8516-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8516_pinctrl) = {
+	.name = "mt8516_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = mt8516_pctrl_match,
+	.ops = &mtk_pinctrl_ops,
+	.probe = mtk_pinctrl_mt8516_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC
  2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
                   ` (4 preceding siblings ...)
  2019-02-04 10:58 ` [U-Boot] [PATCH 5/6] pinctrl: " Fabien Parent
@ 2019-02-04 10:58 ` Fabien Parent
  2019-02-08 15:59   ` Tom Rini
  5 siblings, 1 reply; 13+ messages in thread
From: Fabien Parent @ 2019-02-04 10:58 UTC (permalink / raw)
  To: u-boot

Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm/dts/mt8516.dtsi               | 142 +++++++++++++++++++++++++
 arch/arm/mach-mediatek/Kconfig         |  10 ++
 arch/arm/mach-mediatek/Makefile        |   1 +
 arch/arm/mach-mediatek/mt8516/Makefile |   3 +
 arch/arm/mach-mediatek/mt8516/init.c   | 112 +++++++++++++++++++
 5 files changed, 268 insertions(+)
 create mode 100644 arch/arm/dts/mt8516.dtsi
 create mode 100644 arch/arm/mach-mediatek/mt8516/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt8516/init.c

diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi
new file mode 100644
index 0000000000..72808c5757
--- /dev/null
+++ b/arch/arm/dts/mt8516.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/clock/mt8516-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt8516";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "mediatek,mt8516-smp";
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x1>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x2>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x3>;
+			clock-frequency = <1300000000>;
+		};
+	};
+
+	topckgen: clock-controller at 10000000 {
+		compatible = "mediatek,mt8516-topckgen";
+		reg = <0x10000000 0x1000>;
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+	};
+
+	topckgen_cg: clock-controller-cg at 10000000 {
+		compatible = "mediatek,mt8516-topckgen-cg";
+		reg = <0x10000000 0x1000>;
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+	};
+
+	infracfg: clock-controller at 10001000 {
+		compatible = "mediatek,mt8516-infracfg";
+		reg = <0x10001000 0x1000>;
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+	};
+
+	apmixedsys: clock-controller at 10018000 {
+		compatible = "mediatek,mt8516-apmixedsys";
+		reg = <0x10018000 0x710>;
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+	};
+
+	gic: interrupt-controller at 10310000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0x10310000 0x1000>,
+		      <0x10320000 0x1000>,
+		      <0x10340000 0x2000>,
+		      <0x10360000 0x2000>;
+		interrupts = <GIC_PPI 9
+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	sysirq: interrupt-controller at 10200620 {
+		compatible = "mediatek,sysirq";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0x10200620 0x20>;
+	};
+
+	watchdog: watchdog at 10007000 {
+		compatible = "mediatek,wdt";
+		reg = <0x10007000 0x1000>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+		#reset-cells = <1>;
+		status = "disabled";
+	};
+
+	pinctrl: pinctrl at 10005000 {
+		compatible = "mediatek,mt8516-pinctrl";
+		reg = <0x10005000 0x1000>;
+
+		gpio: gpio-controller {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
+	mmc0: mmc at 11120000 {
+		compatible = "mediatek,mt8516-mmc";
+		reg = <0x11120000 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen_cg CLK_TOP_MSDC0>,
+			 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
+			 <&topckgen_cg CLK_TOP_MSDC0_INFRA>;
+		clock-names = "source", "hclk", "source_cg";
+		status = "disabled";
+	};
+
+	uart0: serial at 11005000 {
+		compatible = "mediatek,hsuart";
+		reg = <0x11005000 0x1000>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_UART0_SEL>,
+			 <&topckgen_cg CLK_TOP_UART0>;
+		clock-names = "baud","bus";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 7a733e95df..b5e91d4a7d 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -31,6 +31,16 @@ config TARGET_MT7629
 	  including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
 	  switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
 
+config TARGET_MT8516
+	bool "MediaTek MT8516 SoC"
+	select ARM64
+	select ARCH_MISC_INIT
+	help
+	  The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
+	  including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+	  Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+	  chip and several DDR3 and DDR4 options.
+
 endchoice
 
 source "board/mediatek/mt7623/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index b5d3a379bc..ea414dc407 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_SPL_BUILD)	+= spl.o
 
 obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
+obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt8516/Makefile b/arch/arm/mach-mediatek/mt8516/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8516/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c
new file mode 100644
index 0000000000..2dbd4369af
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8516/init.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <linux/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WDOG_SWRST		0x10007014
+#define WDOG_SWRST_KEY		0x1209
+
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	return fdtdec_setup_mem_size_base();
+}
+
+int mtk_pll_early_init(void)
+{
+	unsigned long pll_rates[] = {
+		[CLK_APMIXED_ARMPLL] =   1300000000,
+		[CLK_APMIXED_MAINPLL] =  1501000000,
+		[CLK_APMIXED_UNIVPLL] =  1248000000,
+		[CLK_APMIXED_MMPLL] =     380000000,
+	};
+	struct udevice *dev;
+	int ret, i;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+	if (ret)
+		return ret;
+
+	/* configure default rate then enable apmixedsys */
+	for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+		struct clk clk = { .id = i, .dev = dev };
+
+		ret = clk_set_rate(&clk, pll_rates[i]);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(&clk);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+	int ret;
+
+	/* initialize early clocks */
+	ret = mtk_pll_early_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	while (1) {
+		writel(WDOG_SWRST_KEY, WDOG_SWRST);
+		mdelay(5);
+	}
+}
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   MediaTek MT8516\n");
+	return 0;
+}
+
+static struct mm_region mt8516_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+struct mm_region *mem_map = mt8516_mem_map;
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC
  2019-02-04 10:58 ` [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
@ 2019-02-08 15:59   ` Tom Rini
  0 siblings, 0 replies; 13+ messages in thread
From: Tom Rini @ 2019-02-08 15:59 UTC (permalink / raw)
  To: u-boot

On Mon, Feb 04, 2019 at 11:58:46AM +0100, Fabien Parent wrote:

> Add support for MediaTek MT8516 SoC. This include the file
> that will initialize the SoC after boot and its device tree.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
[snip]
> +	topckgen: clock-controller at 10000000 {
> +		compatible = "mediatek,mt8516-topckgen";
> +		reg = <0x10000000 0x1000>;
> +		#clock-cells = <1>;
> +		u-boot,dm-pre-reloc;
> +	};

The u-boot,xxx properties go in a -u-boot.dtsi file, see
scripts/Makefile.lib for the logic on how we automatically find them.
This makes future re-syncs with this file from the kernel less
problematic (as seen on say am33xx where we broke some platforms when we
removed these dm-pre-reloc properties by accident as they didn't get put
into am33xx-u-boot.dtsi as the mechanism didn't exist then).  Thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 5/6] pinctrl: add driver for MT8516
  2019-02-04 10:58 ` [U-Boot] [PATCH 5/6] pinctrl: " Fabien Parent
@ 2019-02-11  2:51   ` Ryder Lee
  0 siblings, 0 replies; 13+ messages in thread
From: Ryder Lee @ 2019-02-11  2:51 UTC (permalink / raw)
  To: u-boot

On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add Pinctrl driver for MediaTek MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/pinctrl/mediatek/Kconfig          |   4 +
>  drivers/pinctrl/mediatek/Makefile         |   1 +
>  drivers/pinctrl/mediatek/pinctrl-mt8516.c | 391 ++++++++++++++++++++++
>  3 files changed, 396 insertions(+)
>  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
> 
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index 1bd9a925a5..9930ca1faf 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -12,4 +12,8 @@ config PINCTRL_MT7629
>  	bool "MT7629 SoC pinctrl driver"
>  	select PINCTRL_MTK
>  
> +config PINCTRL_MT8516
> +	bool "MT8516 SoC pinctrl driver"
> +	select PINCTRL_MTK
> +
>  endif
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index f6ef3627e8..c4f29088d2 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
>  # SoC Drivers
>  obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
>  obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
> +obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
> new file mode 100644
> index 0000000000..17083e9aa3
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
> @@ -0,0 +1,391 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */

Looks good to me, but we are in 2019 now :)

Acked-by: Ryder Lee <ryder.lee@mediatek.com>

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516
  2019-02-04 10:58 ` [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516 Fabien Parent
@ 2019-02-11  2:52   ` Ryder Lee
  0 siblings, 0 replies; 13+ messages in thread
From: Ryder Lee @ 2019-02-11  2:52 UTC (permalink / raw)
  To: u-boot

On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add config for handling MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Acked-by: Ryder Lee <ryder.lee@mediatek.com>

> ---
>  drivers/mmc/mtk-sd.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
> index 8573ea7430..9373481f50 100644
> --- a/drivers/mmc/mtk-sd.c
> +++ b/drivers/mmc/mtk-sd.c
> @@ -1384,8 +1384,18 @@ static const struct msdc_compatible mt7623_compat = {
>  	.enhance_rx = false
>  };
>  
> +static const struct msdc_compatible mt8516_compat = {
> +	.clk_div_bits = 12,
> +	.pad_tune0 = true,
> +	.async_fifo = true,
> +	.data_tune = true,
> +	.busy_check = true,
> +	.stop_clk_fix = true,
> +};
> +
>  static const struct udevice_id msdc_ids[] = {
>  	{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
> +	{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
>  	{}
>  };
>  

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag
  2019-02-04 10:58 ` [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag Fabien Parent
@ 2019-02-11  2:54   ` Ryder Lee
  0 siblings, 0 replies; 13+ messages in thread
From: Ryder Lee @ 2019-02-11  2:54 UTC (permalink / raw)
  To: u-boot

On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add the implementation for the CLK_GATE_SETCLR_INV flag.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Acked-by: Ryder Lee <ryder.lee@mediatek.com>

> ---
>  drivers/clk/mediatek/clk-mtk.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 870b14ed8b..725be031b8 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -390,6 +390,9 @@ static int mtk_clk_gate_enable(struct clk *clk)
>  	case CLK_GATE_SETCLR:
>  		writel(bit, priv->base + gate->regs->clr_ofs);
>  		break;
> +	case CLK_GATE_SETCLR_INV:
> +		writel(bit, priv->base + gate->regs->set_ofs);
> +		break;
>  	case CLK_GATE_NO_SETCLR_INV:
>  		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
>  		break;

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516
  2019-02-04 10:58 ` [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516 Fabien Parent
@ 2019-02-11  3:20   ` Ryder Lee
  0 siblings, 0 replies; 13+ messages in thread
From: Ryder Lee @ 2019-02-11  3:20 UTC (permalink / raw)
  To: u-boot

On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Add clock driver for MediaTek MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8516.c      | 802 +++++++++++++++++++++++++
>  include/dt-bindings/clock/mt8516-clk.h | 251 ++++++++
>  3 files changed, 1054 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8516.c
>  create mode 100644 include/dt-bindings/clock/mt8516-clk.h
> 
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 0632dc87b6..a47a5bdbc2 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
>  # SoC Drivers
>  obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
>  obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
> +obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
> diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
> new file mode 100644
> index 0000000000..8963449bb9
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8516.c
> @@ -0,0 +1,802 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek clock driver for MT8516 SoC
> + *
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
[snip]

> diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
> new file mode 100644
> index 0000000000..b62a971c59
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8516-clk.h
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 BayLibre, SAS
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
[snip]

We are in 2019 now :)

Acked-by: Ryder Lee <ryder.lee@mediatek.com>

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support
  2019-02-04 10:58 ` [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support Fabien Parent
@ 2019-02-11  3:46   ` Ryder Lee
  0 siblings, 0 replies; 13+ messages in thread
From: Ryder Lee @ 2019-02-11  3:46 UTC (permalink / raw)
  To: u-boot

On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote:
> Some MediaTek SoC need an additional clock "source_cg". Enable
> this new clock. We reuse the same clock name as in the kernel.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Acked-by: Ryder Lee <ryder.lee@mediatek.com>

> ---
>  drivers/mmc/mtk-sd.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
> index d3f0778368..8573ea7430 100644
> --- a/drivers/mmc/mtk-sd.c
> +++ b/drivers/mmc/mtk-sd.c
> @@ -247,7 +247,9 @@ struct msdc_host {
>  	struct msdc_compatible *dev_comp;
>  
>  	struct clk src_clk;	/* for SD/MMC bus clock */
> +	struct clk src_clk_cg;	/* optional, MSDC source clock control gate */
>  	struct clk h_clk;	/* MSDC core clock */
> +	bool has_src_clk_cg;

<just_checking>
  Could we have a chance to get rid of this flag?
</just_checking>

>  	u32 src_clk_freq;	/* source clock */
>  	u32 mclk;		/* mmc framework required bus clock */
> @@ -1269,6 +1271,8 @@ static void msdc_ungate_clock(struct msdc_host *host)
>  {
>  	clk_enable(&host->src_clk);
>  	clk_enable(&host->h_clk);
> +	if (host->has_src_clk_cg)
> +		clk_enable(&host->src_clk_cg);
>  }
>  
>  static int msdc_drv_probe(struct udevice *dev)
> @@ -1332,6 +1336,10 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
>  	if (ret < 0)
>  		return ret;
>  
> +	ret = clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
> +	if (!ret)
> +		host->has_src_clk_cg = true;
> +
>  #if IS_ENABLED(DM_GPIO)
>  	gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
>  	gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);

^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-02-11  3:46 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-04 10:58 [U-Boot] [PATCH 0/6] Add support for MT8516 SoCs Fabien Parent
2019-02-04 10:58 ` [U-Boot] [PATCH 1/6] mmc: mtk-sd: add source_cg clock support Fabien Parent
2019-02-11  3:46   ` Ryder Lee
2019-02-04 10:58 ` [U-Boot] [PATCH 2/6] mmc: mtk-sd: add support for MT8516 Fabien Parent
2019-02-11  2:52   ` Ryder Lee
2019-02-04 10:58 ` [U-Boot] [PATCH 3/6] clk: mediatek: add support for CLK_GATE_SETCLR_INV flag Fabien Parent
2019-02-11  2:54   ` Ryder Lee
2019-02-04 10:58 ` [U-Boot] [PATCH 4/6] clk: mediatek: add driver for MT8516 Fabien Parent
2019-02-11  3:20   ` Ryder Lee
2019-02-04 10:58 ` [U-Boot] [PATCH 5/6] pinctrl: " Fabien Parent
2019-02-11  2:51   ` Ryder Lee
2019-02-04 10:58 ` [U-Boot] [PATCH 6/6] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
2019-02-08 15:59   ` Tom Rini

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