[v8 0/5] Add support for Gen 11 pipe color features

[v8 0/5] Add support for Gen 11 pipe color features

[Uma Shankar]

This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.

CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in
pipe. Also there is a corner case where Lut precision is increased
to 3.16, hence its not possible to accurately represent 1.0 which
will require 17 bits. Support for extending the ABI is already in
discussion in below series:
https://patchwork.freedesktop.org/patch/249771/

ToDo: Support for Multi Segmented Gamma will be added later.

v2: Addressed Maarten's review comments and re-ordered the patch
series.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Matt's, Ville and Jani Nikula's review comments.

v6: Addressed Matt and Ville's review comments. Extended GLK 
degamma function and merged ICL degamma support to that. Handled
pipe output csc separately along with regular pipe csc. Dropped
gamma_mode removal patch as Ville is using that to refactor the
gamma handling. This series may need a rebase on top of Ville's
below series:
https://patchwork.freedesktop.org/series/55081/. 

v7: Rebased the series on top of Ville's color management
cleanup and state refactoring series. Addressed Matt's review
comments and aligned state handling as per atomic design.

v8: Fixed macro alignment and some checkpatch warnings.

Uma Shankar (5):
  drm/i915/glk: Fix degamma lut programming
  drm/i915/icl: Add icl pipe degamma and gamma support
  drm/i915/icl: Enable ICL Pipe CSC block
  drm/i915/icl: Enable pipe output csc
  drm/i915/icl: Add degamma and gamma lut size to gen11 caps

 drivers/gpu/drm/i915/i915_pci.c    |   5 +-
 drivers/gpu/drm/i915/i915_reg.h    |  86 +++++++++++++++++++---
 drivers/gpu/drm/i915/intel_color.c | 141 ++++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_drv.h   |   3 +
 4 files changed, 199 insertions(+), 36 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v8 1/5] drm/i915/glk: Fix degamma lut programming

[Uma Shankar]

Fixed the glk degamma lut programming which currently
was hard coding a linear lut all the time, making degamma
block of glk basically a pass through.

Currently degamma lut for glk is assigned as 0 in platform
configuration. Updated the same to 33 as per the hardware
capability. IGT tests for degamma were getting skipped due to
this, spotted by Swati.

ToDo: The current gamma/degamm lut ABI has just 16bit for each
color component. This is not enough for GLK+, since input
precision is increased to 3.16 which will need 19bit entries.

v2: Added Matt's RB.

v3: Changed uint32_t to u32.

Credits-to: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c    |  2 +-
 drivers/gpu/drm/i915/intel_color.c | 34 ++++++++++++++++++++++++++--------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 66f82f3..2a4d25c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -75,7 +75,7 @@
 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 #define GLK_COLORS \
-	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024, \
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 					DRM_COLOR_LUT_EQUAL_CHANNELS, \
 	}
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index c0e2806..4e13286 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,7 +518,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = 33;
+	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	u32 i;
 
 	/*
@@ -529,14 +529,32 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 	I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 
-	/*
-	 *  FIXME: The pipe degamma table in geminilake doesn't support
-	 *  different values per channel, so this just loads a linear table.
-	 */
-	for (i = 0; i < lut_size; i++) {
-		u32 v = (i * (1 << 16)) / (lut_size - 1);
+	if (crtc_state->base.degamma_lut) {
+		struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
+
+		for (i = 0; i < lut_size; i++) {
+			/*
+			 * First 33 entries represent range from 0 to 1.0
+			 * 34th and 35th entry will represent extended range
+			 * inputs 3.0 and 7.0 respectively, currently clamped
+			 * at 1.0. Since the precision is 16bit, the user
+			 * value can be directly filled to register.
+			 * The pipe degamma table in GLK+ onwards doesn't
+			 * support different values per channel, so this just
+			 * programs green value which will be equal to Red and
+			 * Blue into the lut registers.
+			 * ToDo: Extend to max 7.0. Enable 32 bit input value
+			 * as compared to just 16 to achieve this.
+			 */
+			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
+		}
+	} else {
+		/* load a linear table. */
+		for (i = 0; i < lut_size; i++) {
+			u32 v = (i * (1 << 16)) / (lut_size - 1);
 
-		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
+			I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
+		}
 	}
 
 	/* Clamp values > 1.0. */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support

[Uma Shankar]

Add support for icl pipe degamma and gamma.

v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Fixed Matt's review comments.

v5: Corrected macro alignment as per Jani Nikula's comments.
Addressed Ville and Matt's  review comments.

v6: Merged ICL degamma handling with GLK and dropped ICL
degamma function as per Ville and Matt's comments.

v7: updated gamma_mode state with pre csc gammma and post
gamma enabling in intel_color_check to align with atomic.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
 drivers/gpu/drm/i915/intel_color.c | 32 ++++++++++++++++++++++++++++++--
 2 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11bf60d..13a207a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7111,11 +7111,13 @@ enum {
 #define _GAMMA_MODE_A		0x4a480
 #define _GAMMA_MODE_B		0x4ac80
 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
-#define GAMMA_MODE_MODE_MASK	(3 << 0)
-#define GAMMA_MODE_MODE_8BIT	(0 << 0)
-#define GAMMA_MODE_MODE_10BIT	(1 << 0)
-#define GAMMA_MODE_MODE_12BIT	(2 << 0)
-#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
+#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
+#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
+#define  GAMMA_MODE_MODE_MASK	(3 << 0)
+#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
+#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
+#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
+#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 4e13286..0fcaae4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -583,6 +583,28 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static void icl_load_luts(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	glk_load_degamma_lut(crtc_state);
+
+	if (crtc_state_is_legacy_gamma(crtc_state)) {
+		i9xx_load_luts(crtc_state);
+	} else {
+		/* ToDo: Add support for multi segment gamma LUT */
+		bdw_load_gamma_lut(crtc_state, 0);
+
+		/*
+		 * Reset the index, otherwise it prevents the legacy
+		 * palette to be written properly.
+		 */
+		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+	}
+}
+
 static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -772,7 +794,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	    drm_color_lut_check(gamma_lut, gamma_tests))
 		return -EINVAL;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
+		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT |
+					 PRE_CSC_GAMMA_ENABLE |
+					 POST_CSC_GAMMA_ENABLE;
+	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
@@ -796,7 +822,9 @@ void intel_color_init(struct intel_crtc *crtc)
 
 		dev_priv->display.color_commit = i9xx_color_commit;
 	} else {
-		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		if (IS_ICELAKE(dev_priv))
+			dev_priv->display.load_luts = icl_load_luts;
+		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			dev_priv->display.load_luts = glk_load_luts;
 		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 			dev_priv->display.load_luts = broadwell_load_luts;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v8 3/5] drm/i915/icl: Enable ICL Pipe CSC block

[Uma Shankar]

Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.

ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.

v2: Addressed Maarten's review comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Ville's review comments.

v6: Separated pipe output csc programming from regular csc.

v7: Rebase

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 9 ++++++---
 drivers/gpu/drm/i915/intel_color.c | 5 ++++-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13a207a..4cb0013 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9885,10 +9885,13 @@ enum skl_power_gate {
 #define _PIPE_A_CSC_COEFF_BU	0x4901c
 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
 #define _PIPE_A_CSC_COEFF_BV	0x49024
+
 #define _PIPE_A_CSC_MODE	0x49028
-#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
-#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
-#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
+#define  ICL_CSC_ENABLE			(1 << 31)
+#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
+#define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
+#define  CSC_MODE_YUV_TO_RGB		(1 << 0)
+
 #define _PIPE_A_CSC_PREOFF_HI	0x49030
 #define _PIPE_A_CSC_PREOFF_ME	0x49034
 #define _PIPE_A_CSC_PREOFF_LO	0x49038
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0fcaae4..826f8a8 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -243,7 +243,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		if (INTEL_GEN(dev_priv) >= 11)
+			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
+		else
+			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 	} else {
 		u32 mode = CSC_MODE_YUV_TO_RGB;
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v8 4/5] drm/i915/icl: Enable pipe output csc

[Uma Shankar]

GEN11+ onwards an output csc hardware block has been added.
This is after the pipe gamma block and is in addition to the
legacy pipe CSC block. Primary use case for this block is to
convert RGB to YUV in case sink supports YUV.
This patch adds supports for the same.

v2: This is added after splitting the existing ICL pipe CSC
handling. As per Matt's suggestion, made this to co-exist
with existing pipe CSC, wherein both can be enabled if a
certain usecase arises.

v3: Fixed an issue with co-existence of output csc and normal
pipe csc, spotted by Matt. Put the csc mode flag enabling to
color_check to align with atomic.

v4: Fixed macro alignment and checkpatch complaints wrt line over
100 characters limit.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 65 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_color.c | 77 ++++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h   |  3 ++
 3 files changed, 126 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4cb0013..668e862 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9888,6 +9888,7 @@ enum skl_power_gate {
 
 #define _PIPE_A_CSC_MODE	0x49028
 #define  ICL_CSC_ENABLE			(1 << 31)
+#define  ICL_OUTPUT_CSC_ENABLE		(1 << 30)
 #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
 #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
 #define  CSC_MODE_YUV_TO_RGB		(1 << 0)
@@ -9927,6 +9928,70 @@ enum skl_power_gate {
 #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
 #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
+/* Pipe Output CSC */
+#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
+#define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
+#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
+#define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
+#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
+#define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
+#define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
+#define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
+#define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
+#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
+
+#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
+#define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
+#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
+#define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
+#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
+#define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
+#define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
+#define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
+#define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
+#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
+
+#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe,\
+							   _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
+							   _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
+#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_COEFF_BY, \
+							   _PIPE_B_OUTPUT_CSC_COEFF_BY)
+#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
+							   _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
+#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_COEFF_BU, \
+							   _PIPE_B_OUTPUT_CSC_COEFF_BU)
+#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
+							   _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
+#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_COEFF_BV, \
+							   _PIPE_B_OUTPUT_CSC_COEFF_BV)
+#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
+							   _PIPE_B_OUTPUT_CSC_PREOFF_HI)
+#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
+							   _PIPE_B_OUTPUT_CSC_PREOFF_ME)
+#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
+							   _PIPE_B_OUTPUT_CSC_PREOFF_LO)
+#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
+							   _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
+#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
+							   _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
+#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, \
+							   _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
+							   _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
+
 /* pipe degamma/gamma LUTs on IVB+ */
 #define _PAL_PREC_INDEX_A	0x4A400
 #define _PAL_PREC_INDEX_B	0x4AC00
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 826f8a8..1fb22cf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -118,23 +118,47 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+	if (INTEL_GEN(dev_priv) < 11) {
+		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 
-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
+		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
 
-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
+		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
 
-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
+		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
 
-	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
-	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
-	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
-	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
+	} else {
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
+		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
+			   CSC_RGB_TO_YUV_RU_GU);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
+			   CSC_RGB_TO_YUV_RY_GY);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
+			   CSC_RGB_TO_YUV_RV_GV);
+		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
+			   POSTOFF_RGB_TO_YUV_HI);
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
+			   POSTOFF_RGB_TO_YUV_ME);
+		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
+			   POSTOFF_RGB_TO_YUV_LO);
+	}
 }
 
 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
@@ -156,8 +180,16 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
 		ilk_load_ycbcr_conversion_matrix(crtc);
-		return;
-	} else if (crtc_state->base.ctm) {
+		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
+		/*
+		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC
+		 * RGB to YUV conversion can be done. No need to go further
+		 */
+		if (INTEL_GEN(dev_priv) < 11)
+			return;
+	}
+
+	if (crtc_state->base.ctm) {
 		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 		const u64 *input;
 		u64 temp[9];
@@ -243,10 +275,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		if (INTEL_GEN(dev_priv) >= 11)
-			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
-		else
-			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
 	} else {
 		u32 mode = CSC_MODE_YUV_TO_RGB;
 
@@ -808,6 +837,16 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 
+	crtc_state->csc_mode = 0;
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+			crtc_state->csc_mode |= ICL_OUTPUT_CSC_ENABLE;
+
+		crtc_state->csc_mode |= ICL_CSC_ENABLE;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5eb0b66..765c2ff 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -942,6 +942,9 @@ struct intel_crtc_state {
 	/* Gamma mode programmed on the pipe */
 	u32 gamma_mode;
 
+	/* CSC mode programmed on the pipe */
+	u32 csc_mode;
+
 	/* bitmask of visible planes (enum plane_id) */
 	u8 active_planes;
 	u8 nv12_planes;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v8 5/5] drm/i915/icl: Add degamma and gamma lut size to gen11 caps

[Uma Shankar]

Add the degamma and gamma lut sizes to gen11 capability
structure.

Note: Currently this doesn't account for the extended range gamma
entries and this will be addressed with new segmented gamma ABI
in a future patch.

v2: Reorder the patch as per Maarten's suggestion.

v3: Rebase

v4: Updated commit message with a note as per Matt's suggestion.

v5: No Change.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2a4d25c..c4d6b8d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -648,7 +648,8 @@
 	}, \
 	GEN(11), \
 	.ddb_size = 2048, \
-	.has_logical_ring_elsq = 1
+	.has_logical_ring_elsq = 1, \
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 
 static const struct intel_device_info intel_icelake_11_info = {
 	GEN11_FEATURES,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support

[Maarten Lankhorst]

Op 11-02-2019 om 10:26 schreef Uma Shankar:
> Add support for icl pipe degamma and gamma.
>
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
>
> v4: Fixed Matt's review comments.
>
> v5: Corrected macro alignment as per Jani Nikula's comments.
> Addressed Ville and Matt's  review comments.
>
> v6: Merged ICL degamma handling with GLK and dropped ICL
> degamma function as per Ville and Matt's comments.
>
> v7: updated gamma_mode state with pre csc gammma and post
> gamma enabling in intel_color_check to align with atomic.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>  drivers/gpu/drm/i915/intel_color.c | 32 ++++++++++++++++++++++++++++++--
>  2 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 11bf60d..13a207a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7111,11 +7111,13 @@ enum {
>  #define _GAMMA_MODE_A		0x4a480
>  #define _GAMMA_MODE_B		0x4ac80
>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
>  /* DMC/CSR */
>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 4e13286..0fcaae4 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -583,6 +583,28 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> +static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +
> +	glk_load_degamma_lut(crtc_state);
> +
> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
> +		i9xx_load_luts(crtc_state);
> +	} else {
> +		/* ToDo: Add support for multi segment gamma LUT */
> +		bdw_load_gamma_lut(crtc_state, 0);
> +
> +		/*
> +		 * Reset the index, otherwise it prevents the legacy
> +		 * palette to be written properly.
> +		 */
> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +	}
> +}
> +

Perhaps this write should be moved to bdw_load_gamma_lut() ?

Seems we might also fix the same missing write in glk_load_luts() then..

>  static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -772,7 +794,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  	    drm_color_lut_check(gamma_lut, gamma_tests))
>  		return -EINVAL;
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT |
> +					 PRE_CSC_GAMMA_ENABLE |
> +					 POST_CSC_GAMMA_ENABLE;
> +	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>  	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>  		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> @@ -796,7 +822,9 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>  		dev_priv->display.color_commit = i9xx_color_commit;
>  	} else {
> -		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> +		if (IS_ICELAKE(dev_priv))
> +			dev_priv->display.load_luts = icl_load_luts;
> +		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>  			dev_priv->display.load_luts = glk_load_luts;
>  		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>  			dev_priv->display.load_luts = broadwell_load_luts;

~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v8 5/5] drm/i915/icl: Add degamma and gamma lut size to gen11 caps

[Maarten Lankhorst]

Op 11-02-2019 om 10:26 schreef Uma Shankar:
> Add the degamma and gamma lut sizes to gen11 capability
> structure.
>
> Note: Currently this doesn't account for the extended range gamma
> entries and this will be addressed with new segmented gamma ABI
> in a future patch.
>
> v2: Reorder the patch as per Maarten's suggestion.
>
> v3: Rebase
>
> v4: Updated commit message with a note as per Matt's suggestion.
>
> v5: No Change.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2a4d25c..c4d6b8d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -648,7 +648,8 @@
>  	}, \
>  	GEN(11), \
>  	.ddb_size = 2048, \
> -	.has_logical_ring_elsq = 1
> +	.has_logical_ring_elsq = 1, \
> +	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>  
>  static const struct intel_device_info intel_icelake_11_info = {
>  	GEN11_FEATURES,

For rest of series:

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Add support for Gen 11 pipe color features (rev8)

[Patchwork]

== Series Details ==

Series: Add support for Gen 11 pipe color features (rev8)
URL   : https://patchwork.freedesktop.org/series/51408/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5585_full -> Patchwork_12190_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_12190_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12190_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12190_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_color@pipe-c-degamma:
    - shard-glk:          {SKIP} [fdo#109271] -> FAIL +4

  
Known issues
------------

  Here are the changes found in Patchwork_12190_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-write:
    - shard-snb:          PASS -> INCOMPLETE [fdo#105411]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
    - shard-glk:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-128x42-onscreen:
    - shard-glk:          NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +3

  * igt@kms_cursor_crc@cursor-alpha-opaque:
    - shard-apl:          PASS -> FAIL [fdo#109350]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-apl:          PASS -> FAIL [fdo#103167] +3

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-glk:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-apl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
    - shard-apl:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
    - shard-glk:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_setmode@basic:
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  
#### Possible fixes ####

  * igt@kms_busy@extended-pageflip-hang-newfb-render-c:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-glk:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-b-ctm-green-to-red:
    - shard-glk:          {SKIP} [fdo#109271] -> PASS +29

  * igt@kms_color@pipe-c-degamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * {igt@kms_flip@2x-flip-vs-suspend-interruptible}:
    - shard-glk:          INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-glk:          FAIL [fdo#103060] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-apl:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-glk:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-glk:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-apl:          DMESG-WARN [fdo#107886] / [fdo#109244] -> INCOMPLETE [fdo#103927] / [fdo#106886]

  * igt@kms_color@pipe-a-degamma:
    - shard-glk:          {SKIP} [fdo#109271] -> FAIL [fdo#108145]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (7 -> 5)
------------------------------

  Missing    (2): shard-skl shard-iclb 


Build changes
-------------

    * Linux: CI_DRM_5585 -> Patchwork_12190

  CI_DRM_5585: 07fae9b7c35201c498d9b65bcd822c5c4aa7c07a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4815: 947301563259726b65ce47d3a3fe37931ed42efe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12190: 46decd2ef418963d73373882342eb8f32150631c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12190/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support

[Shankar, Uma]

>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Monday, February 11, 2019 4:51 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma
>support
>
>Op 11-02-2019 om 10:26 schreef Uma Shankar:
>> Add support for icl pipe degamma and gamma.
>>
>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>> Maarten's comments.
>>
>> v3: Addressed Matt's review comments. Removed rmw patterns as
>> suggested by Matt.
>>
>> v4: Fixed Matt's review comments.
>>
>> v5: Corrected macro alignment as per Jani Nikula's comments.
>> Addressed Ville and Matt's  review comments.
>>
>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>> function as per Ville and Matt's comments.
>>
>> v7: updated gamma_mode state with pre csc gammma and post gamma
>> enabling in intel_color_check to align with atomic.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>>  drivers/gpu/drm/i915/intel_color.c | 32
>> ++++++++++++++++++++++++++++++--
>>  2 files changed, 37 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 11bf60d..13a207a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7111,11 +7111,13 @@ enum {
>>  #define _GAMMA_MODE_A		0x4a480
>>  #define _GAMMA_MODE_B		0x4ac80
>>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>_GAMMA_MODE_B)
>> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
>> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
>> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
>> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
>> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
>> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
>> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
>> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
>> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
>> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
>> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>
>>  /* DMC/CSR */
>>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 4e13286..0fcaae4 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -583,6 +583,28 @@ static void glk_load_luts(const struct intel_crtc_state
>*crtc_state)
>>  	}
>>  }
>>
>> +static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>> +
>> +	glk_load_degamma_lut(crtc_state);
>> +
>> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> +		i9xx_load_luts(crtc_state);
>> +	} else {
>> +		/* ToDo: Add support for multi segment gamma LUT */
>> +		bdw_load_gamma_lut(crtc_state, 0);
>> +
>> +		/*
>> +		 * Reset the index, otherwise it prevents the legacy
>> +		 * palette to be written properly.
>> +		 */
>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>> +	}
>> +}
>> +
>
>Perhaps this write should be moved to bdw_load_gamma_lut() ?
>
>Seems we might also fix the same missing write in glk_load_luts() then..

Thanks Maarten for reviewing this series.

Ok Sure, will move this to bdw_load_gamma_lut(). Can I add your RB on this patch also with this fix ?

Will send out the next version once you confirm.

Regards,
Uma Shankar

>
>>  static void cherryview_load_luts(const struct intel_crtc_state
>> *crtc_state)  {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> @@ -772,7 +794,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>>  	    drm_color_lut_check(gamma_lut, gamma_tests))
>>  		return -EINVAL;
>>
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (INTEL_GEN(dev_priv) >= 11)
>> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT |
>> +					 PRE_CSC_GAMMA_ENABLE |
>> +					 POST_CSC_GAMMA_ENABLE;
>> +	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>>  		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>>  	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>>  		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; @@ -
>796,7 +822,9 @@
>> void intel_color_init(struct intel_crtc *crtc)
>>
>>  		dev_priv->display.color_commit = i9xx_color_commit;
>>  	} else {
>> -		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>> +		if (IS_ICELAKE(dev_priv))
>> +			dev_priv->display.load_luts = icl_load_luts;
>> +		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>  			dev_priv->display.load_luts = glk_load_luts;
>>  		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>>  			dev_priv->display.load_luts = broadwell_load_luts;
>
>~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support

[Maarten Lankhorst]

Op 11-02-2019 om 14:01 schreef Shankar, Uma:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>> Sent: Monday, February 11, 2019 4:51 PM
>> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
>> <maarten.lankhorst@intel.com>
>> Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma
>> support
>>
>> Op 11-02-2019 om 10:26 schreef Uma Shankar:
>>> Add support for icl pipe degamma and gamma.
>>>
>>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>>> Maarten's comments.
>>>
>>> v3: Addressed Matt's review comments. Removed rmw patterns as
>>> suggested by Matt.
>>>
>>> v4: Fixed Matt's review comments.
>>>
>>> v5: Corrected macro alignment as per Jani Nikula's comments.
>>> Addressed Ville and Matt's  review comments.
>>>
>>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>>> function as per Ville and Matt's comments.
>>>
>>> v7: updated gamma_mode state with pre csc gammma and post gamma
>>> enabling in intel_color_check to align with atomic.
>>>
>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>>>  drivers/gpu/drm/i915/intel_color.c | 32
>>> ++++++++++++++++++++++++++++++--
>>>  2 files changed, 37 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h index 11bf60d..13a207a 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7111,11 +7111,13 @@ enum {
>>>  #define _GAMMA_MODE_A		0x4a480
>>>  #define _GAMMA_MODE_B		0x4ac80
>>>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>> _GAMMA_MODE_B)
>>> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
>>> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
>>> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
>>> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
>>> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
>>> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
>>> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
>>> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
>>> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
>>> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
>>> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>>
>>>  /* DMC/CSR */
>>>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>>> b/drivers/gpu/drm/i915/intel_color.c
>>> index 4e13286..0fcaae4 100644
>>> --- a/drivers/gpu/drm/i915/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/intel_color.c
>>> @@ -583,6 +583,28 @@ static void glk_load_luts(const struct intel_crtc_state
>> *crtc_state)
>>>  	}
>>>  }
>>>
>>> +static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>>> +{
>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>> +	enum pipe pipe = crtc->pipe;
>>> +
>>> +	glk_load_degamma_lut(crtc_state);
>>> +
>>> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
>>> +		i9xx_load_luts(crtc_state);
>>> +	} else {
>>> +		/* ToDo: Add support for multi segment gamma LUT */
>>> +		bdw_load_gamma_lut(crtc_state, 0);
>>> +
>>> +		/*
>>> +		 * Reset the index, otherwise it prevents the legacy
>>> +		 * palette to be written properly.
>>> +		 */
>>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>> +	}
>>> +}
>>> +
>> Perhaps this write should be moved to bdw_load_gamma_lut() ?
>>
>> Seems we might also fix the same missing write in glk_load_luts() then..
> Thanks Maarten for reviewing this series.
>
> Ok Sure, will move this to bdw_load_gamma_lut(). Can I add your RB on this patch also with this fix ?
>
> Will send out the next version once you confirm.
Yes. :)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support

[Shankar, Uma]

>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Monday, February 11, 2019 6:54 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma
>support
>
>Op 11-02-2019 om 14:01 schreef Shankar, Uma:
>>
>>> -----Original Message-----
>>> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>>> Sent: Monday, February 11, 2019 4:51 PM
>>> To: Shankar, Uma <uma.shankar@intel.com>;
>>> intel-gfx@lists.freedesktop.org
>>> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
>>> <maarten.lankhorst@intel.com>
>>> Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe degamma
>>> and gamma support
>>>
>>> Op 11-02-2019 om 10:26 schreef Uma Shankar:
>>>> Add support for icl pipe degamma and gamma.
>>>>
>>>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>>>> Maarten's comments.
>>>>
>>>> v3: Addressed Matt's review comments. Removed rmw patterns as
>>>> suggested by Matt.
>>>>
>>>> v4: Fixed Matt's review comments.
>>>>
>>>> v5: Corrected macro alignment as per Jani Nikula's comments.
>>>> Addressed Ville and Matt's  review comments.
>>>>
>>>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>>>> function as per Ville and Matt's comments.
>>>>
>>>> v7: updated gamma_mode state with pre csc gammma and post gamma
>>>> enabling in intel_color_check to align with atomic.
>>>>
>>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/i915_reg.h    | 12 +++++++-----
>>>>  drivers/gpu/drm/i915/intel_color.c | 32
>>>> ++++++++++++++++++++++++++++++--
>>>>  2 files changed, 37 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>> b/drivers/gpu/drm/i915/i915_reg.h index 11bf60d..13a207a 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -7111,11 +7111,13 @@ enum {
>>>>  #define _GAMMA_MODE_A		0x4a480
>>>>  #define _GAMMA_MODE_B		0x4ac80
>>>>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>>> _GAMMA_MODE_B)
>>>> -#define GAMMA_MODE_MODE_MASK	(3 << 0)
>>>> -#define GAMMA_MODE_MODE_8BIT	(0 << 0)
>>>> -#define GAMMA_MODE_MODE_10BIT	(1 << 0)
>>>> -#define GAMMA_MODE_MODE_12BIT	(2 << 0)
>>>> -#define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>>> +#define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
>>>> +#define  POST_CSC_GAMMA_ENABLE	(1 << 30)
>>>> +#define  GAMMA_MODE_MODE_MASK	(3 << 0)
>>>> +#define  GAMMA_MODE_MODE_8BIT	(0 << 0)
>>>> +#define  GAMMA_MODE_MODE_10BIT	(1 << 0)
>>>> +#define  GAMMA_MODE_MODE_12BIT	(2 << 0)
>>>> +#define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
>>>>
>>>>  /* DMC/CSR */
>>>>  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>>>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>>>> b/drivers/gpu/drm/i915/intel_color.c
>>>> index 4e13286..0fcaae4 100644
>>>> --- a/drivers/gpu/drm/i915/intel_color.c
>>>> +++ b/drivers/gpu/drm/i915/intel_color.c
>>>> @@ -583,6 +583,28 @@ static void glk_load_luts(const struct
>>>> intel_crtc_state
>>> *crtc_state)
>>>>  	}
>>>>  }
>>>>
>>>> +static void icl_load_luts(const struct intel_crtc_state
>>>> +*crtc_state) {
>>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>>> +	enum pipe pipe = crtc->pipe;
>>>> +
>>>> +	glk_load_degamma_lut(crtc_state);
>>>> +
>>>> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
>>>> +		i9xx_load_luts(crtc_state);
>>>> +	} else {
>>>> +		/* ToDo: Add support for multi segment gamma LUT */
>>>> +		bdw_load_gamma_lut(crtc_state, 0);
>>>> +
>>>> +		/*
>>>> +		 * Reset the index, otherwise it prevents the legacy
>>>> +		 * palette to be written properly.
>>>> +		 */
>>>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>>> +	}
>>>> +}
>>>> +
>>> Perhaps this write should be moved to bdw_load_gamma_lut() ?
>>>
>>> Seems we might also fix the same missing write in glk_load_luts() then..
>> Thanks Maarten for reviewing this series.
>>
>> Ok Sure, will move this to bdw_load_gamma_lut(). Can I add your RB on this patch
>also with this fix ?
>>
>> Will send out the next version once you confirm.
>Yes. :)

Thanks Maarten, sent the latest. 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx