[igt-dev] [RFC PATCH v9 0/5] new engine discovery interface

[igt-dev] [RFC PATCH v9 0/5] new engine discovery interface

[Andi Shyti via igt-dev]

Hi,

In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.

Andi

v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:
- all the allocation in gem_query have been made in stack, not
  anymore allocated dynamically.
- removed get/set_context as it was already implemented and I
  didn't know.
- renamed some functions and variables to hopefully more
  meaningful names.

V7 --> v8
=========
RFC v7: [9]
- all functions have been moved from lib/igt_gt.{c,h} and
  lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
  Chris)
- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
  be consistent with the '2' that indicates the new 'struct
  intel_execution_engine2' data structure.

V6 --> V7
=========
RFC v6: [8]
- a new patch has been added (patch 3) which adds a new
  requirement check through the igt_require_gem_engine_list()
  function. (thanks Chris) This function will initialize the
  engine list instead of the instead of igt_require_gem() as it
  was in v6
- all the ioctls have been wrapped (thanks Chris and Antonio) and
  new library functions have been added and assert the ioctls
- gem_init_engine_list() function returns the errno from the
  GETPARAM ioctl in order to be used as a requirement. (thanks
  Chris)
- fixed few requires/asserts
- The engine list "intel_active_engines2" is allocated of the
  number of engines instead of a political 64 (thanks Antonio).
- some parameter renaming in gem_has_ring_by_idx(). (thanks
  Chris).
- the original "intel_execution_engines2" has not been renamed,
  because it is used to create subtests before even executing any
  test/ioctl. By renaming it, some subtest generations failed.
  (thanks Petri)

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
  to figure otu whether the new interface has been implemented.
  This way the for_each_engine_ctx() is able to work with new and
  old kernel uapi (thanks Chris)

V4 --> V5
=========
RFC v4: [6]
- the engine list is now built in 'igt_require_gem()' instead of
  '__open_driver()' so that we keep this discovery method
  specific to the i915 driver (thanks Chris).
- All the query/setparam structures dynamic allocation based on
  the number of engines, now are politically allocated 64 times,
  to avoid extra ioctl calls that retrieve the engine number
  (thanks Chris)
- use igt_ioctl instead of ioctl (thanks Chris)
- allocate intel_execution_engines2 dynamically instead of
  statically (thanks Tvrtko)
- simplify the test in 'gem_exec_basic()' so that simply checks
  the presence of the engine instead of executing a buffer
  (thank Chris)
- a new patch has been added (patch 3) that extends the
  'gem_has_ring()' boolean function. The new version sets the
  index as it's mapped in the kernel.The previous function is now
  a wrapper to the new function.

V3 --> V4
=========
PATCH v3: [3]
- re-architectured the discovery mechanism based on Tvrtko's
  sugestion and reviews.. In this version the discovery is done
  during the device opening and stored in a NULL terminated
  array, which replaces the existing intel_execution_engines2
  that is mainly used as a reference.

V2 --> V3
=========
RFC v2: [2]
- removed a standalone gem_query_engines_demo test and added the
  exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).
- fixed most of Tvrtko's comments in [5], which consist in
  putting the mallocs igt_assert and ictls in igt_require and few
  refactoring (thanks Tvrtko).

V1 --> V2
=========
RFC v1: [1]
- added a demo test that simply queries the driver about the
  engines and executes a buffer (thanks Tvrtko)
- refactored the for_each_engine_ctx() macro so that what in the
  previous version was done by the "bind" function, now it's done
  in the first iteration. (Thanks Crhis)
- removed the "gem_has_ring_ctx()" because it was out of the
  scope.
- rename functions to more meaningful names

[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html

Andi Shyti (5):
  include/drm-uapi: import i915_drm.h header file
  lib/i915: add gem_query library
  lib/igt_gt: use for_each_engine2 to loop through engines
  lib: ioctl_wrappers: reach engines by index as well
  tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

 include/drm-uapi/i915_drm.h | 292 +++++++++++++++++++++++++++---------
 lib/Makefile.sources        |   2 +
 lib/i915/gem_query.c        | 184 +++++++++++++++++++++++
 lib/i915/gem_query.h        |  38 +++++
 lib/igt_gt.c                |   2 +-
 lib/igt_gt.h                |  10 +-
 lib/ioctl_wrappers.c        |   4 +-
 lib/ioctl_wrappers.h        |   4 +-
 lib/meson.build             |   1 +
 tests/i915/gem_exec_basic.c |  15 ++
 10 files changed, 477 insertions(+), 75 deletions(-)
 create mode 100644 lib/i915/gem_query.c
 create mode 100644 lib/i915/gem_query.h

-- 
2.20.1

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[igt-dev] [RFC PATCH v9 1/5] include/drm-uapi: import i915_drm.h header file

[Andi Shyti via igt-dev]

This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 include/drm-uapi/i915_drm.h | 292 +++++++++++++++++++++++++++---------
 1 file changed, 221 insertions(+), 71 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index d2792ab3640b..a9f6ebfba4af 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -102,6 +122,8 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -319,6 +341,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -367,6 +391,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -377,6 +402,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -476,6 +503,8 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_ENABLED	(1ul << 0)
 #define   I915_SCHEDULER_CAP_PRIORITY	(1ul << 1)
 #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
+#define   I915_SCHEDULER_CAP_PMU	(1ul << 3)
+#define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 4)
 
 #define I915_PARAM_HUC_STATUS		 42
 
@@ -972,7 +1001,7 @@ struct drm_i915_gem_execbuffer2 {
 	 * struct drm_i915_gem_exec_fence *fences.
 	 */
 	__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK              (7<<0)
+#define I915_EXEC_RING_MASK              (0x3f)
 #define I915_EXEC_DEFAULT                (0<<0)
 #define I915_EXEC_RENDER                 (1<<0)
 #define I915_EXEC_BSD                    (2<<0)
@@ -1120,32 +1149,34 @@ struct drm_i915_gem_busy {
 	 * as busy may become idle before the ioctl is completed.
 	 *
 	 * Furthermore, if the object is busy, which engine is busy is only
-	 * provided as a guide. There are race conditions which prevent the
-	 * report of which engines are busy from being always accurate.
-	 * However, the converse is not true. If the object is idle, the
-	 * result of the ioctl, that all engines are idle, is accurate.
+	 * provided as a guide and only indirectly by reporting its class
+	 * (there may be more than one engine in each class). There are race
+	 * conditions which prevent the report of which engines are busy from
+	 * being always accurate.  However, the converse is not true. If the
+	 * object is idle, the result of the ioctl, that all engines are idle,
+	 * is accurate.
 	 *
 	 * The returned dword is split into two fields to indicate both
-	 * the engines on which the object is being read, and the
-	 * engine on which it is currently being written (if any).
+	 * the engine classess on which the object is being read, and the
+	 * engine class on which it is currently being written (if any).
 	 *
 	 * The low word (bits 0:15) indicate if the object is being written
 	 * to by any engine (there can only be one, as the GEM implicit
 	 * synchronisation rules force writes to be serialised). Only the
-	 * engine for the last write is reported.
+	 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
+	 * 1 not 0 etc) for the last write is reported.
 	 *
-	 * The high word (bits 16:31) are a bitmask of which engines are
-	 * currently reading from the object. Multiple engines may be
+	 * The high word (bits 16:31) are a bitmask of which engines classes
+	 * are currently reading from the object. Multiple engines may be
 	 * reading from the object simultaneously.
 	 *
-	 * The value of each engine is the same as specified in the
-	 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
-	 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
-	 * the I915_EXEC_RENDER engine for execution, and so it is never
+	 * The value of each engine class is the same as specified in the
+	 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+	 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
 	 * reported as active itself. Some hardware may have parallel
 	 * execution engines, e.g. multiple media engines, which are
-	 * mapped to the same identifier in the EXECBUFFER2 ioctl and
-	 * so are not separately reported for busyness.
+	 * mapped to the same class identifier and so are not separately
+	 * reported for busyness.
 	 *
 	 * Caveat emptor:
 	 * Only the boolean result of this query is reliable; that is whether
@@ -1412,65 +1443,15 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
-	__u32 pad;
-};
-
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
-	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_GEM_CONTEXT_SINGLE_TIMELINE	0x1
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1491,6 +1472,38 @@ struct drm_i915_gem_context_param {
 	 * drm_i915_gem_context_param_sseu.
 	 */
 #define I915_CONTEXT_PARAM_SSEU		0x7
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retreived and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x8
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0x9
+
 	__u64 value;
 };
 
@@ -1553,6 +1566,98 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+};
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
@@ -1714,6 +1819,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 
 	/*
 	 * When set to zero by userspace, this is filled with the size of the
@@ -1811,6 +1917,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 class;
+
+	/** Engine instance number. */
+	__u16 instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

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[igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Andi Shyti via igt-dev]

The gem_query library is a set of functions that interface with
the query and getparam/setparam ioctls.

The entry point of the library is the
igt_require_gem_engine_list() which checks whether the ioctls are
implemented in the running kernel. If not the function skips the
test with -ENODEV.
On the other hand, if the interfaces are implemented, then, at
the first call it initializes an array of active engines (either
physical or virtual).

The global '*intel_active_engines2' points to the active engines
array or to the existing 'intel_execution_engines2'. The latter
is in preparation to the next patch.

The value of the 'intel_active_engines2' will be used in further
calls to check whether the above mentioned ioctls are implemented
without the need to call getparam().

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources |   2 +
 lib/i915/gem_query.c | 184 +++++++++++++++++++++++++++++++++++++++++++
 lib/i915/gem_query.h |  38 +++++++++
 lib/igt_gt.c         |   2 +-
 lib/igt_gt.h         |   2 +-
 lib/meson.build      |   1 +
 6 files changed, 227 insertions(+), 2 deletions(-)
 create mode 100644 lib/i915/gem_query.c
 create mode 100644 lib/i915/gem_query.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 808b9617eca2..9dd5e9242ae4 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -11,6 +11,8 @@ lib_source_list =	 	\
 	i915/gem_submission.h	\
 	i915/gem_ring.h	\
 	i915/gem_ring.c	\
+	i915/gem_query.c	\
+	i915/gem_query.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_query.c b/lib/i915/gem_query.c
new file mode 100644
index 000000000000..e55f6fd94543
--- /dev/null
+++ b/lib/i915/gem_query.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+
+#include "i915/gem_query.h"
+
+/*
+ * HACK: the '2 * sizeof(__u16)' is the size required for the flexible array
+ * inside 'struct i915_context_param_engines' that doesn't have a name and
+ * therefore cannot be referenced. It needs a name in the uapi.
+ */
+#define SIZEOF_CTX_PARAM	sizeof(struct i915_context_param_engines) + \
+					I915_EXEC_RING_MASK * \
+					2 * sizeof(__u16)
+#define SIZEOF_QUERY		sizeof(struct drm_i915_query_engine_info) + \
+					I915_EXEC_RING_MASK * \
+					sizeof(struct drm_i915_engine_info)
+
+struct intel_execution_engine2 *intel_active_engines2;
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if(igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+bool gem_can_query(void)
+{
+	return intel_active_engines2 != intel_execution_engines2;
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines)
+{
+	struct drm_i915_query query = { };
+	struct drm_i915_query_item item = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = SIZEOF_QUERY;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+void __set_ctx_engine_map(int fd, uint32_t ctx_id)
+{
+	int i;
+	__u8 ctx_param_buffer[SIZEOF_CTX_PARAM] = { };
+	const struct intel_execution_engine2 *e2;
+	struct drm_i915_gem_context_param ctx_param;
+	struct i915_context_param_engines *ctx_engine;
+
+	if (!gem_can_query())
+		return;
+
+	ctx_engine = (struct i915_context_param_engines *) ctx_param_buffer;
+
+	ctx_param.ctx_id = ctx_id;
+	ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
+	ctx_param.size = SIZEOF_CTX_PARAM;
+
+	ctx_engine->extensions = 0;
+	for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {
+		ctx_engine->class_instance[i].engine_class = e2->class;
+		ctx_engine->class_instance[i].engine_instance = e2->instance;
+	}
+
+	ctx_param.value = to_user_pointer(ctx_engine);
+
+	gem_context_set_param(fd, &ctx_param);
+}
+
+/*
+ * Initializes the list of engines.
+ *
+ * Returns:
+ *
+ *  - 0 in case of success and the get/set_param ioctls are implemented
+ *  - -ENODEV in case of success but I915_CONTEXT_PARAM_ENGINES is not
+ *    implemented in DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM ioctl.
+ *  - -errno in case of failure
+ */
+static int gem_init_engine_list(int fd)
+{
+	int i, ret;
+	unsigned char query_buffer[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine;
+	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	/* the list is already initialized */
+	if (intel_active_engines2)
+		return gem_can_query() ? 0 : -ENODEV;
+
+	/*
+	 * We check first whether the I915_CONTEXT_PARAM_ENGINES parameter is
+	 * supported by the running kernel. If not, __gem_context_get_param()
+	 * will return -EINVAL which, at this point, is not necessarily a
+	 * failure but it means that we need to fall beck to polling the engines
+	 * directly from intel_execution_engines2[].
+	 *
+	 * We will return -ENODEV with the meaning of missing interface
+	 */
+	ret = __gem_context_get_param(fd, &ctx_param);
+	if (ret) {
+		if (ret == -EINVAL) {
+			intel_active_engines2 = intel_execution_engines2;
+			return -ENODEV;
+		}
+		return ret;
+	}
+
+	query_engine = (struct drm_i915_query_engine_info *) query_buffer;
+	query_engines(fd, query_engine);
+
+	intel_active_engines2 = malloc((query_engine->num_engines + 1) *
+				       sizeof(*intel_active_engines2));
+	igt_assert(intel_active_engines2);
+
+	for (i = 0; i < query_engine->num_engines; i++) {
+		char *name;
+		int class = query_engine->engines[i].class;
+		int instance = query_engine->engines[i].instance;
+
+		igt_assert(class < ARRAY_SIZE(class_names) && class >= 0);
+		igt_assert(class_names[class]);
+
+		intel_active_engines2[i].class = class;
+		intel_active_engines2[i].instance = instance;
+
+		igt_assert(asprintf(&name, "%s%d",
+				    class_names[class], instance) > 0);
+		intel_active_engines2[i].name = name;
+	}
+
+	/* '0' value sentinel */
+	intel_active_engines2[i].name = NULL;
+	intel_active_engines2[i].class = 0;
+	intel_active_engines2[i].instance = 0;
+
+	return 0;
+}
+
+void igt_require_gem_engine_list(int fd)
+{
+	igt_require(!gem_init_engine_list(fd));
+}
diff --git a/lib/i915/gem_query.h b/lib/i915/gem_query.h
new file mode 100644
index 000000000000..263c7bd5c6e2
--- /dev/null
+++ b/lib/i915/gem_query.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_QUERY_H
+#define GEM_QUERY_H
+
+#include "igt_gt.h"
+
+void __set_ctx_engine_map(int fd, uint32_t ctx_id);
+
+bool gem_can_query(void);
+void gem_query(int fd, struct drm_i915_query *q);
+
+void igt_require_gem_engine_list(int fd);
+
+extern struct intel_execution_engine2 *intel_active_engines2;
+
+#endif /* GEM_QUEY_H */
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 646696727ee4..2bfd6417b5e5 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -577,7 +577,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	return true;
 }
 
-const struct intel_execution_engine2 intel_execution_engines2[] = {
+struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
 	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
 	{ "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..f4bd6c22a81a 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -91,7 +91,7 @@ bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
 bool gem_can_store_dword(int fd, unsigned int engine);
 
-extern const struct intel_execution_engine2 {
+extern struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
diff --git a/lib/meson.build b/lib/meson.build
index dd36f818033c..a703da2fb0d2 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -4,6 +4,7 @@ lib_sources = [
 	'i915/gem_scheduler.c',
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
+	'i915/gem_query.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

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[igt-dev] [RFC PATCH v9 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

[Andi Shyti via igt-dev]

'for_each_engine2()' defines a loop through the gpu engines.

It can work with both active and pre-defined engines.

In case we are looping through active engines (i.e. the running
kernel has the query and get/setparam ioctls), the
intel_active_engines2 points to an array that contains only the
list engines dynamically allocated after having interrogated the
driver.

While, if we are looping through pre-defined engines,
intel_active_engines2 points to the 'intel_execution_engines2'
array and works exactly as for_each_engine() but using the
new 'struct intel_execution_engine2' data type.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index f4bd6c22a81a..39e3a927191c 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -30,6 +30,8 @@
 
 #include "i915_drm.h"
 
+#include "i915/gem_query.h"
+
 void igt_require_hang_ring(int fd, int ring);
 
 typedef struct igt_hang {
@@ -86,6 +88,12 @@ extern const struct intel_execution_engine {
 	     e__++) \
 		for_if (gem_ring_has_physical_engine(fd__, flags__ = e__->exec_id | e__->flags))
 
+#define for_each_engine2(fd, ctx, e) \
+		for (__set_ctx_engine_map(fd, ctx_id), \
+		     e = intel_active_engines2; e->name; e++) \
+			for_if (gem_can_query() || \
+				gem_has_engine(fd, e->class, e->instance))
+
 bool gem_ring_is_physical_engine(int fd, unsigned int ring);
 bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
-- 
2.20.1

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[igt-dev] [RFC PATCH v9 4/5] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti via igt-dev]

With the new engine query method engines are reachable through
an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.

The previous 'gem_has_ring()' function becomes a wrapper to the new
'gem_context_has_engine()'.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/ioctl_wrappers.c | 4 +++-
 lib/ioctl_wrappers.h | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 404c2fbf9355..4303607f9279 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1465,7 +1465,7 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
@@ -1481,6 +1481,8 @@ bool gem_has_ring(int fd, unsigned ring)
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
 	execbuf.flags = ring;
+	execbuf.rsvd1 = ctx;
+
 	return __gem_execbuf(fd, &execbuf) == -ENOENT;
 }
 
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index b22b36b0b2dd..847380d69826 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -164,11 +164,13 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(fd, ring) gem_context_has_engine(fd, ring, 0)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;
-- 
2.20.1

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[igt-dev] [RFC PATCH v9 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

[Andi Shyti via igt-dev]

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with igt_require_gem_engine_list().

The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
Hi Chris,

one note on this. You didn't like the explicit iterator in the
for_each, while for me it makes quite sense to have it explicit
rather than hidden because, as I said in the previous review, the
user might want to use it.

At the end, we iterate for the iterating value, e.g. we do

	for (i = 0; i < N; i++)
		...

because we are interested in 'i' (of course, not always, but most
of the cases), at the same way we might be interested to the e2
value.

If we really want to hide e2, I would rather call it
for_each_mapped_idx() or similar.

Andi

 tests/i915/gem_exec_basic.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..a26eaff1cfe8 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,21 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-ctx") {
+		uint32_t ctx_id;
+		struct intel_execution_engine2 *e2;
+		int index_map = 0;
+
+		igt_require_gem_engine_list(fd);
+		ctx_id = gem_context_create(fd);
+
+		for_each_engine2(fd, ctx_id, e2)
+			igt_assert(gem_context_has_engine(fd, ++index_map,
+							  ctx_id));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.20.1

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Re: [igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Chris Wilson]

Quoting Andi Shyti (2019-02-14 00:44:42)
> The gem_query library is a set of functions that interface with
> the query and getparam/setparam ioctls.
> 
> The entry point of the library is the
> igt_require_gem_engine_list() which checks whether the ioctls are
> implemented in the running kernel. If not the function skips the
> test with -ENODEV.
> On the other hand, if the interfaces are implemented, then, at
> the first call it initializes an array of active engines (either
> physical or virtual).
> 
> The global '*intel_active_engines2' points to the active engines
> array or to the existing 'intel_execution_engines2'. The latter
> is in preparation to the next patch.
> 
> The value of the 'intel_active_engines2' will be used in further
> calls to check whether the above mentioned ioctls are implemented
> without the need to call getparam().
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  lib/Makefile.sources |   2 +
>  lib/i915/gem_query.c | 184 +++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/gem_query.h |  38 +++++++++
>  lib/igt_gt.c         |   2 +-
>  lib/igt_gt.h         |   2 +-
>  lib/meson.build      |   1 +
>  6 files changed, 227 insertions(+), 2 deletions(-)
>  create mode 100644 lib/i915/gem_query.c
>  create mode 100644 lib/i915/gem_query.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 808b9617eca2..9dd5e9242ae4 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -11,6 +11,8 @@ lib_source_list =             \
>         i915/gem_submission.h   \
>         i915/gem_ring.h \
>         i915/gem_ring.c \
> +       i915/gem_query.c        \
> +       i915/gem_query.h        \
>         i915_3d.h               \
>         i915_reg.h              \
>         i915_pciids.h           \
> diff --git a/lib/i915/gem_query.c b/lib/i915/gem_query.c
> new file mode 100644
> index 000000000000..e55f6fd94543
> --- /dev/null
> +++ b/lib/i915/gem_query.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "ioctl_wrappers.h"
> +#include "drmtest.h"
> +
> +#include "i915/gem_query.h"
> +
> +/*
> + * HACK: the '2 * sizeof(__u16)' is the size required for the flexible array
> + * inside 'struct i915_context_param_engines' that doesn't have a name and
> + * therefore cannot be referenced. It needs a name in the uapi.
> + */

It's not going to get one until you raise the point in review of the
uAPI. It doesn't though, you can use sizeof on the unnamed member.

> +#define SIZEOF_CTX_PARAM       sizeof(struct i915_context_param_engines) + \
> +                                       I915_EXEC_RING_MASK * \
> +                                       2 * sizeof(__u16)

For example:

SIZEOF_CTX_PARAM offsetofend(struct i915_context_param_engines,
			     class_instance[I915_EXEC_RING_MASK + 1])

To make it generic though, it needs __attribute__((packed))

(If the maximum index is I915_EXEC_RING_MASK, we need
I915_EXEC_RING_MASK + 1 storage.)

> +#define SIZEOF_QUERY           sizeof(struct drm_i915_query_engine_info) + \
> +                                       I915_EXEC_RING_MASK * \
> +                                       sizeof(struct drm_i915_engine_info)
> +
> +struct intel_execution_engine2 *intel_active_engines2;
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +       int err = 0;
> +
> +       if(igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
            ^ kernel coding style applies (missed space)
> +               err = -errno;

> +       errno = 0;
> +       return err;
> +}
> +
> +void gem_query(int fd, struct drm_i915_query *q)
> +{
> +       igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +bool gem_can_query(void)

Still nothing to do with query per-se...

gem_has_engine_topology() ?

> +{
> +       return intel_active_engines2 != intel_execution_engines2;
> +}
> +
> +static void query_engines(int fd,
> +                         struct drm_i915_query_engine_info *query_engines)
> +{
> +       struct drm_i915_query query = { };
> +       struct drm_i915_query_item item = { };
> +
> +       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +       query.items_ptr = to_user_pointer(&item);
> +       query.num_items = 1;
> +       item.length = SIZEOF_QUERY;
> +
> +       item.data_ptr = to_user_pointer(query_engines);
> +
> +       gem_query(fd, &query);
> +}
> +
> +void __set_ctx_engine_map(int fd, uint32_t ctx_id)

We've drifted out of the domain of i915/gem_query.c into
i915/gem_engine.c You could even argue we want to keep gem_engine.c for
lower level interactions, and say gem_engine_topology.c for the details of
the layout. Hmm, I like?

> +{
> +       int i;

Kernel coding style is to order variable lines by length, longest first;
unless there is a clear reason why not to.

> +       __u8 ctx_param_buffer[SIZEOF_CTX_PARAM] = { };

s/__u8/uint8_t/

It just a boring stack buf, so call it buf.

> +       const struct intel_execution_engine2 *e2;
> +       struct drm_i915_gem_context_param ctx_param;
> +       struct i915_context_param_engines *ctx_engine;
> +
> +       if (!gem_can_query())
> +               return;
> +
> +       ctx_engine = (struct i915_context_param_engines *) ctx_param_buffer;
> +
> +       ctx_param.ctx_id = ctx_id;
> +       ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
> +       ctx_param.size = SIZEOF_CTX_PARAM;

Not quite; size is used to determine the number of engines, this makes a
large array with upto 5 real engines followed by rcs0 repeated ~60
times. Interesting ;)

> +       ctx_engine->extensions = 0;
> +       for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {

You should at least have an assert you don't overflow your assumptions.

> +               ctx_engine->class_instance[i].engine_class = e2->class;
> +               ctx_engine->class_instance[i].engine_instance = e2->instance;
> +       }

> +       ctx_param.value = to_user_pointer(ctx_engine);
ctx_param.size = offsetof(typeof(*ctx_engine), class_instance[i]);

* quickly adds the packed attribute

> +
> +       gem_context_set_param(fd, &ctx_param);
> +}
> +
> +/*
> + * Initializes the list of engines.
> + *
> + * Returns:
> + *
> + *  - 0 in case of success and the get/set_param ioctls are implemented
> + *  - -ENODEV in case of success but I915_CONTEXT_PARAM_ENGINES is not
> + *    implemented in DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM ioctl.
> + *  - -errno in case of failure
> + */
> +static int gem_init_engine_list(int fd)
> +{
> +       int i, ret;
> +       unsigned char query_buffer[SIZEOF_QUERY] = { };
> +       struct drm_i915_query_engine_info *query_engine;
> +       const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> +       struct drm_i915_gem_context_param ctx_param = {
> +               .param = I915_CONTEXT_PARAM_ENGINES,
> +       };
> +
> +       /* the list is already initialized */
> +       if (intel_active_engines2)
> +               return gem_can_query() ? 0 : -ENODEV;
> +
> +       /*
> +        * We check first whether the I915_CONTEXT_PARAM_ENGINES parameter is
> +        * supported by the running kernel. If not, __gem_context_get_param()
> +        * will return -EINVAL which, at this point, is not necessarily a
> +        * failure but it means that we need to fall beck to polling the engines
> +        * directly from intel_execution_engines2[].
> +        *
> +        * We will return -ENODEV with the meaning of missing interface
> +        */
> +       ret = __gem_context_get_param(fd, &ctx_param);
> +       if (ret) {
> +               if (ret == -EINVAL) {

Just

if (__gem_context_get_param()) {
	intel_active_engines2 = intel_execution_engines2;
	return -ENODEV;
}

This be library code, so you define the interface; as opposed to test
code where we demand certain responses from the kernel.

> +       query_engine = (struct drm_i915_query_engine_info *) query_buffer;
> +       query_engines(fd, query_engine);
> +
> +       intel_active_engines2 = malloc((query_engine->num_engines + 1) *
> +                                      sizeof(*intel_active_engines2));

> +       igt_assert(intel_active_engines2);
> +
> +       for (i = 0; i < query_engine->num_engines; i++) {
> +               char *name;
> +               int class = query_engine->engines[i].class;
> +               int instance = query_engine->engines[i].instance;
> +
> +               igt_assert(class < ARRAY_SIZE(class_names) && class >= 0);
> +               igt_assert(class_names[class]);

Be future proof;

if ((unsigned)class >= ARRAY_SIZE() || !class_names[class])
	tmpl = "xxx"; // or "unk" I think I've seen Tvrtko use
else
	tmpl = class_names[class];

Bonus points to include class-id in tmpl in case there's more than one!

> +               intel_active_engines2[i].class = class;
> +               intel_active_engines2[i].instance = instance;
> +
> +               igt_assert(asprintf(&name, "%s%d",
> +                                   class_names[class], instance) > 0);
> +               intel_active_engines2[i].name = name;
> +       }
> +
> +       /* '0' value sentinel */
Which bit?
class_instance = (0, 0) is valid (rcs0)

/* Use .name=NULL as a sentinel */
> +       intel_active_engines2[i].name = NULL;
> +       intel_active_engines2[i].class = 0;
> +       intel_active_engines2[i].instance = 0;
> +
> +       return 0;
> +}
> +
> +void igt_require_gem_engine_list(int fd)
> +{
> +       igt_require(!gem_init_engine_list(fd));
> +}
> diff --git a/lib/i915/gem_query.h b/lib/i915/gem_query.h
> new file mode 100644
> index 000000000000..263c7bd5c6e2
> --- /dev/null
> +++ b/lib/i915/gem_query.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_QUERY_H
> +#define GEM_QUERY_H
> +
> +#include "igt_gt.h"

For intel_execution_engine2?

Just a forward decl will do.

> +void __set_ctx_engine_map(int fd, uint32_t ctx_id);

One day you'll find a more fitting name. Hint, this isn't part of the
"set" infrastructure.

> +bool gem_can_query(void);
> +void gem_query(int fd, struct drm_i915_query *q);
> +
> +void igt_require_gem_engine_list(int fd);
> +
> +extern struct intel_execution_engine2 *intel_active_engines2;

But I'm voting this extern should be in gem_engine_topology.[ch]
-Chris
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Re: [igt-dev] [RFC PATCH v9 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

[Chris Wilson]

Quoting Andi Shyti (2019-02-14 00:44:43)
> 'for_each_engine2()' defines a loop through the gpu engines.
> 
> It can work with both active and pre-defined engines.
> 
> In case we are looping through active engines (i.e. the running
> kernel has the query and get/setparam ioctls), the
> intel_active_engines2 points to an array that contains only the
> list engines dynamically allocated after having interrogated the
> driver.
> 
> While, if we are looping through pre-defined engines,
> intel_active_engines2 points to the 'intel_execution_engines2'
> array and works exactly as for_each_engine() but using the
> new 'struct intel_execution_engine2' data type.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  lib/igt_gt.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index f4bd6c22a81a..39e3a927191c 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -30,6 +30,8 @@
>  
>  #include "i915_drm.h"
>  
> +#include "i915/gem_query.h"
> +
>  void igt_require_hang_ring(int fd, int ring);
>  
>  typedef struct igt_hang {
> @@ -86,6 +88,12 @@ extern const struct intel_execution_engine {
>              e__++) \
>                 for_if (gem_ring_has_physical_engine(fd__, flags__ = e__->exec_id | e__->flags))
>  
> +#define for_each_engine2(fd, ctx, e) \
> +               for (__set_ctx_engine_map(fd, ctx_id), \
> +                    e = intel_active_engines2; e->name; e++) \

#define for_each_ctx_engine(fd, ctx, e__) \
	for ((e__) = gem_context_get_engines((fd), (ctx)); (e__)->name; (e__)++)

Phrased like that, there is no need for extraneous entries in the array.
-Chris
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Re: [igt-dev] [RFC PATCH v9 4/5] lib: ioctl_wrappers: reach engines by index as well

[Chris Wilson]

Quoting Andi Shyti (2019-02-14 00:44:44)
> With the new engine query method engines are reachable through
> an index and context they are combined with.
> 
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> 
> The previous 'gem_has_ring()' function becomes a wrapper to the new
> 'gem_context_has_engine()'.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  lib/ioctl_wrappers.c | 4 +++-
>  lib/ioctl_wrappers.h | 4 +++-
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 404c2fbf9355..4303607f9279 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1465,7 +1465,7 @@ void igt_require_gem(int fd)
>         igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
>  }
>  
> -bool gem_has_ring(int fd, unsigned ring)
> +bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)

Remember to lift it out of ioctl_wrappers, and as this operates on the
context (given the name), the context should be a primary argument.
-Chris
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Re: [igt-dev] [RFC PATCH v9 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

[Chris Wilson]

Quoting Andi Shyti (2019-02-14 00:44:45)
> The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
> test. The main goal is to reach the engines by using
> the new uapi interfacing with igt_require_gem_engine_list().
> 
> The "exec-ctx" subtest simply gets the list of engines, binds
> them to a context and executes a buffer. This is done through a
> new "for_each_engine2" loop which iterates through the
> engines.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
> Hi Chris,
> 
> one note on this. You didn't like the explicit iterator in the
> for_each, while for me it makes quite sense to have it explicit
> rather than hidden because, as I said in the previous review, the
> user might want to use it.
> 
> At the end, we iterate for the iterating value, e.g. we do
> 
>         for (i = 0; i < N; i++)
>                 ...
> 
> because we are interested in 'i' (of course, not always, but most
> of the cases), at the same way we might be interested to the e2
> value.
> 
> If we really want to hide e2, I would rather call it
> for_each_mapped_idx() or similar.
> 
> Andi
> 
>  tests/i915/gem_exec_basic.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
> index dcb83864b1c1..a26eaff1cfe8 100644
> --- a/tests/i915/gem_exec_basic.c
> +++ b/tests/i915/gem_exec_basic.c
> @@ -135,6 +135,21 @@ igt_main
>                         gtt(fd, e->exec_id | e->flags);
>         }
>  
> +       igt_subtest("exec-ctx") {
> +               uint32_t ctx_id;
> +               struct intel_execution_engine2 *e2;
> +               int index_map = 0;
> +
> +               igt_require_gem_engine_list(fd);

This test is for the iterator, it needs to work regardless of having
SET_ENGINES.

Logging which interface it is using is useful.

> +               ctx_id = gem_context_create(fd);
> +
> +               for_each_engine2(fd, ctx_id, e2)
> +                       igt_assert(gem_context_has_engine(fd, ++index_map,
> +                                                         ctx_id));

Do you see why it must be using only the iterator now? As that's what I
want tested! gem_ctx_engines is checking the SET_ENGINES interface and
making sure execbufs on ctx->engines[] map back to the old uabi. What we
need here is a simple sanitycheck that the for_each_ctx_engine() does
not explode.
-Chris
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[igt-dev] ✗ Fi.CI.BAT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/56638/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5599 -> IGTPW_2401
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2401 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2401, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56638/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2401:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7567u:       PASS -> FAIL +2

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_reloc@basic-write-gtt:
    - {fi-icl-y}:         NOTRUN -> INCOMPLETE

  
Known issues
------------

  Here are the changes found in IGTPW_2401 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]

  * igt@gem_exec_suspend@basic-s3:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602] +1

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-skl-6700hq:      PASS -> DMESG-WARN [fdo#105998]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-kbl-7567u:       PASS -> DMESG-FAIL [fdo#105079]

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#108529]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] -> PASS

  * igt@i915_selftest@live_workarounds:
    - {fi-icl-u3}:        INCOMPLETE [fdo#109626] -> PASS
    - {fi-icl-u2}:        INCOMPLETE [fdo#109626] -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       DMESG-FAIL [fdo#109627] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS +2

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109226]: https://bugs.freedesktop.org/show_bug.cgi?id=109226
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
  [fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
  [fdo#109627]: https://bugs.freedesktop.org/show_bug.cgi?id=109627


Participating hosts (43 -> 44)
------------------------------

  Additional (7): fi-skl-6260u fi-whl-u fi-ivb-3770 fi-icl-y fi-kbl-7560u fi-bsw-kefka fi-snb-2600 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4824 -> IGTPW_2401

  CI_DRM_5599: 39119c9b385742d49446c25d6902864a60eda6b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2401: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2401/
  IGT_4824: e55d439a9ba744227fb4c9d727338276b78871d4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@exec-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2401/
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Re: [igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Andi Shyti via igt-dev]

Hi Chris,

> > +/*
> > + * HACK: the '2 * sizeof(__u16)' is the size required for the flexible array
> > + * inside 'struct i915_context_param_engines' that doesn't have a name and
> > + * therefore cannot be referenced. It needs a name in the uapi.
> > + */
> 
> It's not going to get one until you raise the point in review of the
> uAPI. It doesn't though, you can use sizeof on the unnamed member.
> 
> > +#define SIZEOF_CTX_PARAM       sizeof(struct i915_context_param_engines) + \
> > +                                       I915_EXEC_RING_MASK * \
> > +                                       2 * sizeof(__u16)
> 
> For example:
> 
> SIZEOF_CTX_PARAM offsetofend(struct i915_context_param_engines,
> 			     class_instance[I915_EXEC_RING_MASK + 1])
> 
> To make it generic though, it needs __attribute__((packed))

yeah! makes sense.

> (If the maximum index is I915_EXEC_RING_MASK, we need
> I915_EXEC_RING_MASK + 1 storage.)

Yes, I didn't add the '+ 1' because in the driver you do:

	if (set.nengine == 0 || set.nengine > I915_EXEC_RING_MASK)
		return -EINVAL;

> > +#define SIZEOF_QUERY           sizeof(struct drm_i915_query_engine_info) + \
> > +                                       I915_EXEC_RING_MASK * \
> > +                                       sizeof(struct drm_i915_engine_info)
> > +
> > +struct intel_execution_engine2 *intel_active_engines2;
> > +
> > +static int __gem_query(int fd, struct drm_i915_query *q)
> > +{
> > +       int err = 0;
> > +
> > +       if(igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
>             ^ kernel coding style applies (missed space)

yes :) I didn't notice, it should be some late night coding
leftover, we should add checkpatch.

> > +bool gem_can_query(void)
> 
> Still nothing to do with query per-se...
> 
> gem_has_engine_topology() ?

OK, sure.

> > +void __set_ctx_engine_map(int fd, uint32_t ctx_id)
> 
> We've drifted out of the domain of i915/gem_query.c into
> i915/gem_engine.c You could even argue we want to keep gem_engine.c for
> lower level interactions, and say gem_engine_topology.c for the details of
> the layout. Hmm, I like?

OK, I can add a new API

> > +{
> > +       int i;
> 
> Kernel coding style is to order variable lines by length, longest first;
> unless there is a clear reason why not to.

It's a community based preference, each maintainer has his own
opinion on variable ordering. I just place it in the order that
they come to my mind, until the maintainer dictates the rule.

> > +       __u8 ctx_param_buffer[SIZEOF_CTX_PARAM] = { };
> 
> s/__u8/uint8_t/
> 
> It just a boring stack buf, so call it buf.

OK.

> > +       ctx_param.ctx_id = ctx_id;
> > +       ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
> > +       ctx_param.size = SIZEOF_CTX_PARAM;
> 
> Not quite; size is used to determine the number of engines, this makes a
> large array with upto 5 real engines followed by rcs0 repeated ~60
> times. Interesting ;)

yes, need to save the engine count somewhere. In a previous
series I was 'for(...);' but then removed it...

> > +       ctx_engine->extensions = 0;
> > +       for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {
> 
> You should at least have an assert you don't overflow your assumptions.

yes, this happened quite many times last night while I was fixing
the code and i promised myself to add the assert, but eventually
I forgot.

> > +               ctx_engine->class_instance[i].engine_class = e2->class;
> > +               ctx_engine->class_instance[i].engine_instance = e2->instance;
> > +       }
> 
> > +       ctx_param.value = to_user_pointer(ctx_engine);

> ctx_param.size = offsetof(typeof(*ctx_engine), class_instance[i]);
> 
> * quickly adds the packed attribute

... neat!

> > +       ret = __gem_context_get_param(fd, &ctx_param);
> > +       if (ret) {
> > +               if (ret == -EINVAL) {
> 
> Just
> 
> if (__gem_context_get_param()) {
> 	intel_active_engines2 = intel_execution_engines2;
> 	return -ENODEV;
> }
> 
> This be library code, so you define the interface; as opposed to test
> code where we demand certain responses from the kernel.

we don't need other -errnos? OK!

> > +       for (i = 0; i < query_engine->num_engines; i++) {
> > +               char *name;
> > +               int class = query_engine->engines[i].class;
> > +               int instance = query_engine->engines[i].instance;
> > +
> > +               igt_assert(class < ARRAY_SIZE(class_names) && class >= 0);
> > +               igt_assert(class_names[class]);
> 
> Be future proof;
> 
> if ((unsigned)class >= ARRAY_SIZE() || !class_names[class])
> 	tmpl = "xxx"; // or "unk" I think I've seen Tvrtko use
> else
> 	tmpl = class_names[class];
> 
> Bonus points to include class-id in tmpl in case there's more than one!

OK.

> > +               intel_active_engines2[i].class = class;
> > +               intel_active_engines2[i].instance = instance;
> > +
> > +               igt_assert(asprintf(&name, "%s%d",
> > +                                   class_names[class], instance) > 0);
> > +               intel_active_engines2[i].name = name;
> > +       }
> > +
> > +       /* '0' value sentinel */
> Which bit?
> class_instance = (0, 0) is valid (rcs0)
> 
> /* Use .name=NULL as a sentinel */

Sure.

> > +#ifndef GEM_QUERY_H
> > +#define GEM_QUERY_H
> > +
> > +#include "igt_gt.h"
> 
> For intel_execution_engine2?
> 
> Just a forward decl will do.
> 
> > +void __set_ctx_engine_map(int fd, uint32_t ctx_id);
> 
> One day you'll find a more fitting name. Hint, this isn't part of the
> "set" infrastructure.
> 
> > +bool gem_can_query(void);
> > +void gem_query(int fd, struct drm_i915_query *q);
> > +
> > +void igt_require_gem_engine_list(int fd);
> > +
> > +extern struct intel_execution_engine2 *intel_active_engines2;
> 
> But I'm voting this extern should be in gem_engine_topology.[ch]

OK, I will add the gem_engine_topology.[ch]

Thanks,
Andi
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Re: [igt-dev] [RFC PATCH v9 4/5] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti via igt-dev]

Hi Chris,

> > -bool gem_has_ring(int fd, unsigned ring)
> > +bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
> 
> Remember to lift it out of ioctl_wrappers, and as this operates on the
> context (given the name), the context should be a primary argument.

All right, I'll put 'gem_context_has_engine()' in
lib/i915/gem_context.c.

Andi
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Re: [igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Chris Wilson]

Quoting Andi Shyti (2019-02-14 13:02:58)
> Hi Chris,
> 
> > > +/*
> > > + * HACK: the '2 * sizeof(__u16)' is the size required for the flexible array
> > > + * inside 'struct i915_context_param_engines' that doesn't have a name and
> > > + * therefore cannot be referenced. It needs a name in the uapi.
> > > + */
> > 
> > It's not going to get one until you raise the point in review of the
> > uAPI. It doesn't though, you can use sizeof on the unnamed member.
> > 
> > > +#define SIZEOF_CTX_PARAM       sizeof(struct i915_context_param_engines) + \
> > > +                                       I915_EXEC_RING_MASK * \
> > > +                                       2 * sizeof(__u16)
> > 
> > For example:
> > 
> > SIZEOF_CTX_PARAM offsetofend(struct i915_context_param_engines,
> >                            class_instance[I915_EXEC_RING_MASK + 1])
> > 
> > To make it generic though, it needs __attribute__((packed))
> 
> yeah! makes sense.
> 
> > (If the maximum index is I915_EXEC_RING_MASK, we need
> > I915_EXEC_RING_MASK + 1 storage.)
> 
> Yes, I didn't add the '+ 1' because in the driver you do:
> 
>         if (set.nengine == 0 || set.nengine > I915_EXEC_RING_MASK)
>                 return -EINVAL;

Indeed that needs to be +1 since we aren't reserving slot 0 anymore.
> 
> > > +       ret = __gem_context_get_param(fd, &ctx_param);
> > > +       if (ret) {
> > > +               if (ret == -EINVAL) {
> > 
> > Just
> > 
> > if (__gem_context_get_param()) {
> >       intel_active_engines2 = intel_execution_engines2;
> >       return -ENODEV;
> > }
> > 
> > This be library code, so you define the interface; as opposed to test
> > code where we demand certain responses from the kernel.
> 
> we don't need other -errnos? OK!

I haven't checked if we need that error either ;)

I think I have a slightly different idea for the for_each_engine loop
anyway.
-Chris
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Re: [igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Petri Latvala via igt-dev]

On Thu, Feb 14, 2019 at 02:44:42AM +0200, Andi Shyti via igt-dev wrote:
> diff --git a/lib/i915/gem_query.c b/lib/i915/gem_query.c
> new file mode 100644
> index 000000000000..e55f6fd94543
> --- /dev/null
> +++ b/lib/i915/gem_query.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2017 Intel Corporation


2017?


-- 
Petri Latvala
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Re: [igt-dev] [RFC PATCH v9 2/5] lib/i915: add gem_query library

[Chris Wilson]

Quoting Petri Latvala via igt-dev (2019-02-15 09:59:37)
> On Thu, Feb 14, 2019 at 02:44:42AM +0200, Andi Shyti via igt-dev wrote:
> > diff --git a/lib/i915/gem_query.c b/lib/i915/gem_query.c
> > new file mode 100644
> > index 000000000000..e55f6fd94543
> > --- /dev/null
> > +++ b/lib/i915/gem_query.c
> > @@ -0,0 +1,184 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> 
> 
> 2017?

* still living in 2009.
-Chris
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