* [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
@ 2019-02-15 19:22 Richard Henderson
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv Richard Henderson
` (16 more replies)
0 siblings, 17 replies; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Changes since v3:
Rebased on master, and combined the JSConv and FHM patch sets.
There were a number of patch conflicts which needed fixing up.
Changes since v2:
Patch 2 splits out vfp_helper.c, which I wrote for something else.
But while rebasing it occured to me that helper_vjcvt is better placed
in vfp_helper.c than op_helper.c, so why not include it here and now.
Patch 3 corresponds to the v2 patch 1, but totally rewritten. What
I missed the first time around is that register Sn is encoded differenly
than Dn, so merely setting dp = 0 doesn't help because we've already
decoded the register number incorrectly. Therefore, replace some really
ugly if conditions and set some variables as appropriate.
Patch 4 is adjusted to match the change in decode from patch 2, and
putting the aa32 flags in the right place.
r~
Richard Henderson (8):
target/arm: Restructure disas_fp_int_conv
target/arm: Split out vfp_helper.c
target/arm: Rearrange Floating-point data-processing (2 regs)
target/arm: Implement ARMv8.3-JSConv
target/arm: Add helpers for FMLAL
target/arm: Implement FMLAL and FMLSL for aarch64
target/arm: Implement VFMAL and VFMSL for aarch32
target/arm: Enable ARMv8.2-FHM for -cpu max
target/arm/cpu.h | 20 +
target/arm/helper.h | 8 +
target/arm/cpu.c | 2 +
target/arm/cpu64.c | 4 +
target/arm/helper.c | 1062 --------------------------------
target/arm/translate-a64.c | 170 ++++--
target/arm/translate.c | 340 ++++++-----
target/arm/vec_helper.c | 114 ++++
target/arm/vfp_helper.c | 1176 ++++++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 2 +-
10 files changed, 1644 insertions(+), 1254 deletions(-)
create mode 100644 target/arm/vfp_helper.c
--
2.17.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
@ 2019-02-15 19:22 ` Richard Henderson
2019-02-19 15:28 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c Richard Henderson
` (15 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
For opcodes 0-5, move some if conditions into the structure
of a switch statement. For opcodes 6 & 7, decode everything
at once with a second switch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 94 ++++++++++++++++++++------------------
1 file changed, 49 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index af8e4fd4be..dbce24fe32 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6541,68 +6541,72 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
int type = extract32(insn, 22, 2);
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
+ bool itof = false;
if (sbit) {
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
- if (opcode > 5) {
- /* FMOV */
- bool itof = opcode & 1;
-
- if (rmode >= 2) {
- unallocated_encoding(s);
- return;
- }
-
- switch (sf << 3 | type << 1 | rmode) {
- case 0x0: /* 32 bit */
- case 0xa: /* 64 bit */
- case 0xd: /* 64 bit to top half of quad */
- break;
- case 0x6: /* 16-bit float, 32-bit int */
- case 0xe: /* 16-bit float, 64-bit int */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
- }
- /* fallthru */
- default:
- /* all other sf/type/rmode combinations are invalid */
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
- handle_fmov(s, rd, rn, type, itof);
- } else {
- /* actual FP conversions */
- bool itof = extract32(opcode, 1, 1);
-
- if (rmode != 0 && opcode > 1) {
- unallocated_encoding(s);
- return;
+ switch (opcode) {
+ case 2: /* SCVTF */
+ case 3: /* UCVTF */
+ itof = true;
+ /* fallthru */
+ case 4: /* FCVTAS */
+ case 5: /* FCVTAU */
+ if (rmode != 0) {
+ goto do_unallocated;
}
+ /* fallthru */
+ case 0: /* FCVT[NPMZ]S */
+ case 1: /* FCVT[NPMZ]U */
switch (type) {
case 0: /* float32 */
case 1: /* float64 */
break;
case 3: /* float16 */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
}
- /* fallthru */
+ break;
default:
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
-
if (!fp_access_check(s)) {
return;
}
handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
+ break;
+
+ default:
+ switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
+ case 0b01100110: /* FMOV half <-> 32-bit int */
+ case 0b01100111:
+ case 0b11100110: /* FMOV half <-> 64-bit int */
+ case 0b11100111:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
+ }
+ /* fallthru */
+ case 0b00000110: /* FMOV 32-bit */
+ case 0b00000111:
+ case 0b10100110: /* FMOV 64-bit */
+ case 0b10100111:
+ case 0b11001110: /* FMOV top half of 128-bit */
+ case 0b11001111:
+ if (!fp_access_check(s)) {
+ return;
+ }
+ itof = opcode & 1;
+ handle_fmov(s, rd, rn, type, itof);
+ break;
+
+ default:
+ do_unallocated:
+ unallocated_encoding(s);
+ return;
+ }
+ break;
}
}
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv Richard Henderson
@ 2019-02-15 19:22 ` Richard Henderson
2019-02-19 15:32 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs) Richard Henderson
` (14 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Move all of the fp helpers out of helper.c into a new file.
This is code movement only. Since helper.c has no copyright
header, take the one from cpu.h for the new file.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 1062 -------------------------------------
target/arm/vfp_helper.c | 1088 ++++++++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 2 +-
3 files changed, 1089 insertions(+), 1063 deletions(-)
create mode 100644 target/arm/vfp_helper.c
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 55e9b77bb1..9fd97fbf31 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12678,1068 +12678,6 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
return (a & mask) | (b & ~mask);
}
-/* VFP support. We follow the convention used for VFP instructions:
- Single precision routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to vfp form. */
-static inline int vfp_exceptbits_from_host(int host_bits)
-{
- int target_bits = 0;
-
- if (host_bits & float_flag_invalid)
- target_bits |= 1;
- if (host_bits & float_flag_divbyzero)
- target_bits |= 2;
- if (host_bits & float_flag_overflow)
- target_bits |= 4;
- if (host_bits & (float_flag_underflow | float_flag_output_denormal))
- target_bits |= 8;
- if (host_bits & float_flag_inexact)
- target_bits |= 0x10;
- if (host_bits & float_flag_input_denormal)
- target_bits |= 0x80;
- return target_bits;
-}
-
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
-{
- uint32_t i, fpscr;
-
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
- | (env->vfp.vec_len << 16)
- | (env->vfp.vec_stride << 20);
-
- i = get_float_exception_flags(&env->vfp.fp_status);
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
- /* FZ16 does not generate an input denormal exception. */
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
- & ~float_flag_input_denormal);
- fpscr |= vfp_exceptbits_from_host(i);
-
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
- fpscr |= i ? FPCR_QC : 0;
-
- return fpscr;
-}
-
-uint32_t vfp_get_fpscr(CPUARMState *env)
-{
- return HELPER(vfp_get_fpscr)(env);
-}
-
-/* Convert vfp exception flags to target form. */
-static inline int vfp_exceptbits_to_host(int target_bits)
-{
- int host_bits = 0;
-
- if (target_bits & 1)
- host_bits |= float_flag_invalid;
- if (target_bits & 2)
- host_bits |= float_flag_divbyzero;
- if (target_bits & 4)
- host_bits |= float_flag_overflow;
- if (target_bits & 8)
- host_bits |= float_flag_underflow;
- if (target_bits & 0x10)
- host_bits |= float_flag_inexact;
- if (target_bits & 0x80)
- host_bits |= float_flag_input_denormal;
- return host_bits;
-}
-
-void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
-{
- int i;
- uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
-
- /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
- if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
- val &= ~FPCR_FZ16;
- }
-
- /*
- * We don't implement trapped exception handling, so the
- * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
- *
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
- * (which are stored in fp_status), and the other RES0 bits
- * in between, then we clear all of the low 16 bits.
- */
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
- env->vfp.vec_len = (val >> 16) & 7;
- env->vfp.vec_stride = (val >> 20) & 3;
-
- /*
- * The bit we set within fpscr_q is arbitrary; the register as a
- * whole being zero/non-zero is what counts.
- */
- env->vfp.qc[0] = val & FPCR_QC;
- env->vfp.qc[1] = 0;
- env->vfp.qc[2] = 0;
- env->vfp.qc[3] = 0;
-
- changed ^= val;
- if (changed & (3 << 22)) {
- i = (val >> 22) & 3;
- switch (i) {
- case FPROUNDING_TIEEVEN:
- i = float_round_nearest_even;
- break;
- case FPROUNDING_POSINF:
- i = float_round_up;
- break;
- case FPROUNDING_NEGINF:
- i = float_round_down;
- break;
- case FPROUNDING_ZERO:
- i = float_round_to_zero;
- break;
- }
- set_float_rounding_mode(i, &env->vfp.fp_status);
- set_float_rounding_mode(i, &env->vfp.fp_status_f16);
- }
- if (changed & FPCR_FZ16) {
- bool ftz_enabled = val & FPCR_FZ16;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
- }
- if (changed & FPCR_FZ) {
- bool ftz_enabled = val & FPCR_FZ;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
- }
- if (changed & FPCR_DN) {
- bool dnan_enabled = val & FPCR_DN;
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
- }
-
- /* The exception flags are ORed together when we read fpscr so we
- * only need to preserve the current state in one of our
- * float_status values.
- */
- i = vfp_exceptbits_to_host(val);
- set_float_exception_flags(i, &env->vfp.fp_status);
- set_float_exception_flags(0, &env->vfp.fp_status_f16);
- set_float_exception_flags(0, &env->vfp.standard_fp_status);
-}
-
-void vfp_set_fpscr(CPUARMState *env, uint32_t val)
-{
- HELPER(vfp_set_fpscr)(env, val);
-}
-
-#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
-
-#define VFP_BINOP(name) \
-float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- return float32_ ## name(a, b, fpst); \
-} \
-float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- return float64_ ## name(a, b, fpst); \
-}
-VFP_BINOP(add)
-VFP_BINOP(sub)
-VFP_BINOP(mul)
-VFP_BINOP(div)
-VFP_BINOP(min)
-VFP_BINOP(max)
-VFP_BINOP(minnum)
-VFP_BINOP(maxnum)
-#undef VFP_BINOP
-
-float32 VFP_HELPER(neg, s)(float32 a)
-{
- return float32_chs(a);
-}
-
-float64 VFP_HELPER(neg, d)(float64 a)
-{
- return float64_chs(a);
-}
-
-float32 VFP_HELPER(abs, s)(float32 a)
-{
- return float32_abs(a);
-}
-
-float64 VFP_HELPER(abs, d)(float64 a)
-{
- return float64_abs(a);
-}
-
-float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
-{
- return float32_sqrt(a, &env->vfp.fp_status);
-}
-
-float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
-{
- return float64_sqrt(a, &env->vfp.fp_status);
-}
-
-static void softfloat_to_vfp_compare(CPUARMState *env, int cmp)
-{
- uint32_t flags;
- switch (cmp) {
- case float_relation_equal:
- flags = 0x6;
- break;
- case float_relation_less:
- flags = 0x8;
- break;
- case float_relation_greater:
- flags = 0x2;
- break;
- case float_relation_unordered:
- flags = 0x3;
- break;
- default:
- g_assert_not_reached();
- }
- env->vfp.xregs[ARM_VFP_FPSCR] =
- deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
-}
-
-/* XXX: check quiet/signaling case */
-#define DO_VFP_cmp(p, type) \
-void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
-{ \
- softfloat_to_vfp_compare(env, \
- type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
-} \
-void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
-{ \
- softfloat_to_vfp_compare(env, \
- type ## _compare(a, b, &env->vfp.fp_status)); \
-}
-DO_VFP_cmp(s, float32)
-DO_VFP_cmp(d, float64)
-#undef DO_VFP_cmp
-
-/* Integer to float and float to integer conversions */
-
-#define CONV_ITOF(name, ftype, fsz, sign) \
-ftype HELPER(name)(uint32_t x, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
-}
-
-#define CONV_FTOI(name, ftype, fsz, sign, round) \
-sign##int32_t HELPER(name)(ftype x, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- if (float##fsz##_is_any_nan(x)) { \
- float_raise(float_flag_invalid, fpst); \
- return 0; \
- } \
- return float##fsz##_to_##sign##int32##round(x, fpst); \
-}
-
-#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
- CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
- CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
- CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
-
-FLOAT_CONVS(si, h, uint32_t, 16, )
-FLOAT_CONVS(si, s, float32, 32, )
-FLOAT_CONVS(si, d, float64, 64, )
-FLOAT_CONVS(ui, h, uint32_t, 16, u)
-FLOAT_CONVS(ui, s, float32, 32, u)
-FLOAT_CONVS(ui, d, float64, 64, u)
-
-#undef CONV_ITOF
-#undef CONV_FTOI
-#undef FLOAT_CONVS
-
-/* floating point conversion */
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
-{
- return float32_to_float64(x, &env->vfp.fp_status);
-}
-
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
-{
- return float64_to_float32(x, &env->vfp.fp_status);
-}
-
-/* VFP3 fixed point conversion. */
-#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
-float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
- void *fpstp) \
-{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
-
-#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
-uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
- void *fpst) \
-{ \
- if (unlikely(float##fsz##_is_any_nan(x))) { \
- float_raise(float_flag_invalid, fpst); \
- return 0; \
- } \
- return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
-}
-
-#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
-VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
-VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
- float_round_to_zero, _round_to_zero) \
-VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
- get_float_rounding_mode(fpst), )
-
-#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
-VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
-VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
- get_float_rounding_mode(fpst), )
-
-VFP_CONV_FIX(sh, d, 64, 64, int16)
-VFP_CONV_FIX(sl, d, 64, 64, int32)
-VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
-VFP_CONV_FIX(uh, d, 64, 64, uint16)
-VFP_CONV_FIX(ul, d, 64, 64, uint32)
-VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
-VFP_CONV_FIX(sh, s, 32, 32, int16)
-VFP_CONV_FIX(sl, s, 32, 32, int32)
-VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
-VFP_CONV_FIX(uh, s, 32, 32, uint16)
-VFP_CONV_FIX(ul, s, 32, 32, uint32)
-VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
-
-#undef VFP_CONV_FIX
-#undef VFP_CONV_FIX_FLOAT
-#undef VFP_CONV_FLOAT_FIX_ROUND
-#undef VFP_CONV_FIX_A64
-
-uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
-{
- return int32_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
-{
- return uint32_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
-{
- return int64_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
-{
- return uint64_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-/* Set the current fp rounding mode and return the old one.
- * The argument is a softfloat float_round_ value.
- */
-uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
-{
- float_status *fp_status = fpstp;
-
- uint32_t prev_rmode = get_float_rounding_mode(fp_status);
- set_float_rounding_mode(rmode, fp_status);
-
- return prev_rmode;
-}
-
-/* Set the current fp rounding mode in the standard fp status and return
- * the old one. This is for NEON instructions that need to change the
- * rounding mode but wish to use the standard FPSCR values for everything
- * else. Always set the rounding mode back to the correct value after
- * modifying it.
- * The argument is a softfloat float_round_ value.
- */
-uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
-{
- float_status *fp_status = &env->vfp.standard_fp_status;
-
- uint32_t prev_rmode = get_float_rounding_mode(fp_status);
- set_float_rounding_mode(rmode, fp_status);
-
- return prev_rmode;
-}
-
-/* Half precision conversions. */
-float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
-{
- /* Squash FZ16 to 0 for the duration of conversion. In this case,
- * it would affect flushing input denormals.
- */
- float_status *fpst = fpstp;
- flag save = get_flush_inputs_to_zero(fpst);
- set_flush_inputs_to_zero(false, fpst);
- float32 r = float16_to_float32(a, !ahp_mode, fpst);
- set_flush_inputs_to_zero(save, fpst);
- return r;
-}
-
-uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
-{
- /* Squash FZ16 to 0 for the duration of conversion. In this case,
- * it would affect flushing output denormals.
- */
- float_status *fpst = fpstp;
- flag save = get_flush_to_zero(fpst);
- set_flush_to_zero(false, fpst);
- float16 r = float32_to_float16(a, !ahp_mode, fpst);
- set_flush_to_zero(save, fpst);
- return r;
-}
-
-float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
-{
- /* Squash FZ16 to 0 for the duration of conversion. In this case,
- * it would affect flushing input denormals.
- */
- float_status *fpst = fpstp;
- flag save = get_flush_inputs_to_zero(fpst);
- set_flush_inputs_to_zero(false, fpst);
- float64 r = float16_to_float64(a, !ahp_mode, fpst);
- set_flush_inputs_to_zero(save, fpst);
- return r;
-}
-
-uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
-{
- /* Squash FZ16 to 0 for the duration of conversion. In this case,
- * it would affect flushing output denormals.
- */
- float_status *fpst = fpstp;
- flag save = get_flush_to_zero(fpst);
- set_flush_to_zero(false, fpst);
- float16 r = float64_to_float16(a, !ahp_mode, fpst);
- set_flush_to_zero(save, fpst);
- return r;
-}
-
-#define float32_two make_float32(0x40000000)
-#define float32_three make_float32(0x40400000)
-#define float32_one_point_five make_float32(0x3fc00000)
-
-float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
-{
- float_status *s = &env->vfp.standard_fp_status;
- if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
- (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
- if (!(float32_is_zero(a) || float32_is_zero(b))) {
- float_raise(float_flag_input_denormal, s);
- }
- return float32_two;
- }
- return float32_sub(float32_two, float32_mul(a, b, s), s);
-}
-
-float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
-{
- float_status *s = &env->vfp.standard_fp_status;
- float32 product;
- if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
- (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
- if (!(float32_is_zero(a) || float32_is_zero(b))) {
- float_raise(float_flag_input_denormal, s);
- }
- return float32_one_point_five;
- }
- product = float32_mul(a, b, s);
- return float32_div(float32_sub(float32_three, product, s), float32_two, s);
-}
-
-/* NEON helpers. */
-
-/* Constants 256 and 512 are used in some helpers; we avoid relying on
- * int->float conversions at run-time. */
-#define float64_256 make_float64(0x4070000000000000LL)
-#define float64_512 make_float64(0x4080000000000000LL)
-#define float16_maxnorm make_float16(0x7bff)
-#define float32_maxnorm make_float32(0x7f7fffff)
-#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
-
-/* Reciprocal functions
- *
- * The algorithm that must be used to calculate the estimate
- * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
- */
-
-/* See RecipEstimate()
- *
- * input is a 9 bit fixed point number
- * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
- * result range 256 .. 511 for a number from 1.0 to 511/256.
- */
-
-static int recip_estimate(int input)
-{
- int a, b, r;
- assert(256 <= input && input < 512);
- a = (input * 2) + 1;
- b = (1 << 19) / a;
- r = (b + 1) >> 1;
- assert(256 <= r && r < 512);
- return r;
-}
-
-/*
- * Common wrapper to call recip_estimate
- *
- * The parameters are exponent and 64 bit fraction (without implicit
- * bit) where the binary point is nominally at bit 52. Returns a
- * float64 which can then be rounded to the appropriate size by the
- * callee.
- */
-
-static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
-{
- uint32_t scaled, estimate;
- uint64_t result_frac;
- int result_exp;
-
- /* Handle sub-normals */
- if (*exp == 0) {
- if (extract64(frac, 51, 1) == 0) {
- *exp = -1;
- frac <<= 2;
- } else {
- frac <<= 1;
- }
- }
-
- /* scaled = UInt('1':fraction<51:44>) */
- scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
- estimate = recip_estimate(scaled);
-
- result_exp = exp_off - *exp;
- result_frac = deposit64(0, 44, 8, estimate);
- if (result_exp == 0) {
- result_frac = deposit64(result_frac >> 1, 51, 1, 1);
- } else if (result_exp == -1) {
- result_frac = deposit64(result_frac >> 2, 50, 2, 1);
- result_exp = 0;
- }
-
- *exp = result_exp;
-
- return result_frac;
-}
-
-static bool round_to_inf(float_status *fpst, bool sign_bit)
-{
- switch (fpst->float_rounding_mode) {
- case float_round_nearest_even: /* Round to Nearest */
- return true;
- case float_round_up: /* Round to +Inf */
- return !sign_bit;
- case float_round_down: /* Round to -Inf */
- return sign_bit;
- case float_round_to_zero: /* Round to Zero */
- return false;
- }
-
- g_assert_not_reached();
-}
-
-uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
-{
- float_status *fpst = fpstp;
- float16 f16 = float16_squash_input_denormal(input, fpst);
- uint32_t f16_val = float16_val(f16);
- uint32_t f16_sign = float16_is_neg(f16);
- int f16_exp = extract32(f16_val, 10, 5);
- uint32_t f16_frac = extract32(f16_val, 0, 10);
- uint64_t f64_frac;
-
- if (float16_is_any_nan(f16)) {
- float16 nan = f16;
- if (float16_is_signaling_nan(f16, fpst)) {
- float_raise(float_flag_invalid, fpst);
- nan = float16_silence_nan(f16, fpst);
- }
- if (fpst->default_nan_mode) {
- nan = float16_default_nan(fpst);
- }
- return nan;
- } else if (float16_is_infinity(f16)) {
- return float16_set_sign(float16_zero, float16_is_neg(f16));
- } else if (float16_is_zero(f16)) {
- float_raise(float_flag_divbyzero, fpst);
- return float16_set_sign(float16_infinity, float16_is_neg(f16));
- } else if (float16_abs(f16) < (1 << 8)) {
- /* Abs(value) < 2.0^-16 */
- float_raise(float_flag_overflow | float_flag_inexact, fpst);
- if (round_to_inf(fpst, f16_sign)) {
- return float16_set_sign(float16_infinity, f16_sign);
- } else {
- return float16_set_sign(float16_maxnorm, f16_sign);
- }
- } else if (f16_exp >= 29 && fpst->flush_to_zero) {
- float_raise(float_flag_underflow, fpst);
- return float16_set_sign(float16_zero, float16_is_neg(f16));
- }
-
- f64_frac = call_recip_estimate(&f16_exp, 29,
- ((uint64_t) f16_frac) << (52 - 10));
-
- /* result = sign : result_exp<4:0> : fraction<51:42> */
- f16_val = deposit32(0, 15, 1, f16_sign);
- f16_val = deposit32(f16_val, 10, 5, f16_exp);
- f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
- return make_float16(f16_val);
-}
-
-float32 HELPER(recpe_f32)(float32 input, void *fpstp)
-{
- float_status *fpst = fpstp;
- float32 f32 = float32_squash_input_denormal(input, fpst);
- uint32_t f32_val = float32_val(f32);
- bool f32_sign = float32_is_neg(f32);
- int f32_exp = extract32(f32_val, 23, 8);
- uint32_t f32_frac = extract32(f32_val, 0, 23);
- uint64_t f64_frac;
-
- if (float32_is_any_nan(f32)) {
- float32 nan = f32;
- if (float32_is_signaling_nan(f32, fpst)) {
- float_raise(float_flag_invalid, fpst);
- nan = float32_silence_nan(f32, fpst);
- }
- if (fpst->default_nan_mode) {
- nan = float32_default_nan(fpst);
- }
- return nan;
- } else if (float32_is_infinity(f32)) {
- return float32_set_sign(float32_zero, float32_is_neg(f32));
- } else if (float32_is_zero(f32)) {
- float_raise(float_flag_divbyzero, fpst);
- return float32_set_sign(float32_infinity, float32_is_neg(f32));
- } else if (float32_abs(f32) < (1ULL << 21)) {
- /* Abs(value) < 2.0^-128 */
- float_raise(float_flag_overflow | float_flag_inexact, fpst);
- if (round_to_inf(fpst, f32_sign)) {
- return float32_set_sign(float32_infinity, f32_sign);
- } else {
- return float32_set_sign(float32_maxnorm, f32_sign);
- }
- } else if (f32_exp >= 253 && fpst->flush_to_zero) {
- float_raise(float_flag_underflow, fpst);
- return float32_set_sign(float32_zero, float32_is_neg(f32));
- }
-
- f64_frac = call_recip_estimate(&f32_exp, 253,
- ((uint64_t) f32_frac) << (52 - 23));
-
- /* result = sign : result_exp<7:0> : fraction<51:29> */
- f32_val = deposit32(0, 31, 1, f32_sign);
- f32_val = deposit32(f32_val, 23, 8, f32_exp);
- f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
- return make_float32(f32_val);
-}
-
-float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-{
- float_status *fpst = fpstp;
- float64 f64 = float64_squash_input_denormal(input, fpst);
- uint64_t f64_val = float64_val(f64);
- bool f64_sign = float64_is_neg(f64);
- int f64_exp = extract64(f64_val, 52, 11);
- uint64_t f64_frac = extract64(f64_val, 0, 52);
-
- /* Deal with any special cases */
- if (float64_is_any_nan(f64)) {
- float64 nan = f64;
- if (float64_is_signaling_nan(f64, fpst)) {
- float_raise(float_flag_invalid, fpst);
- nan = float64_silence_nan(f64, fpst);
- }
- if (fpst->default_nan_mode) {
- nan = float64_default_nan(fpst);
- }
- return nan;
- } else if (float64_is_infinity(f64)) {
- return float64_set_sign(float64_zero, float64_is_neg(f64));
- } else if (float64_is_zero(f64)) {
- float_raise(float_flag_divbyzero, fpst);
- return float64_set_sign(float64_infinity, float64_is_neg(f64));
- } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
- /* Abs(value) < 2.0^-1024 */
- float_raise(float_flag_overflow | float_flag_inexact, fpst);
- if (round_to_inf(fpst, f64_sign)) {
- return float64_set_sign(float64_infinity, f64_sign);
- } else {
- return float64_set_sign(float64_maxnorm, f64_sign);
- }
- } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
- float_raise(float_flag_underflow, fpst);
- return float64_set_sign(float64_zero, float64_is_neg(f64));
- }
-
- f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
-
- /* result = sign : result_exp<10:0> : fraction<51:0>; */
- f64_val = deposit64(0, 63, 1, f64_sign);
- f64_val = deposit64(f64_val, 52, 11, f64_exp);
- f64_val = deposit64(f64_val, 0, 52, f64_frac);
- return make_float64(f64_val);
-}
-
-/* The algorithm that must be used to calculate the estimate
- * is specified by the ARM ARM.
- */
-
-static int do_recip_sqrt_estimate(int a)
-{
- int b, estimate;
-
- assert(128 <= a && a < 512);
- if (a < 256) {
- a = a * 2 + 1;
- } else {
- a = (a >> 1) << 1;
- a = (a + 1) * 2;
- }
- b = 512;
- while (a * (b + 1) * (b + 1) < (1 << 28)) {
- b += 1;
- }
- estimate = (b + 1) / 2;
- assert(256 <= estimate && estimate < 512);
-
- return estimate;
-}
-
-
-static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
-{
- int estimate;
- uint32_t scaled;
-
- if (*exp == 0) {
- while (extract64(frac, 51, 1) == 0) {
- frac = frac << 1;
- *exp -= 1;
- }
- frac = extract64(frac, 0, 51) << 1;
- }
-
- if (*exp & 1) {
- /* scaled = UInt('01':fraction<51:45>) */
- scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
- } else {
- /* scaled = UInt('1':fraction<51:44>) */
- scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
- }
- estimate = do_recip_sqrt_estimate(scaled);
-
- *exp = (exp_off - *exp) / 2;
- return extract64(estimate, 0, 8) << 44;
-}
-
-uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
-{
- float_status *s = fpstp;
- float16 f16 = float16_squash_input_denormal(input, s);
- uint16_t val = float16_val(f16);
- bool f16_sign = float16_is_neg(f16);
- int f16_exp = extract32(val, 10, 5);
- uint16_t f16_frac = extract32(val, 0, 10);
- uint64_t f64_frac;
-
- if (float16_is_any_nan(f16)) {
- float16 nan = f16;
- if (float16_is_signaling_nan(f16, s)) {
- float_raise(float_flag_invalid, s);
- nan = float16_silence_nan(f16, s);
- }
- if (s->default_nan_mode) {
- nan = float16_default_nan(s);
- }
- return nan;
- } else if (float16_is_zero(f16)) {
- float_raise(float_flag_divbyzero, s);
- return float16_set_sign(float16_infinity, f16_sign);
- } else if (f16_sign) {
- float_raise(float_flag_invalid, s);
- return float16_default_nan(s);
- } else if (float16_is_infinity(f16)) {
- return float16_zero;
- }
-
- /* Scale and normalize to a double-precision value between 0.25 and 1.0,
- * preserving the parity of the exponent. */
-
- f64_frac = ((uint64_t) f16_frac) << (52 - 10);
-
- f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
-
- /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
- val = deposit32(0, 15, 1, f16_sign);
- val = deposit32(val, 10, 5, f16_exp);
- val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
- return make_float16(val);
-}
-
-float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
-{
- float_status *s = fpstp;
- float32 f32 = float32_squash_input_denormal(input, s);
- uint32_t val = float32_val(f32);
- uint32_t f32_sign = float32_is_neg(f32);
- int f32_exp = extract32(val, 23, 8);
- uint32_t f32_frac = extract32(val, 0, 23);
- uint64_t f64_frac;
-
- if (float32_is_any_nan(f32)) {
- float32 nan = f32;
- if (float32_is_signaling_nan(f32, s)) {
- float_raise(float_flag_invalid, s);
- nan = float32_silence_nan(f32, s);
- }
- if (s->default_nan_mode) {
- nan = float32_default_nan(s);
- }
- return nan;
- } else if (float32_is_zero(f32)) {
- float_raise(float_flag_divbyzero, s);
- return float32_set_sign(float32_infinity, float32_is_neg(f32));
- } else if (float32_is_neg(f32)) {
- float_raise(float_flag_invalid, s);
- return float32_default_nan(s);
- } else if (float32_is_infinity(f32)) {
- return float32_zero;
- }
-
- /* Scale and normalize to a double-precision value between 0.25 and 1.0,
- * preserving the parity of the exponent. */
-
- f64_frac = ((uint64_t) f32_frac) << 29;
-
- f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
-
- /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
- val = deposit32(0, 31, 1, f32_sign);
- val = deposit32(val, 23, 8, f32_exp);
- val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
- return make_float32(val);
-}
-
-float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
-{
- float_status *s = fpstp;
- float64 f64 = float64_squash_input_denormal(input, s);
- uint64_t val = float64_val(f64);
- bool f64_sign = float64_is_neg(f64);
- int f64_exp = extract64(val, 52, 11);
- uint64_t f64_frac = extract64(val, 0, 52);
-
- if (float64_is_any_nan(f64)) {
- float64 nan = f64;
- if (float64_is_signaling_nan(f64, s)) {
- float_raise(float_flag_invalid, s);
- nan = float64_silence_nan(f64, s);
- }
- if (s->default_nan_mode) {
- nan = float64_default_nan(s);
- }
- return nan;
- } else if (float64_is_zero(f64)) {
- float_raise(float_flag_divbyzero, s);
- return float64_set_sign(float64_infinity, float64_is_neg(f64));
- } else if (float64_is_neg(f64)) {
- float_raise(float_flag_invalid, s);
- return float64_default_nan(s);
- } else if (float64_is_infinity(f64)) {
- return float64_zero;
- }
-
- f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
-
- /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
- val = deposit64(0, 61, 1, f64_sign);
- val = deposit64(val, 52, 11, f64_exp);
- val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
- return make_float64(val);
-}
-
-uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
-{
- /* float_status *s = fpstp; */
- int input, estimate;
-
- if ((a & 0x80000000) == 0) {
- return 0xffffffff;
- }
-
- input = extract32(a, 23, 9);
- estimate = recip_estimate(input);
-
- return deposit32(0, (32 - 9), 9, estimate);
-}
-
-uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
-{
- int estimate;
-
- if ((a & 0xc0000000) == 0) {
- return 0xffffffff;
- }
-
- estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
-
- return deposit32(0, 23, 9, estimate);
-}
-
-/* VFPv4 fused multiply-accumulate */
-float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
-{
- float_status *fpst = fpstp;
- return float32_muladd(a, b, c, 0, fpst);
-}
-
-float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
-{
- float_status *fpst = fpstp;
- return float64_muladd(a, b, c, 0, fpst);
-}
-
-/* ARMv8 round to integral */
-float32 HELPER(rints_exact)(float32 x, void *fp_status)
-{
- return float32_round_to_int(x, fp_status);
-}
-
-float64 HELPER(rintd_exact)(float64 x, void *fp_status)
-{
- return float64_round_to_int(x, fp_status);
-}
-
-float32 HELPER(rints)(float32 x, void *fp_status)
-{
- int old_flags = get_float_exception_flags(fp_status), new_flags;
- float32 ret;
-
- ret = float32_round_to_int(x, fp_status);
-
- /* Suppress any inexact exceptions the conversion produced */
- if (!(old_flags & float_flag_inexact)) {
- new_flags = get_float_exception_flags(fp_status);
- set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
- }
-
- return ret;
-}
-
-float64 HELPER(rintd)(float64 x, void *fp_status)
-{
- int old_flags = get_float_exception_flags(fp_status), new_flags;
- float64 ret;
-
- ret = float64_round_to_int(x, fp_status);
-
- new_flags = get_float_exception_flags(fp_status);
-
- /* Suppress any inexact exceptions the conversion produced */
- if (!(old_flags & float_flag_inexact)) {
- new_flags = get_float_exception_flags(fp_status);
- set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
- }
-
- return ret;
-}
-
-/* Convert ARM rounding mode to softfloat */
-int arm_rmode_to_sf(int rmode)
-{
- switch (rmode) {
- case FPROUNDING_TIEAWAY:
- rmode = float_round_ties_away;
- break;
- case FPROUNDING_ODD:
- /* FIXME: add support for TIEAWAY and ODD */
- qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
- rmode);
- /* fall through for now */
- case FPROUNDING_TIEEVEN:
- default:
- rmode = float_round_nearest_even;
- break;
- case FPROUNDING_POSINF:
- rmode = float_round_up;
- break;
- case FPROUNDING_NEGINF:
- rmode = float_round_down;
- break;
- case FPROUNDING_ZERO:
- rmode = float_round_to_zero;
- break;
- }
- return rmode;
-}
-
/* CRC helpers.
* The upper bytes of val (above the number specified by 'bytes') must have
* been zeroed out by the caller.
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
new file mode 100644
index 0000000000..74d3030c47
--- /dev/null
+++ b/target/arm/vfp_helper.c
@@ -0,0 +1,1088 @@
+/*
+ * ARM VFP floating-point operations
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "fpu/softfloat.h"
+#include "internals.h"
+
+
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
+ "d" suffix. */
+
+/* Convert host exception flags to vfp form. */
+static inline int vfp_exceptbits_from_host(int host_bits)
+{
+ int target_bits = 0;
+
+ if (host_bits & float_flag_invalid)
+ target_bits |= 1;
+ if (host_bits & float_flag_divbyzero)
+ target_bits |= 2;
+ if (host_bits & float_flag_overflow)
+ target_bits |= 4;
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
+ target_bits |= 8;
+ if (host_bits & float_flag_inexact)
+ target_bits |= 0x10;
+ if (host_bits & float_flag_input_denormal)
+ target_bits |= 0x80;
+ return target_bits;
+}
+
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
+{
+ uint32_t i, fpscr;
+
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
+ | (env->vfp.vec_len << 16)
+ | (env->vfp.vec_stride << 20);
+
+ i = get_float_exception_flags(&env->vfp.fp_status);
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
+ /* FZ16 does not generate an input denormal exception. */
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
+ & ~float_flag_input_denormal);
+ fpscr |= vfp_exceptbits_from_host(i);
+
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
+ fpscr |= i ? FPCR_QC : 0;
+
+ return fpscr;
+}
+
+uint32_t vfp_get_fpscr(CPUARMState *env)
+{
+ return HELPER(vfp_get_fpscr)(env);
+}
+
+/* Convert vfp exception flags to target form. */
+static inline int vfp_exceptbits_to_host(int target_bits)
+{
+ int host_bits = 0;
+
+ if (target_bits & 1)
+ host_bits |= float_flag_invalid;
+ if (target_bits & 2)
+ host_bits |= float_flag_divbyzero;
+ if (target_bits & 4)
+ host_bits |= float_flag_overflow;
+ if (target_bits & 8)
+ host_bits |= float_flag_underflow;
+ if (target_bits & 0x10)
+ host_bits |= float_flag_inexact;
+ if (target_bits & 0x80)
+ host_bits |= float_flag_input_denormal;
+ return host_bits;
+}
+
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
+{
+ int i;
+ uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
+
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
+ if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
+ val &= ~FPCR_FZ16;
+ }
+
+ /*
+ * We don't implement trapped exception handling, so the
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
+ *
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
+ * (which are stored in fp_status), and the other RES0 bits
+ * in between, then we clear all of the low 16 bits.
+ */
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
+ env->vfp.vec_len = (val >> 16) & 7;
+ env->vfp.vec_stride = (val >> 20) & 3;
+
+ /*
+ * The bit we set within fpscr_q is arbitrary; the register as a
+ * whole being zero/non-zero is what counts.
+ */
+ env->vfp.qc[0] = val & FPCR_QC;
+ env->vfp.qc[1] = 0;
+ env->vfp.qc[2] = 0;
+ env->vfp.qc[3] = 0;
+
+ changed ^= val;
+ if (changed & (3 << 22)) {
+ i = (val >> 22) & 3;
+ switch (i) {
+ case FPROUNDING_TIEEVEN:
+ i = float_round_nearest_even;
+ break;
+ case FPROUNDING_POSINF:
+ i = float_round_up;
+ break;
+ case FPROUNDING_NEGINF:
+ i = float_round_down;
+ break;
+ case FPROUNDING_ZERO:
+ i = float_round_to_zero;
+ break;
+ }
+ set_float_rounding_mode(i, &env->vfp.fp_status);
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16);
+ }
+ if (changed & FPCR_FZ16) {
+ bool ftz_enabled = val & FPCR_FZ16;
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ }
+ if (changed & FPCR_FZ) {
+ bool ftz_enabled = val & FPCR_FZ;
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+ }
+ if (changed & FPCR_DN) {
+ bool dnan_enabled = val & FPCR_DN;
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
+ }
+
+ /* The exception flags are ORed together when we read fpscr so we
+ * only need to preserve the current state in one of our
+ * float_status values.
+ */
+ i = vfp_exceptbits_to_host(val);
+ set_float_exception_flags(i, &env->vfp.fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status_f16);
+ set_float_exception_flags(0, &env->vfp.standard_fp_status);
+}
+
+void vfp_set_fpscr(CPUARMState *env, uint32_t val)
+{
+ HELPER(vfp_set_fpscr)(env, val);
+}
+
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
+
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
+VFP_BINOP(add)
+VFP_BINOP(sub)
+VFP_BINOP(mul)
+VFP_BINOP(div)
+VFP_BINOP(min)
+VFP_BINOP(max)
+VFP_BINOP(minnum)
+VFP_BINOP(maxnum)
+#undef VFP_BINOP
+
+float32 VFP_HELPER(neg, s)(float32 a)
+{
+ return float32_chs(a);
+}
+
+float64 VFP_HELPER(neg, d)(float64 a)
+{
+ return float64_chs(a);
+}
+
+float32 VFP_HELPER(abs, s)(float32 a)
+{
+ return float32_abs(a);
+}
+
+float64 VFP_HELPER(abs, d)(float64 a)
+{
+ return float64_abs(a);
+}
+
+float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
+{
+ return float32_sqrt(a, &env->vfp.fp_status);
+}
+
+float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
+{
+ return float64_sqrt(a, &env->vfp.fp_status);
+}
+
+static void softfloat_to_vfp_compare(CPUARMState *env, int cmp)
+{
+ uint32_t flags;
+ switch (cmp) {
+ case float_relation_equal:
+ flags = 0x6;
+ break;
+ case float_relation_less:
+ flags = 0x8;
+ break;
+ case float_relation_greater:
+ flags = 0x2;
+ break;
+ case float_relation_unordered:
+ flags = 0x3;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ env->vfp.xregs[ARM_VFP_FPSCR] =
+ deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
+}
+
+/* XXX: check quiet/signaling case */
+#define DO_VFP_cmp(p, type) \
+void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
+{ \
+ softfloat_to_vfp_compare(env, \
+ type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
+} \
+void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
+{ \
+ softfloat_to_vfp_compare(env, \
+ type ## _compare(a, b, &env->vfp.fp_status)); \
+}
+DO_VFP_cmp(s, float32)
+DO_VFP_cmp(d, float64)
+#undef DO_VFP_cmp
+
+/* Integer to float and float to integer conversions */
+
+#define CONV_ITOF(name, ftype, fsz, sign) \
+ftype HELPER(name)(uint32_t x, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+}
+
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
+sign##int32_t HELPER(name)(ftype x, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ if (float##fsz##_is_any_nan(x)) { \
+ float_raise(float_flag_invalid, fpst); \
+ return 0; \
+ } \
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
+}
+
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
+
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
+
+#undef CONV_ITOF
+#undef CONV_FTOI
+#undef FLOAT_CONVS
+
+/* floating point conversion */
+float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
+{
+ return float32_to_float64(x, &env->vfp.fp_status);
+}
+
+float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
+{
+ return float64_to_float32(x, &env->vfp.fp_status);
+}
+
+/* VFP3 fixed point conversion. */
+#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
+float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
+ void *fpstp) \
+{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
+
+#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
+uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
+ void *fpst) \
+{ \
+ if (unlikely(float##fsz##_is_any_nan(x))) { \
+ float_raise(float_flag_invalid, fpst); \
+ return 0; \
+ } \
+ return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
+}
+
+#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
+VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
+VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
+ float_round_to_zero, _round_to_zero) \
+VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
+ get_float_rounding_mode(fpst), )
+
+#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
+VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
+VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
+ get_float_rounding_mode(fpst), )
+
+VFP_CONV_FIX(sh, d, 64, 64, int16)
+VFP_CONV_FIX(sl, d, 64, 64, int32)
+VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
+VFP_CONV_FIX(uh, d, 64, 64, uint16)
+VFP_CONV_FIX(ul, d, 64, 64, uint32)
+VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
+VFP_CONV_FIX(sh, s, 32, 32, int16)
+VFP_CONV_FIX(sl, s, 32, 32, int32)
+VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
+VFP_CONV_FIX(uh, s, 32, 32, uint16)
+VFP_CONV_FIX(ul, s, 32, 32, uint32)
+VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
+
+#undef VFP_CONV_FIX
+#undef VFP_CONV_FIX_FLOAT
+#undef VFP_CONV_FLOAT_FIX_ROUND
+#undef VFP_CONV_FIX_A64
+
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ return int32_to_float16_scalbn(x, -shift, fpst);
+}
+
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ return uint32_to_float16_scalbn(x, -shift, fpst);
+}
+
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+{
+ return int64_to_float16_scalbn(x, -shift, fpst);
+}
+
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+{
+ return uint64_to_float16_scalbn(x, -shift, fpst);
+}
+
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
+{
+ if (unlikely(float16_is_any_nan(x))) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst),
+ shift, fpst);
+}
+
+/* Set the current fp rounding mode and return the old one.
+ * The argument is a softfloat float_round_ value.
+ */
+uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
+{
+ float_status *fp_status = fpstp;
+
+ uint32_t prev_rmode = get_float_rounding_mode(fp_status);
+ set_float_rounding_mode(rmode, fp_status);
+
+ return prev_rmode;
+}
+
+/* Set the current fp rounding mode in the standard fp status and return
+ * the old one. This is for NEON instructions that need to change the
+ * rounding mode but wish to use the standard FPSCR values for everything
+ * else. Always set the rounding mode back to the correct value after
+ * modifying it.
+ * The argument is a softfloat float_round_ value.
+ */
+uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
+{
+ float_status *fp_status = &env->vfp.standard_fp_status;
+
+ uint32_t prev_rmode = get_float_rounding_mode(fp_status);
+ set_float_rounding_mode(rmode, fp_status);
+
+ return prev_rmode;
+}
+
+/* Half precision conversions. */
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
+{
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
+ * it would affect flushing input denormals.
+ */
+ float_status *fpst = fpstp;
+ flag save = get_flush_inputs_to_zero(fpst);
+ set_flush_inputs_to_zero(false, fpst);
+ float32 r = float16_to_float32(a, !ahp_mode, fpst);
+ set_flush_inputs_to_zero(save, fpst);
+ return r;
+}
+
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+{
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
+ * it would affect flushing output denormals.
+ */
+ float_status *fpst = fpstp;
+ flag save = get_flush_to_zero(fpst);
+ set_flush_to_zero(false, fpst);
+ float16 r = float32_to_float16(a, !ahp_mode, fpst);
+ set_flush_to_zero(save, fpst);
+ return r;
+}
+
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
+{
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
+ * it would affect flushing input denormals.
+ */
+ float_status *fpst = fpstp;
+ flag save = get_flush_inputs_to_zero(fpst);
+ set_flush_inputs_to_zero(false, fpst);
+ float64 r = float16_to_float64(a, !ahp_mode, fpst);
+ set_flush_inputs_to_zero(save, fpst);
+ return r;
+}
+
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+{
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
+ * it would affect flushing output denormals.
+ */
+ float_status *fpst = fpstp;
+ flag save = get_flush_to_zero(fpst);
+ set_flush_to_zero(false, fpst);
+ float16 r = float64_to_float16(a, !ahp_mode, fpst);
+ set_flush_to_zero(save, fpst);
+ return r;
+}
+
+#define float32_two make_float32(0x40000000)
+#define float32_three make_float32(0x40400000)
+#define float32_one_point_five make_float32(0x3fc00000)
+
+float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
+{
+ float_status *s = &env->vfp.standard_fp_status;
+ if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
+ (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
+ if (!(float32_is_zero(a) || float32_is_zero(b))) {
+ float_raise(float_flag_input_denormal, s);
+ }
+ return float32_two;
+ }
+ return float32_sub(float32_two, float32_mul(a, b, s), s);
+}
+
+float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
+{
+ float_status *s = &env->vfp.standard_fp_status;
+ float32 product;
+ if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
+ (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
+ if (!(float32_is_zero(a) || float32_is_zero(b))) {
+ float_raise(float_flag_input_denormal, s);
+ }
+ return float32_one_point_five;
+ }
+ product = float32_mul(a, b, s);
+ return float32_div(float32_sub(float32_three, product, s), float32_two, s);
+}
+
+/* NEON helpers. */
+
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
+ * int->float conversions at run-time. */
+#define float64_256 make_float64(0x4070000000000000LL)
+#define float64_512 make_float64(0x4080000000000000LL)
+#define float16_maxnorm make_float16(0x7bff)
+#define float32_maxnorm make_float32(0x7f7fffff)
+#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
+
+/* Reciprocal functions
+ *
+ * The algorithm that must be used to calculate the estimate
+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
+ */
+
+/* See RecipEstimate()
+ *
+ * input is a 9 bit fixed point number
+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
+ * result range 256 .. 511 for a number from 1.0 to 511/256.
+ */
+
+static int recip_estimate(int input)
+{
+ int a, b, r;
+ assert(256 <= input && input < 512);
+ a = (input * 2) + 1;
+ b = (1 << 19) / a;
+ r = (b + 1) >> 1;
+ assert(256 <= r && r < 512);
+ return r;
+}
+
+/*
+ * Common wrapper to call recip_estimate
+ *
+ * The parameters are exponent and 64 bit fraction (without implicit
+ * bit) where the binary point is nominally at bit 52. Returns a
+ * float64 which can then be rounded to the appropriate size by the
+ * callee.
+ */
+
+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
+{
+ uint32_t scaled, estimate;
+ uint64_t result_frac;
+ int result_exp;
+
+ /* Handle sub-normals */
+ if (*exp == 0) {
+ if (extract64(frac, 51, 1) == 0) {
+ *exp = -1;
+ frac <<= 2;
+ } else {
+ frac <<= 1;
+ }
+ }
+
+ /* scaled = UInt('1':fraction<51:44>) */
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+ estimate = recip_estimate(scaled);
+
+ result_exp = exp_off - *exp;
+ result_frac = deposit64(0, 44, 8, estimate);
+ if (result_exp == 0) {
+ result_frac = deposit64(result_frac >> 1, 51, 1, 1);
+ } else if (result_exp == -1) {
+ result_frac = deposit64(result_frac >> 2, 50, 2, 1);
+ result_exp = 0;
+ }
+
+ *exp = result_exp;
+
+ return result_frac;
+}
+
+static bool round_to_inf(float_status *fpst, bool sign_bit)
+{
+ switch (fpst->float_rounding_mode) {
+ case float_round_nearest_even: /* Round to Nearest */
+ return true;
+ case float_round_up: /* Round to +Inf */
+ return !sign_bit;
+ case float_round_down: /* Round to -Inf */
+ return sign_bit;
+ case float_round_to_zero: /* Round to Zero */
+ return false;
+ }
+
+ g_assert_not_reached();
+}
+
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float16 f16 = float16_squash_input_denormal(input, fpst);
+ uint32_t f16_val = float16_val(f16);
+ uint32_t f16_sign = float16_is_neg(f16);
+ int f16_exp = extract32(f16_val, 10, 5);
+ uint32_t f16_frac = extract32(f16_val, 0, 10);
+ uint64_t f64_frac;
+
+ if (float16_is_any_nan(f16)) {
+ float16 nan = f16;
+ if (float16_is_signaling_nan(f16, fpst)) {
+ float_raise(float_flag_invalid, fpst);
+ nan = float16_silence_nan(f16, fpst);
+ }
+ if (fpst->default_nan_mode) {
+ nan = float16_default_nan(fpst);
+ }
+ return nan;
+ } else if (float16_is_infinity(f16)) {
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
+ } else if (float16_is_zero(f16)) {
+ float_raise(float_flag_divbyzero, fpst);
+ return float16_set_sign(float16_infinity, float16_is_neg(f16));
+ } else if (float16_abs(f16) < (1 << 8)) {
+ /* Abs(value) < 2.0^-16 */
+ float_raise(float_flag_overflow | float_flag_inexact, fpst);
+ if (round_to_inf(fpst, f16_sign)) {
+ return float16_set_sign(float16_infinity, f16_sign);
+ } else {
+ return float16_set_sign(float16_maxnorm, f16_sign);
+ }
+ } else if (f16_exp >= 29 && fpst->flush_to_zero) {
+ float_raise(float_flag_underflow, fpst);
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
+ }
+
+ f64_frac = call_recip_estimate(&f16_exp, 29,
+ ((uint64_t) f16_frac) << (52 - 10));
+
+ /* result = sign : result_exp<4:0> : fraction<51:42> */
+ f16_val = deposit32(0, 15, 1, f16_sign);
+ f16_val = deposit32(f16_val, 10, 5, f16_exp);
+ f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
+ return make_float16(f16_val);
+}
+
+float32 HELPER(recpe_f32)(float32 input, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float32 f32 = float32_squash_input_denormal(input, fpst);
+ uint32_t f32_val = float32_val(f32);
+ bool f32_sign = float32_is_neg(f32);
+ int f32_exp = extract32(f32_val, 23, 8);
+ uint32_t f32_frac = extract32(f32_val, 0, 23);
+ uint64_t f64_frac;
+
+ if (float32_is_any_nan(f32)) {
+ float32 nan = f32;
+ if (float32_is_signaling_nan(f32, fpst)) {
+ float_raise(float_flag_invalid, fpst);
+ nan = float32_silence_nan(f32, fpst);
+ }
+ if (fpst->default_nan_mode) {
+ nan = float32_default_nan(fpst);
+ }
+ return nan;
+ } else if (float32_is_infinity(f32)) {
+ return float32_set_sign(float32_zero, float32_is_neg(f32));
+ } else if (float32_is_zero(f32)) {
+ float_raise(float_flag_divbyzero, fpst);
+ return float32_set_sign(float32_infinity, float32_is_neg(f32));
+ } else if (float32_abs(f32) < (1ULL << 21)) {
+ /* Abs(value) < 2.0^-128 */
+ float_raise(float_flag_overflow | float_flag_inexact, fpst);
+ if (round_to_inf(fpst, f32_sign)) {
+ return float32_set_sign(float32_infinity, f32_sign);
+ } else {
+ return float32_set_sign(float32_maxnorm, f32_sign);
+ }
+ } else if (f32_exp >= 253 && fpst->flush_to_zero) {
+ float_raise(float_flag_underflow, fpst);
+ return float32_set_sign(float32_zero, float32_is_neg(f32));
+ }
+
+ f64_frac = call_recip_estimate(&f32_exp, 253,
+ ((uint64_t) f32_frac) << (52 - 23));
+
+ /* result = sign : result_exp<7:0> : fraction<51:29> */
+ f32_val = deposit32(0, 31, 1, f32_sign);
+ f32_val = deposit32(f32_val, 23, 8, f32_exp);
+ f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
+ return make_float32(f32_val);
+}
+
+float64 HELPER(recpe_f64)(float64 input, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float64 f64 = float64_squash_input_denormal(input, fpst);
+ uint64_t f64_val = float64_val(f64);
+ bool f64_sign = float64_is_neg(f64);
+ int f64_exp = extract64(f64_val, 52, 11);
+ uint64_t f64_frac = extract64(f64_val, 0, 52);
+
+ /* Deal with any special cases */
+ if (float64_is_any_nan(f64)) {
+ float64 nan = f64;
+ if (float64_is_signaling_nan(f64, fpst)) {
+ float_raise(float_flag_invalid, fpst);
+ nan = float64_silence_nan(f64, fpst);
+ }
+ if (fpst->default_nan_mode) {
+ nan = float64_default_nan(fpst);
+ }
+ return nan;
+ } else if (float64_is_infinity(f64)) {
+ return float64_set_sign(float64_zero, float64_is_neg(f64));
+ } else if (float64_is_zero(f64)) {
+ float_raise(float_flag_divbyzero, fpst);
+ return float64_set_sign(float64_infinity, float64_is_neg(f64));
+ } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
+ /* Abs(value) < 2.0^-1024 */
+ float_raise(float_flag_overflow | float_flag_inexact, fpst);
+ if (round_to_inf(fpst, f64_sign)) {
+ return float64_set_sign(float64_infinity, f64_sign);
+ } else {
+ return float64_set_sign(float64_maxnorm, f64_sign);
+ }
+ } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
+ float_raise(float_flag_underflow, fpst);
+ return float64_set_sign(float64_zero, float64_is_neg(f64));
+ }
+
+ f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
+
+ /* result = sign : result_exp<10:0> : fraction<51:0>; */
+ f64_val = deposit64(0, 63, 1, f64_sign);
+ f64_val = deposit64(f64_val, 52, 11, f64_exp);
+ f64_val = deposit64(f64_val, 0, 52, f64_frac);
+ return make_float64(f64_val);
+}
+
+/* The algorithm that must be used to calculate the estimate
+ * is specified by the ARM ARM.
+ */
+
+static int do_recip_sqrt_estimate(int a)
+{
+ int b, estimate;
+
+ assert(128 <= a && a < 512);
+ if (a < 256) {
+ a = a * 2 + 1;
+ } else {
+ a = (a >> 1) << 1;
+ a = (a + 1) * 2;
+ }
+ b = 512;
+ while (a * (b + 1) * (b + 1) < (1 << 28)) {
+ b += 1;
+ }
+ estimate = (b + 1) / 2;
+ assert(256 <= estimate && estimate < 512);
+
+ return estimate;
+}
+
+
+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
+{
+ int estimate;
+ uint32_t scaled;
+
+ if (*exp == 0) {
+ while (extract64(frac, 51, 1) == 0) {
+ frac = frac << 1;
+ *exp -= 1;
+ }
+ frac = extract64(frac, 0, 51) << 1;
+ }
+
+ if (*exp & 1) {
+ /* scaled = UInt('01':fraction<51:45>) */
+ scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
+ } else {
+ /* scaled = UInt('1':fraction<51:44>) */
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+ }
+ estimate = do_recip_sqrt_estimate(scaled);
+
+ *exp = (exp_off - *exp) / 2;
+ return extract64(estimate, 0, 8) << 44;
+}
+
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
+{
+ float_status *s = fpstp;
+ float16 f16 = float16_squash_input_denormal(input, s);
+ uint16_t val = float16_val(f16);
+ bool f16_sign = float16_is_neg(f16);
+ int f16_exp = extract32(val, 10, 5);
+ uint16_t f16_frac = extract32(val, 0, 10);
+ uint64_t f64_frac;
+
+ if (float16_is_any_nan(f16)) {
+ float16 nan = f16;
+ if (float16_is_signaling_nan(f16, s)) {
+ float_raise(float_flag_invalid, s);
+ nan = float16_silence_nan(f16, s);
+ }
+ if (s->default_nan_mode) {
+ nan = float16_default_nan(s);
+ }
+ return nan;
+ } else if (float16_is_zero(f16)) {
+ float_raise(float_flag_divbyzero, s);
+ return float16_set_sign(float16_infinity, f16_sign);
+ } else if (f16_sign) {
+ float_raise(float_flag_invalid, s);
+ return float16_default_nan(s);
+ } else if (float16_is_infinity(f16)) {
+ return float16_zero;
+ }
+
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
+ * preserving the parity of the exponent. */
+
+ f64_frac = ((uint64_t) f16_frac) << (52 - 10);
+
+ f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
+
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
+ val = deposit32(0, 15, 1, f16_sign);
+ val = deposit32(val, 10, 5, f16_exp);
+ val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
+ return make_float16(val);
+}
+
+float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
+{
+ float_status *s = fpstp;
+ float32 f32 = float32_squash_input_denormal(input, s);
+ uint32_t val = float32_val(f32);
+ uint32_t f32_sign = float32_is_neg(f32);
+ int f32_exp = extract32(val, 23, 8);
+ uint32_t f32_frac = extract32(val, 0, 23);
+ uint64_t f64_frac;
+
+ if (float32_is_any_nan(f32)) {
+ float32 nan = f32;
+ if (float32_is_signaling_nan(f32, s)) {
+ float_raise(float_flag_invalid, s);
+ nan = float32_silence_nan(f32, s);
+ }
+ if (s->default_nan_mode) {
+ nan = float32_default_nan(s);
+ }
+ return nan;
+ } else if (float32_is_zero(f32)) {
+ float_raise(float_flag_divbyzero, s);
+ return float32_set_sign(float32_infinity, float32_is_neg(f32));
+ } else if (float32_is_neg(f32)) {
+ float_raise(float_flag_invalid, s);
+ return float32_default_nan(s);
+ } else if (float32_is_infinity(f32)) {
+ return float32_zero;
+ }
+
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
+ * preserving the parity of the exponent. */
+
+ f64_frac = ((uint64_t) f32_frac) << 29;
+
+ f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
+
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
+ val = deposit32(0, 31, 1, f32_sign);
+ val = deposit32(val, 23, 8, f32_exp);
+ val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
+ return make_float32(val);
+}
+
+float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
+{
+ float_status *s = fpstp;
+ float64 f64 = float64_squash_input_denormal(input, s);
+ uint64_t val = float64_val(f64);
+ bool f64_sign = float64_is_neg(f64);
+ int f64_exp = extract64(val, 52, 11);
+ uint64_t f64_frac = extract64(val, 0, 52);
+
+ if (float64_is_any_nan(f64)) {
+ float64 nan = f64;
+ if (float64_is_signaling_nan(f64, s)) {
+ float_raise(float_flag_invalid, s);
+ nan = float64_silence_nan(f64, s);
+ }
+ if (s->default_nan_mode) {
+ nan = float64_default_nan(s);
+ }
+ return nan;
+ } else if (float64_is_zero(f64)) {
+ float_raise(float_flag_divbyzero, s);
+ return float64_set_sign(float64_infinity, float64_is_neg(f64));
+ } else if (float64_is_neg(f64)) {
+ float_raise(float_flag_invalid, s);
+ return float64_default_nan(s);
+ } else if (float64_is_infinity(f64)) {
+ return float64_zero;
+ }
+
+ f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
+
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
+ val = deposit64(0, 61, 1, f64_sign);
+ val = deposit64(val, 52, 11, f64_exp);
+ val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
+ return make_float64(val);
+}
+
+uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
+{
+ /* float_status *s = fpstp; */
+ int input, estimate;
+
+ if ((a & 0x80000000) == 0) {
+ return 0xffffffff;
+ }
+
+ input = extract32(a, 23, 9);
+ estimate = recip_estimate(input);
+
+ return deposit32(0, (32 - 9), 9, estimate);
+}
+
+uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
+{
+ int estimate;
+
+ if ((a & 0xc0000000) == 0) {
+ return 0xffffffff;
+ }
+
+ estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
+
+ return deposit32(0, 23, 9, estimate);
+}
+
+/* VFPv4 fused multiply-accumulate */
+float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float32_muladd(a, b, c, 0, fpst);
+}
+
+float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float64_muladd(a, b, c, 0, fpst);
+}
+
+/* ARMv8 round to integral */
+float32 HELPER(rints_exact)(float32 x, void *fp_status)
+{
+ return float32_round_to_int(x, fp_status);
+}
+
+float64 HELPER(rintd_exact)(float64 x, void *fp_status)
+{
+ return float64_round_to_int(x, fp_status);
+}
+
+float32 HELPER(rints)(float32 x, void *fp_status)
+{
+ int old_flags = get_float_exception_flags(fp_status), new_flags;
+ float32 ret;
+
+ ret = float32_round_to_int(x, fp_status);
+
+ /* Suppress any inexact exceptions the conversion produced */
+ if (!(old_flags & float_flag_inexact)) {
+ new_flags = get_float_exception_flags(fp_status);
+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
+ }
+
+ return ret;
+}
+
+float64 HELPER(rintd)(float64 x, void *fp_status)
+{
+ int old_flags = get_float_exception_flags(fp_status), new_flags;
+ float64 ret;
+
+ ret = float64_round_to_int(x, fp_status);
+
+ new_flags = get_float_exception_flags(fp_status);
+
+ /* Suppress any inexact exceptions the conversion produced */
+ if (!(old_flags & float_flag_inexact)) {
+ new_flags = get_float_exception_flags(fp_status);
+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
+ }
+
+ return ret;
+}
+
+/* Convert ARM rounding mode to softfloat */
+int arm_rmode_to_sf(int rmode)
+{
+ switch (rmode) {
+ case FPROUNDING_TIEAWAY:
+ rmode = float_round_ties_away;
+ break;
+ case FPROUNDING_ODD:
+ /* FIXME: add support for TIEAWAY and ODD */
+ qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
+ rmode);
+ /* fall through for now */
+ case FPROUNDING_TIEEVEN:
+ default:
+ rmode = float_round_nearest_even;
+ break;
+ case FPROUNDING_POSINF:
+ rmode = float_round_up;
+ break;
+ case FPROUNDING_NEGINF:
+ rmode = float_round_down;
+ break;
+ case FPROUNDING_ZERO:
+ rmode = float_round_to_zero;
+ break;
+ }
+ return rmode;
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 1a4fc06448..6bdcc65c2c 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o
+obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
obj-y += gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
obj-$(TARGET_AARCH64) += pauth_helper.o
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs)
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv Richard Henderson
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c Richard Henderson
@ 2019-02-15 19:22 ` Richard Henderson
2019-02-19 16:57 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv Richard Henderson
` (13 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
There are lots of special cases within these insns. Split the
major argument decode/loading/saving into no_output (compares),
rd_is_dp, and rm_is_dp.
We still need to special case argument load for compare (rd as
input, rm as zero) and vcvt fixed (rd as input+output), but lots
of special cases do disappear.
Now that we have a full switch at the beginning, hoist the ISA
checks from the code generation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 227 ++++++++++++++++++++---------------------
1 file changed, 111 insertions(+), 116 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index dac737f6ca..64c5fe0df3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3639,52 +3639,108 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
}
} else {
/* data processing */
+ bool rd_is_dp = dp;
+ bool rm_is_dp = dp;
+ bool no_output = false;
+
/* The opcode is in bits 23, 21, 20 and 6. */
op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
- if (dp) {
- if (op == 15) {
- /* rn is opcode */
- rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
- } else {
- /* rn is register number */
- VFP_DREG_N(rn, insn);
- }
+ rn = VFP_SREG_N(insn);
- if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18) ||
- ((rn & 0x1e) == 0x6))) {
- /* Integer or single/half precision destination. */
- rd = VFP_SREG_D(insn);
- } else {
- VFP_DREG_D(rd, insn);
- }
- if (op == 15 &&
- (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14) ||
- ((rn & 0x1e) == 0x4))) {
- /* VCVT from int or half precision is always from S reg
- * regardless of dp bit. VCVT with immediate frac_bits
- * has same format as SREG_M.
+ if (op == 15) {
+ /* rn is opcode, encoded as per VFP_SREG_N. */
+ switch (rn) {
+ case 0x00: /* vmov */
+ case 0x01: /* vabs */
+ case 0x02: /* vneg */
+ case 0x03: /* vsqrt */
+ break;
+
+ case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */
+ case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */
+ /*
+ * VCVTB, VCVTT: only present with the halfprec extension
+ * UNPREDICTABLE if bit 8 is set prior to ARMv8
+ * (we choose to UNDEF)
*/
- rm = VFP_SREG_M(insn);
- } else {
- VFP_DREG_M(rm, insn);
+ if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
+ !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
+ return 1;
+ }
+ rm_is_dp = false;
+ break;
+ case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
+ case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
+ if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
+ !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
+ return 1;
+ }
+ rd_is_dp = false;
+ break;
+
+ case 0x08: case 0x0a: /* vcmp, vcmpz */
+ case 0x09: case 0x0b: /* vcmpe, vcmpez */
+ no_output = true;
+ break;
+
+ case 0x0c: /* vrintr */
+ case 0x0d: /* vrintz */
+ case 0x0e: /* vrintx */
+ break;
+
+ case 0x0f: /* vcvt double<->single */
+ rd_is_dp = !dp;
+ break;
+
+ case 0x10: /* vcvt.fxx.u32 */
+ case 0x11: /* vcvt.fxx.s32 */
+ rm_is_dp = false;
+ break;
+ case 0x18: /* vcvtr.u32.fxx */
+ case 0x19: /* vcvtz.u32.fxx */
+ case 0x1a: /* vcvtr.s32.fxx */
+ case 0x1b: /* vcvtz.s32.fxx */
+ rd_is_dp = false;
+ break;
+
+ case 0x14: /* vcvt fp <-> fixed */
+ case 0x15:
+ case 0x16:
+ case 0x17:
+ case 0x1c:
+ case 0x1d:
+ case 0x1e:
+ case 0x1f:
+ if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ return 1;
+ }
+ /* Immediate frac_bits has same format as SREG_M. */
+ rm_is_dp = false;
+ break;
+
+ default:
+ return 1;
}
+ } else if (dp) {
+ /* rn is register number */
+ VFP_DREG_N(rn, insn);
+ }
+
+ if (rd_is_dp) {
+ VFP_DREG_D(rd, insn);
+ } else {
+ rd = VFP_SREG_D(insn);
+ }
+ if (rm_is_dp) {
+ VFP_DREG_M(rm, insn);
} else {
- rn = VFP_SREG_N(insn);
- if (op == 15 && rn == 15) {
- /* Double precision destination. */
- VFP_DREG_D(rd, insn);
- } else {
- rd = VFP_SREG_D(insn);
- }
- /* NB that we implicitly rely on the encoding for the frac_bits
- * in VCVT of fixed to float being the same as that of an SREG_M
- */
rm = VFP_SREG_M(insn);
}
veclen = s->vec_len;
- if (op == 15 && rn > 3)
+ if (op == 15 && rn > 3) {
veclen = 0;
+ }
/* Shut up compiler warnings. */
delta_m = 0;
@@ -3720,55 +3776,28 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
/* Load the initial operands. */
if (op == 15) {
switch (rn) {
- case 16:
- case 17:
- /* Integer source */
- gen_mov_F0_vreg(0, rm);
- break;
- case 8:
- case 9:
- /* Compare */
+ case 0x08: case 0x09: /* Compare */
gen_mov_F0_vreg(dp, rd);
gen_mov_F1_vreg(dp, rm);
break;
- case 10:
- case 11:
- /* Compare with zero */
+ case 0x0a: case 0x0b: /* Compare with zero */
gen_mov_F0_vreg(dp, rd);
gen_vfp_F1_ld0(dp);
break;
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
+ case 0x14: /* vcvt fp <-> fixed */
+ case 0x15:
+ case 0x16:
+ case 0x17:
+ case 0x1c:
+ case 0x1d:
+ case 0x1e:
+ case 0x1f:
/* Source and destination the same. */
gen_mov_F0_vreg(dp, rd);
break;
- case 4:
- case 5:
- case 6:
- case 7:
- /* VCVTB, VCVTT: only present with the halfprec extension
- * UNPREDICTABLE if bit 8 is set prior to ARMv8
- * (we choose to UNDEF)
- */
- if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
- !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
- return 1;
- }
- if (!extract32(rn, 1, 1)) {
- /* Half precision source. */
- gen_mov_F0_vreg(0, rm);
- break;
- }
- /* Otherwise fall through */
default:
/* One source operand. */
- gen_mov_F0_vreg(dp, rm);
+ gen_mov_F0_vreg(rm_is_dp, rm);
break;
}
} else {
@@ -4047,10 +4076,11 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
break;
}
case 15: /* single<->double conversion */
- if (dp)
+ if (dp) {
gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
- else
+ } else {
gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
+ }
break;
case 16: /* fuito */
gen_vfp_uito(dp, 0);
@@ -4059,27 +4089,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
gen_vfp_sito(dp, 0);
break;
case 20: /* fshto */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_shto(dp, 16 - rm, 0);
break;
case 21: /* fslto */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_slto(dp, 32 - rm, 0);
break;
case 22: /* fuhto */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_uhto(dp, 16 - rm, 0);
break;
case 23: /* fulto */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_ulto(dp, 32 - rm, 0);
break;
case 24: /* ftoui */
@@ -4095,57 +4113,34 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
gen_vfp_tosiz(dp, 0);
break;
case 28: /* ftosh */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_tosh(dp, 16 - rm, 0);
break;
case 29: /* ftosl */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_tosl(dp, 32 - rm, 0);
break;
case 30: /* ftouh */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_touh(dp, 16 - rm, 0);
break;
case 31: /* ftoul */
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return 1;
- }
gen_vfp_toul(dp, 32 - rm, 0);
break;
default: /* undefined */
- return 1;
+ g_assert_not_reached();
}
break;
default: /* undefined */
return 1;
}
- /* Write back the result. */
- if (op == 15 && (rn >= 8 && rn <= 11)) {
- /* Comparison, do nothing. */
- } else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
- (rn & 0x1e) == 0x6)) {
- /* VCVT double to int: always integer result.
- * VCVT double to half precision is always a single
- * precision result.
- */
- gen_mov_vreg_F0(0, rd);
- } else if (op == 15 && rn == 15) {
- /* conversion */
- gen_mov_vreg_F0(!dp, rd);
- } else {
- gen_mov_vreg_F0(dp, rd);
+ /* Write back the result, if any. */
+ if (!no_output) {
+ gen_mov_vreg_F0(rd_is_dp, rd);
}
/* break out of the loop if we have finished */
- if (veclen == 0)
+ if (veclen == 0) {
break;
+ }
if (op == 15 && delta_m == 0) {
/* single source one-many */
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (2 preceding siblings ...)
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs) Richard Henderson
@ 2019-02-15 19:22 ` Richard Henderson
2019-02-19 17:06 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL Richard Henderson
` (12 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Return 0 for NaN
v3: Return aa32 flags in FPSCR.NZCV.
---
target/arm/cpu.h | 10 +++++
target/arm/helper.h | 3 ++
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 +
target/arm/translate-a64.c | 26 +++++++++++
target/arm/translate.c | 10 +++++
target/arm/vfp_helper.c | 88 ++++++++++++++++++++++++++++++++++++++
7 files changed, 140 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 84ae6849c2..1eea1a408b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3273,6 +3273,11 @@ static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
}
+static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
+}
+
static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
@@ -3351,6 +3356,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
}
+static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
+}
+
static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 923e8e1525..747cb64d29 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -218,6 +218,9 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
+DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
+
/* neon_helper.c */
DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index edf6e0e1f1..8ea6569088 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2001,6 +2001,7 @@ static void arm_max_initfn(Object *obj)
cpu->isar.id_isar5 = t;
t = cpu->isar.id_isar6;
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
cpu->isar.id_isar6 = t;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index eff0f164dd..69e4134f79 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
@@ -344,6 +345,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_isar5 = u;
u = cpu->isar.id_isar6;
+ u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
cpu->isar.id_isar6 = u;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index dbce24fe32..c56e878787 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6526,6 +6526,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
}
}
+static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
+{
+ TCGv_i64 t = read_fp_dreg(s, rn);
+ TCGv_ptr fpstatus = get_fpstatus_ptr(false);
+
+ gen_helper_fjcvtzs(t, t, fpstatus);
+
+ tcg_temp_free_ptr(fpstatus);
+
+ tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
+ tcg_gen_extrh_i64_i32(cpu_ZF, t);
+ tcg_gen_movi_i32(cpu_CF, 0);
+ tcg_gen_movi_i32(cpu_NF, 0);
+ tcg_gen_movi_i32(cpu_VF, 0);
+
+ tcg_temp_free_i64(t);
+}
+
/* Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
@@ -6601,6 +6619,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
handle_fmov(s, rd, rn, type, itof);
break;
+ case 0b00111110: /* FJCVTZS */
+ if (!dc_isar_feature(aa64_jscvt, s)) {
+ goto do_unallocated;
+ } else if (fp_access_check(s)) {
+ handle_fjcvtzs(s, rd, rn);
+ }
+ break;
+
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 64c5fe0df3..c1175798ac 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3718,6 +3718,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rm_is_dp = false;
break;
+ case 0x13: /* vjcvt */
+ if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
+ return 1;
+ }
+ rd_is_dp = false;
+ break;
+
default:
return 1;
}
@@ -4088,6 +4095,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
case 17: /* fsito */
gen_vfp_sito(dp, 0);
break;
+ case 19: /* vjcvt */
+ gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env);
+ break;
case 20: /* fshto */
gen_vfp_shto(dp, 16 - rm, 0);
break;
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 74d3030c47..f19c0606c2 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1086,3 +1086,91 @@ int arm_rmode_to_sf(int rmode)
}
return rmode;
}
+
+/*
+ * Implement float64 to int32_t conversion without saturation;
+ * the result is supplied modulo 2^32.
+ */
+uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
+{
+ float_status *status = vstatus;
+ uint32_t exp, sign;
+ uint64_t frac;
+ uint32_t inexact = 1; /* !Z */
+
+ sign = extract64(value, 63, 1);
+ exp = extract64(value, 52, 11);
+ frac = extract64(value, 0, 52);
+
+ if (exp == 0) {
+ /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
+ inexact = sign;
+ if (frac != 0) {
+ if (status->flush_inputs_to_zero) {
+ float_raise(float_flag_input_denormal, status);
+ } else {
+ float_raise(float_flag_inexact, status);
+ inexact = 1;
+ }
+ }
+ frac = 0;
+ } else if (exp == 0x7ff) {
+ /* This operation raises Invalid for both NaN and overflow (Inf). */
+ float_raise(float_flag_invalid, status);
+ frac = 0;
+ } else {
+ int true_exp = exp - 1023;
+ int shift = true_exp - 52;
+
+ /* Restore implicit bit. */
+ frac |= 1ull << 52;
+
+ /* Shift the fraction into place. */
+ if (shift >= 0) {
+ /* The number is so large we must shift the fraction left. */
+ if (shift >= 64) {
+ /* The the fraction is shifted out entirely. */
+ frac = 0;
+ } else {
+ frac <<= shift;
+ }
+ } else if (shift > -64) {
+ /* Normal case -- shift right and notice if bits shift out. */
+ inexact = (frac << (64 + shift)) != 0;
+ frac >>= -shift;
+ } else {
+ /* The fraction is shifted out entirely. */
+ frac = 0;
+ }
+
+ /* Notice overflow or inexact exceptions. */
+ if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
+ /* Overflow, for which this operation raises invalid. */
+ float_raise(float_flag_invalid, status);
+ inexact = 1;
+ } else if (inexact) {
+ float_raise(float_flag_inexact, status);
+ }
+
+ /* Honor the sign. */
+ if (sign) {
+ frac = -frac;
+ }
+ }
+
+ /* Pack the result and the env->ZF representation of Z together. */
+ return deposit64(frac, 32, 32, inexact);
+}
+
+uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
+{
+ uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
+ uint32_t result = pair;
+ uint32_t z = (pair >> 32) == 0;
+
+ /* Store Z, clear NCV, in FPSCR.NZCF. */
+ env->vfp.xregs[ARM_VFP_FPSCR]
+ = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
+
+ return result;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (3 preceding siblings ...)
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv Richard Henderson
@ 2019-02-15 19:22 ` Richard Henderson
2019-02-19 17:31 ` Peter Maydell
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64 Richard Henderson
` (11 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected. Thus float16_to_float32_by_bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 5 ++
target/arm/vec_helper.c | 114 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 119 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 747cb64d29..03a613a00b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -677,6 +677,11 @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index dfc635cf9a..224e5315b1 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -898,3 +898,117 @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
}
clear_tail(d, oprsz, simd_maxsz(desc));
}
+
+/*
+ * Convert float16 to float32, raising no exceptions and
+ * preserving exceptional values, including SNaN.
+ * This is effectively an unpack+repack operation.
+ */
+static float32 float16_to_float32_by_bits(uint32_t f16)
+{
+ const int f16_bias = 15;
+ const int f32_bias = 127;
+ uint32_t sign = extract32(f16, 15, 1);
+ uint32_t exp = extract32(f16, 10, 5);
+ uint32_t frac = extract32(f16, 0, 10);
+
+ if (exp == 0x1f) {
+ /* Inf or NaN */
+ exp = 0xff;
+ } else if (exp == 0) {
+ /* Zero or denormal. */
+ if (frac != 0) {
+ /*
+ * Denormal; these are all normal float32.
+ * Shift the fraction so that the msb is at bit 11,
+ * then remove bit 11 as the implicit bit of the
+ * normalized float32. Note that we still go through
+ * the shift for normal numbers below, to put the
+ * float32 fraction at the right place.
+ */
+ int shift = clz32(frac) - 21;
+ frac = (frac << shift) & 0x3ff;
+ exp = f32_bias - f16_bias - shift + 1;
+ }
+ } else {
+ /* Normal number; adjust the bias. */
+ exp += f32_bias - f16_bias;
+ }
+ sign <<= 31;
+ exp <<= 23;
+ frac <<= 23 - 10;
+
+ return sign | exp | frac;
+}
+
+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
+{
+ /*
+ * Branchless load of u32[0], u64[0], u32[1], or u64[1].
+ * Load the 2nd qword iff is_q & is_2.
+ * Shift to the 2nd dword iff !is_q & is_2.
+ * For !is_q & !is_2, the upper bits of the result are garbage.
+ */
+ return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
+}
+
+/*
+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
+ * as there is not yet SVE versions that might use blocking.
+ */
+
+void HELPER(gvec_fmlal_h)(void *vd, void *vn, void *vm,
+ void *fpst, uint32_t desc)
+{
+ intptr_t i, oprsz = simd_oprsz(desc);
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ int is_q = oprsz == 16;
+ float32 *d = vd;
+ uint64_t n_4, m_4;
+
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
+ n_4 = load4_f16(vn, is_q, is_2);
+ m_4 = load4_f16(vm, is_q, is_2);
+
+ /* Negate all inputs for FMLSL at once. */
+ if (is_s) {
+ n_4 ^= 0x8000800080008000ull;
+ }
+
+ for (i = 0; i < oprsz / 4; i++) {
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16));
+ float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16));
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+ }
+ clear_tail(d, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmlal_idx_h)(void *vd, void *vn, void *vm,
+ void *fpst, uint32_t desc)
+{
+ intptr_t i, oprsz = simd_oprsz(desc);
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
+ int is_q = oprsz == 16;
+ float32 *d = vd;
+ uint64_t n_4;
+ float32 m_1;
+
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
+ n_4 = load4_f16(vn, is_q, is_2);
+
+ /* Negate all inputs for FMLSL at once. */
+ if (is_s) {
+ n_4 ^= 0x8000800080008000ull;
+ }
+
+ m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)]);
+
+ for (i = 0; i < oprsz / 4; i++) {
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16));
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+ }
+ clear_tail(d, oprsz, simd_maxsz(desc));
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (4 preceding siblings ...)
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL Richard Henderson
@ 2019-02-15 19:23 ` Richard Henderson
2019-02-19 17:43 ` Peter Maydell
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 7/8] target/arm: Implement VFMAL and VFMSL for aarch32 Richard Henderson
` (10 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:23 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 5 ++++
target/arm/translate-a64.c | 50 +++++++++++++++++++++++++++++++++++++-
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1eea1a408b..69589573e4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3356,6 +3356,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
}
+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
+}
+
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c56e878787..9a4c561982 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10917,9 +10917,26 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
if (!fp_access_check(s)) {
return;
}
-
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
return;
+
+ case 0x1d: /* FMLAL */
+ case 0x3d: /* FMLSL */
+ case 0x59: /* FMLAL2 */
+ case 0x79: /* FMLSL2 */
+ if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (fp_access_check(s)) {
+ int is_s = extract32(insn, 23, 1);
+ int is_2 = extract32(insn, 29, 1);
+ int data = (is_2 << 1) | is_s;
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, data,
+ gen_helper_gvec_fmlal_h);
+ }
+ return;
+
default:
unallocated_encoding(s);
return;
@@ -12739,6 +12756,17 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
is_fp = 2;
break;
+ case 0x00: /* FMLAL */
+ case 0x04: /* FMLSL */
+ case 0x18: /* FMLAL2 */
+ case 0x1c: /* FMLSL2 */
+ if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = MO_16;
+ is_fp = 3;
+ break;
default:
unallocated_encoding(s);
return;
@@ -12780,6 +12808,9 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
break;
+ case 3: /* other fp, size already set and verified. */
+ break;
+
default: /* integer */
switch (size) {
case MO_8:
@@ -12849,6 +12880,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
tcg_temp_free_ptr(fpst);
}
return;
+
+ case 0x00: /* FMLAL */
+ case 0x04: /* FMLSL */
+ case 0x18: /* FMLAL2 */
+ case 0x1c: /* FMLSL2 */
+ {
+ int is_s = extract32(opcode, 2, 1);
+ int is_2 = u;
+ int data = (index << 2) | (is_2 << 1) | is_s;
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), fpst,
+ is_q ? 16 : 8, vec_full_reg_size(s), data,
+ gen_helper_gvec_fmlal_idx_h);
+ tcg_temp_free_ptr(fpst);
+ }
+ return;
}
if (size == 3) {
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 7/8] target/arm: Implement VFMAL and VFMSL for aarch32
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (5 preceding siblings ...)
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64 Richard Henderson
@ 2019-02-15 19:23 ` Richard Henderson
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max Richard Henderson
` (9 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:23 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 5 ++
target/arm/translate.c | 103 +++++++++++++++++++++++++++++------------
2 files changed, 79 insertions(+), 29 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 69589573e4..9cf439fb8d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3283,6 +3283,11 @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
}
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
+}
+
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
{
/*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c1175798ac..c319ba9aae 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8372,15 +8372,8 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
int rd, rn, rm, opr_sz;
int data = 0;
- bool q;
-
- q = extract32(insn, 6, 1);
- VFP_DREG_D(rd, insn);
- VFP_DREG_N(rn, insn);
- VFP_DREG_M(rm, insn);
- if ((rd | rn | rm) & q) {
- return 1;
- }
+ int off_rn, off_rm;
+ bool is_long = false, q = extract32(insn, 6, 1);
if ((insn & 0xfe200f10) == 0xfc200800) {
/* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
@@ -8407,10 +8400,38 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
return 1;
}
fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
+ } else if ((insn & 0xff300f10) == 0xfc200810) {
+ /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
+ int is_s = extract32(insn, 23, 1);
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return 1;
+ }
+ is_long = true;
+ fn_gvec_ptr = gen_helper_gvec_fmlal_h;
+ data = is_s; /* is_2 == 0 */
} else {
return 1;
}
+ VFP_DREG_D(rd, insn);
+ if (rd & q) {
+ return 1;
+ }
+ if (q || !is_long) {
+ VFP_DREG_N(rn, insn);
+ VFP_DREG_M(rm, insn);
+ if ((rn | rm) & q & !is_long) {
+ return 1;
+ }
+ off_rn = vfp_reg_offset(1, rn);
+ off_rm = vfp_reg_offset(1, rm);
+ } else {
+ rn = VFP_SREG_N(insn);
+ rm = VFP_SREG_M(insn);
+ off_rn = vfp_reg_offset(0, rn);
+ off_rm = vfp_reg_offset(0, rm);
+ }
+
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -8423,15 +8444,11 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
opr_sz = (1 + q) * 8;
if (fn_gvec_ptr) {
TCGv_ptr fpst = get_fpstatus_ptr(1);
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
- vfp_reg_offset(1, rn),
- vfp_reg_offset(1, rm), fpst,
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst,
opr_sz, opr_sz, data, fn_gvec_ptr);
tcg_temp_free_ptr(fpst);
} else {
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
- vfp_reg_offset(1, rn),
- vfp_reg_offset(1, rm),
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
opr_sz, opr_sz, data, fn_gvec);
}
return 0;
@@ -8450,14 +8467,8 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
gen_helper_gvec_3 *fn_gvec = NULL;
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
int rd, rn, rm, opr_sz, data;
- bool q;
-
- q = extract32(insn, 6, 1);
- VFP_DREG_D(rd, insn);
- VFP_DREG_N(rn, insn);
- if ((rd | rn) & q) {
- return 1;
- }
+ int off_rn, off_rm;
+ bool is_long = false, q = extract32(insn, 6, 1);
if ((insn & 0xff000f10) == 0xfe000800) {
/* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
@@ -8486,6 +8497,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
} else if ((insn & 0xffb00f00) == 0xfe200d00) {
/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
int u = extract32(insn, 4, 1);
+
if (!dc_isar_feature(aa32_dp, s)) {
return 1;
}
@@ -8493,10 +8505,47 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
/* rm is just Vm, and index is M. */
data = extract32(insn, 5, 1); /* index */
rm = extract32(insn, 0, 4);
+ } else if ((insn & 0xffa00f10) == 0xfe000810) {
+ /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
+ int is_s = extract32(insn, 20, 1);
+ int vm20 = extract32(insn, 0, 3);
+ int vm3 = extract32(insn, 3, 1);
+ int m = extract32(insn, 5, 1);
+ int index;
+
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return 1;
+ }
+ if (q) {
+ rm = vm20;
+ index = m * 2 + vm3;
+ } else {
+ rm = vm20 * 2 + m;
+ index = vm3;
+ }
+ is_long = true;
+ data = (index << 2) | is_s; /* is_2 == 0 */
+ fn_gvec_ptr = gen_helper_gvec_fmlal_idx_h;
} else {
return 1;
}
+ VFP_DREG_D(rd, insn);
+ if (rd & q) {
+ return 1;
+ }
+ if (q || !is_long) {
+ VFP_DREG_N(rn, insn);
+ if (rn & q & !is_long) {
+ return 1;
+ }
+ off_rn = vfp_reg_offset(1, rn);
+ off_rm = vfp_reg_offset(1, rm);
+ } else {
+ rn = VFP_SREG_N(insn);
+ off_rn = vfp_reg_offset(0, rn);
+ off_rm = vfp_reg_offset(0, rm);
+ }
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -8509,15 +8558,11 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
opr_sz = (1 + q) * 8;
if (fn_gvec_ptr) {
TCGv_ptr fpst = get_fpstatus_ptr(1);
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
- vfp_reg_offset(1, rn),
- vfp_reg_offset(1, rm), fpst,
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst,
opr_sz, opr_sz, data, fn_gvec_ptr);
tcg_temp_free_ptr(fpst);
} else {
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
- vfp_reg_offset(1, rn),
- vfp_reg_offset(1, rm),
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
opr_sz, opr_sz, data, fn_gvec);
}
return 0;
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (6 preceding siblings ...)
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 7/8] target/arm: Implement VFMAL and VFMSL for aarch32 Richard Henderson
@ 2019-02-15 19:23 ` Richard Henderson
2019-02-19 17:13 ` Peter Maydell
2019-02-15 19:54 ` [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM no-reply
` (8 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2019-02-15 19:23 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8ea6569088..b9fa548718 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2003,6 +2003,7 @@ static void arm_max_initfn(Object *obj)
t = cpu->isar.id_isar6;
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
cpu->isar.id_isar6 = t;
t = cpu->id_mmfr4;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 69e4134f79..1b0c427277 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -308,6 +308,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64isar1;
@@ -347,6 +348,7 @@ static void aarch64_max_initfn(Object *obj)
u = cpu->isar.id_isar6;
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
+ u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
cpu->isar.id_isar6 = u;
/*
--
2.17.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (7 preceding siblings ...)
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max Richard Henderson
@ 2019-02-15 19:54 ` no-reply
2019-02-15 19:57 ` no-reply
` (7 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-15 19:54 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190123103323.4516-1-stefanha@redhat.com -> patchew/20190123103323.4516-1-stefanha@redhat.com
* [new tag] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
Switched to a new branch 'test'
48aad41d17 target/arm: Enable ARMv8.2-FHM for -cpu max
386bd84229 target/arm: Implement VFMAL and VFMSL for aarch32
bd511444da target/arm: Implement FMLAL and FMLSL for aarch64
320923b415 target/arm: Add helpers for FMLAL
5f16dc5cd4 target/arm: Implement ARMv8.3-JSConv
4e880a6881 target/arm: Rearrange Floating-point data-processing (2 regs)
ec64414896 target/arm: Split out vfp_helper.c
537337ef14 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit 537337ef142f (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit ec64414896da (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1101:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1133: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1134: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1135: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1142: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1144: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1146: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1148: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1150: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1152: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1188: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1190: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1192: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1194: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1196: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1198: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1270: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1285: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1285: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1287: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1399: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1402: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1446: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1451: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1551: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1564: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1584: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1597: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1610: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1623: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1668: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1669: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1676: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1682: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1902: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1984: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1985: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2028: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2029: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 4e880a68817d (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit 5f16dc5cd4a4 (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit 320923b41576 (target/arm: Add helpers for FMLAL)
6/8 Checking commit bd511444da88 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 386bd8422967 (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 48aad41d17ed (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (8 preceding siblings ...)
2019-02-15 19:54 ` [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM no-reply
@ 2019-02-15 19:57 ` no-reply
2019-02-19 15:58 ` no-reply
` (6 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-15 19:57 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190123103323.4516-1-stefanha@redhat.com -> patchew/20190123103323.4516-1-stefanha@redhat.com
* [new tag] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '3464681b2b5983df80086a40179d324102347da3'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
48aad41 target/arm: Enable ARMv8.2-FHM for -cpu max
386bd84 target/arm: Implement VFMAL and VFMSL for aarch32
bd51144 target/arm: Implement FMLAL and FMLSL for aarch64
320923b target/arm: Add helpers for FMLAL
5f16dc5 target/arm: Implement ARMv8.3-JSConv
4e880a6 target/arm: Rearrange Floating-point data-processing (2 regs)
ec64414 target/arm: Split out vfp_helper.c
537337e target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit 537337ef142f (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit ec64414896da (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1101:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1133: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1134: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1135: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1142: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1144: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1146: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1148: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1150: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1152: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1188: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1190: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1192: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1194: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1196: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1198: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1270: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1285: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1285: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1287: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1399: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1402: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1446: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1451: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1551: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1564: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1584: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1597: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1610: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1623: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1668: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1669: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1676: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1682: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1902: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1984: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1985: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2028: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2029: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 4e880a68817d (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit 5f16dc5cd4a4 (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit 320923b41576 (target/arm: Add helpers for FMLAL)
6/8 Checking commit bd511444da88 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 386bd8422967 (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 48aad41d17ed (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv Richard Henderson
@ 2019-02-19 15:28 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 15:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> For opcodes 0-5, move some if conditions into the structure
> of a switch statement. For opcodes 6 & 7, decode everything
> at once with a second switch.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-a64.c | 94 ++++++++++++++++++++------------------
> 1 file changed, 49 insertions(+), 45 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(this is identical to the JSConv v2 patchset patch 2 which I
reviewed, as far as I can tell.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c Richard Henderson
@ 2019-02-19 15:32 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 15:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move all of the fp helpers out of helper.c into a new file.
> This is code movement only. Since helper.c has no copyright
> header, take the one from cpu.h for the new file.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.c | 1062 -------------------------------------
> target/arm/vfp_helper.c | 1088 ++++++++++++++++++++++++++++++++++++++
> target/arm/Makefile.objs | 2 +-
> 3 files changed, 1089 insertions(+), 1063 deletions(-)
> create mode 100644 target/arm/vfp_helper.c
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(confirmed the code motion using git diff --color-moved)
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (9 preceding siblings ...)
2019-02-15 19:57 ` no-reply
@ 2019-02-19 15:58 ` no-reply
2019-02-19 16:02 ` no-reply
` (5 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 15:58 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
51dd832232 target/arm: Enable ARMv8.2-FHM for -cpu max
736c5e9e30 target/arm: Implement VFMAL and VFMSL for aarch32
b3f9f6a883 target/arm: Implement FMLAL and FMLSL for aarch64
cbf8a7e3d5 target/arm: Add helpers for FMLAL
4cb90fe69d target/arm: Implement ARMv8.3-JSConv
9cef9e67a2 target/arm: Rearrange Floating-point data-processing (2 regs)
6378838a3d target/arm: Split out vfp_helper.c
aead6fb4e1 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit aead6fb4e175 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 6378838a3d44 (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 9cef9e67a26e (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit 4cb90fe69d5a (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit cbf8a7e3d53f (target/arm: Add helpers for FMLAL)
6/8 Checking commit b3f9f6a883c6 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 736c5e9e3077 (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 51dd832232a6 (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (10 preceding siblings ...)
2019-02-19 15:58 ` no-reply
@ 2019-02-19 16:02 ` no-reply
2019-02-19 17:28 ` no-reply
` (4 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 16:02 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
* [new tag] patchew/20190219153727.62279-1-stephen.checkoway@oberlin.edu -> patchew/20190219153727.62279-1-stephen.checkoway@oberlin.edu
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '3464681b2b5983df80086a40179d324102347da3'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
51dd832 target/arm: Enable ARMv8.2-FHM for -cpu max
736c5e9 target/arm: Implement VFMAL and VFMSL for aarch32
b3f9f6a target/arm: Implement FMLAL and FMLSL for aarch64
cbf8a7e target/arm: Add helpers for FMLAL
4cb90fe target/arm: Implement ARMv8.3-JSConv
9cef9e6 target/arm: Rearrange Floating-point data-processing (2 regs)
6378838 target/arm: Split out vfp_helper.c
aead6fb target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit aead6fb4e175 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 6378838a3d44 (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 9cef9e67a26e (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit 4cb90fe69d5a (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit cbf8a7e3d53f (target/arm: Add helpers for FMLAL)
6/8 Checking commit b3f9f6a883c6 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 736c5e9e3077 (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 51dd832232a6 (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs)
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs) Richard Henderson
@ 2019-02-19 16:57 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 16:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There are lots of special cases within these insns. Split the
> major argument decode/loading/saving into no_output (compares),
> rd_is_dp, and rm_is_dp.
>
> We still need to special case argument load for compare (rd as
> input, rm as zero) and vcvt fixed (rd as input+output), but lots
> of special cases do disappear.
>
> Now that we have a full switch at the beginning, hoist the ISA
> checks from the code generation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv Richard Henderson
@ 2019-02-19 17:06 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 17:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Return 0 for NaN
> v3: Return aa32 flags in FPSCR.NZCV.
> + /* The number is so large we must shift the fraction left. */
> + if (shift >= 64) {
> + /* The the fraction is shifted out entirely. */
Stil "The the".
> + frac = 0;
> + } else {
> + frac <<= shift;
> + }
> +uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
> +{
> + uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
> + uint32_t result = pair;
> + uint32_t z = (pair >> 32) == 0;
> +
> + /* Store Z, clear NCV, in FPSCR.NZCF. */
"NZCV".
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
If these are the only issues in the series I'll fix them as
I apply it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max Richard Henderson
@ 2019-02-19 17:13 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 17:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 8ea6569088..b9fa548718 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2003,6 +2003,7 @@ static void arm_max_initfn(Object *obj)
> t = cpu->isar.id_isar6;
> t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
> t = FIELD_DP32(t, ID_ISAR6, DP, 1);
> + t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
> cpu->isar.id_isar6 = t;
>
> t = cpu->id_mmfr4;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 69e4134f79..1b0c427277 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -308,6 +308,7 @@ static void aarch64_max_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
> t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
> t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
> + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
> cpu->isar.id_aa64isar0 = t;
>
> t = cpu->isar.id_aa64isar1;
> @@ -347,6 +348,7 @@ static void aarch64_max_initfn(Object *obj)
> u = cpu->isar.id_isar6;
> u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
> u = FIELD_DP32(u, ID_ISAR6, DP, 1);
> + u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
> cpu->isar.id_isar6 = u;
>
> /*
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
We also need to set the HWCAP_ASIMDFHM and HWCAP_JSCVT hwcaps
for linux-user based on the ID regs, but we can do that as
an extra patch on top of this set.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (11 preceding siblings ...)
2019-02-19 16:02 ` no-reply
@ 2019-02-19 17:28 ` no-reply
2019-02-19 17:32 ` no-reply
` (3 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 17:28 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
eccbd527ca target/arm: Enable ARMv8.2-FHM for -cpu max
86326a505b target/arm: Implement VFMAL and VFMSL for aarch32
2ae450b769 target/arm: Implement FMLAL and FMLSL for aarch64
09e02de06d target/arm: Add helpers for FMLAL
ebc9d4e523 target/arm: Implement ARMv8.3-JSConv
f51742b4ab target/arm: Rearrange Floating-point data-processing (2 regs)
65a437834f target/arm: Split out vfp_helper.c
b83a695b43 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit b83a695b4342 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 65a437834fac (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit f51742b4abf6 (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit ebc9d4e5231b (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit 09e02de06d1f (target/arm: Add helpers for FMLAL)
6/8 Checking commit 2ae450b76917 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 86326a505b6d (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit eccbd527cae1 (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL Richard Henderson
@ 2019-02-19 17:31 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 17:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Note that float16_to_float32 rightly squashes SNaN to QNaN.
> But of course pickNaNMulAdd, for ARM, selects SNaNs first.
> So we have to preserve SNaN long enough for the correct NaN
> to be selected. Thus float16_to_float32_by_bits.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> +/*
> + * Convert float16 to float32, raising no exceptions and
> + * preserving exceptional values, including SNaN.
> + * This is effectively an unpack+repack operation.
> + */
> +static float32 float16_to_float32_by_bits(uint32_t f16)
> +{
> + const int f16_bias = 15;
> + const int f32_bias = 127;
> + uint32_t sign = extract32(f16, 15, 1);
> + uint32_t exp = extract32(f16, 10, 5);
> + uint32_t frac = extract32(f16, 0, 10);
> +
> + if (exp == 0x1f) {
> + /* Inf or NaN */
> + exp = 0xff;
> + } else if (exp == 0) {
> + /* Zero or denormal. */
> + if (frac != 0) {
> + /*
> + * Denormal; these are all normal float32.
> + * Shift the fraction so that the msb is at bit 11,
> + * then remove bit 11 as the implicit bit of the
> + * normalized float32. Note that we still go through
> + * the shift for normal numbers below, to put the
> + * float32 fraction at the right place.
> + */
> + int shift = clz32(frac) - 21;
> + frac = (frac << shift) & 0x3ff;
> + exp = f32_bias - f16_bias - shift + 1;
> + }
> + } else {
> + /* Normal number; adjust the bias. */
> + exp += f32_bias - f16_bias;
> + }
> + sign <<= 31;
> + exp <<= 23;
> + frac <<= 23 - 10;
> +
> + return sign | exp | frac;
> +}
Shouldn't we be observing FPCR.FZ16 here and flushing
denormal float16 inputs to zero if it's set ?
(In the pseudocode this happens in FPUnpackBase, called
from FPUnpack.)
NB: this might be awkward because for A64 we need to use the
fpstatus with FZ16 in it (vfp.fp_status_f16) for the float16
inputs, but the one with the normal FZ bit (vfp.fp_status)
for the float32 input.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (12 preceding siblings ...)
2019-02-19 17:28 ` no-reply
@ 2019-02-19 17:32 ` no-reply
2019-02-19 17:46 ` Peter Maydell
` (2 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 17:32 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
- [tag update] patchew/20190219161321.15012-1-berrange@redhat.com -> patchew/20190219161321.15012-1-berrange@redhat.com
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '3464681b2b5983df80086a40179d324102347da3'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
eccbd52 target/arm: Enable ARMv8.2-FHM for -cpu max
86326a5 target/arm: Implement VFMAL and VFMSL for aarch32
2ae450b target/arm: Implement FMLAL and FMLSL for aarch64
09e02de target/arm: Add helpers for FMLAL
ebc9d4e target/arm: Implement ARMv8.3-JSConv
f51742b target/arm: Rearrange Floating-point data-processing (2 regs)
65a4378 target/arm: Split out vfp_helper.c
b83a695 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit b83a695b4342 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 65a437834fac (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit f51742b4abf6 (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit ebc9d4e5231b (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit 09e02de06d1f (target/arm: Add helpers for FMLAL)
6/8 Checking commit 2ae450b76917 (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit 86326a505b6d (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit eccbd527cae1 (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64 Richard Henderson
@ 2019-02-19 17:43 ` Peter Maydell
0 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 17:43 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Encoding stuff is all OK, but as noted in previous email
I think we're going to have fpstatus awkwardness.
(The code in this patch always selects the non-fp16
fpstatus, which is right for everything except for
handling FZ16 on the float16 inputs.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (13 preceding siblings ...)
2019-02-19 17:32 ` no-reply
@ 2019-02-19 17:46 ` Peter Maydell
2019-02-19 17:53 ` no-reply
2019-02-19 17:57 ` no-reply
16 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2019-02-19 17:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 15 Feb 2019 at 19:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
>
> Changes since v3:
>
> Rebased on master, and combined the JSConv and FHM patch sets.
> There were a number of patch conflicts which needed fixing up.
>
> Changes since v2:
>
> Patch 2 splits out vfp_helper.c, which I wrote for something else.
> But while rebasing it occured to me that helper_vjcvt is better placed
> in vfp_helper.c than op_helper.c, so why not include it here and now.
>
> Patch 3 corresponds to the v2 patch 1, but totally rewritten. What
> I missed the first time around is that register Sn is encoded differenly
> than Dn, so merely setting dp = 0 doesn't help because we've already
> decoded the register number incorrectly. Therefore, replace some really
> ugly if conditions and set some variables as appropriate.
>
> Patch 4 is adjusted to match the change in decode from patch 2, and
> putting the aa32 flags in the right place.
I've applied patches 1-4 to target-arm.next; patches 5, 6, 8 I've
commented on. 7 I'll leave until you've dealt with the fpstatus
stuff in your next version of the patchset.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (14 preceding siblings ...)
2019-02-19 17:46 ` Peter Maydell
@ 2019-02-19 17:53 ` no-reply
2019-02-19 17:57 ` no-reply
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 17:53 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
Switched to a new branch 'test'
0ff65a844d target/arm: Enable ARMv8.2-FHM for -cpu max
ad1df52ee0 target/arm: Implement VFMAL and VFMSL for aarch32
5f63a9cb31 target/arm: Implement FMLAL and FMLSL for aarch64
b188cbbcba target/arm: Add helpers for FMLAL
e6e668123e target/arm: Implement ARMv8.3-JSConv
0234b531fe target/arm: Rearrange Floating-point data-processing (2 regs)
04c91ee51e target/arm: Split out vfp_helper.c
037d4059a2 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit 037d4059a225 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 04c91ee51e3c (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 0234b531feac (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit e6e668123e72 (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit b188cbbcba44 (target/arm: Add helpers for FMLAL)
6/8 Checking commit 5f63a9cb31aa (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit ad1df52ee03e (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 0ff65a844d2c (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
` (15 preceding siblings ...)
2019-02-19 17:53 ` no-reply
@ 2019-02-19 17:57 ` no-reply
16 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-02-19 17:57 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, peter.maydell
Patchew URL: https://patchew.org/QEMU/20190215192302.27855-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190215192302.27855-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190215192302.27855-1-richard.henderson@linaro.org -> patchew/20190215192302.27855-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '3464681b2b5983df80086a40179d324102347da3'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
0ff65a8 target/arm: Enable ARMv8.2-FHM for -cpu max
ad1df52 target/arm: Implement VFMAL and VFMSL for aarch32
5f63a9c target/arm: Implement FMLAL and FMLSL for aarch64
b188cbb target/arm: Add helpers for FMLAL
e6e6681 target/arm: Implement ARMv8.3-JSConv
0234b53 target/arm: Rearrange Floating-point data-processing (2 regs)
04c91ee target/arm: Split out vfp_helper.c
037d405 target/arm: Restructure disas_fp_int_conv
=== OUTPUT BEGIN ===
1/8 Checking commit 037d4059a225 (target/arm: Restructure disas_fp_int_conv)
2/8 Checking commit 04c91ee51e3c (target/arm: Split out vfp_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#1102:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#1134: FILE: target/arm/vfp_helper.c:28:
+/* VFP support. We follow the convention used for VFP instructions:
WARNING: Block comments use * on subsequent lines
#1135: FILE: target/arm/vfp_helper.c:29:
+/* VFP support. We follow the convention used for VFP instructions:
+ Single precision routines have a "s" suffix, double precision a
WARNING: Block comments use a trailing */ on a separate line
#1136: FILE: target/arm/vfp_helper.c:30:
+ "d" suffix. */
ERROR: braces {} are necessary for all arms of this statement
#1143: FILE: target/arm/vfp_helper.c:37:
+ if (host_bits & float_flag_invalid)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1145: FILE: target/arm/vfp_helper.c:39:
+ if (host_bits & float_flag_divbyzero)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1147: FILE: target/arm/vfp_helper.c:41:
+ if (host_bits & float_flag_overflow)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1149: FILE: target/arm/vfp_helper.c:43:
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1151: FILE: target/arm/vfp_helper.c:45:
+ if (host_bits & float_flag_inexact)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1153: FILE: target/arm/vfp_helper.c:47:
+ if (host_bits & float_flag_input_denormal)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1189: FILE: target/arm/vfp_helper.c:83:
+ if (target_bits & 1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1191: FILE: target/arm/vfp_helper.c:85:
+ if (target_bits & 2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1193: FILE: target/arm/vfp_helper.c:87:
+ if (target_bits & 4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1195: FILE: target/arm/vfp_helper.c:89:
+ if (target_bits & 8)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1197: FILE: target/arm/vfp_helper.c:91:
+ if (target_bits & 0x10)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1199: FILE: target/arm/vfp_helper.c:93:
+ if (target_bits & 0x80)
[...]
WARNING: Block comments use a leading /* on a separate line
#1271: FILE: target/arm/vfp_helper.c:165:
+ /* The exception flags are ORed together when we read fpscr so we
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: space required after that ',' (ctx:VxV)
#1286: FILE: target/arm/vfp_helper.c:180:
+#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
^
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#1288: FILE: target/arm/vfp_helper.c:182:
+#define VFP_BINOP(name) \
+float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float32_ ## name(a, b, fpst); \
+} \
+float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float64_ ## name(a, b, fpst); \
+}
ERROR: space prohibited before that close parenthesis ')'
#1400: FILE: target/arm/vfp_helper.c:294:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#1403: FILE: target/arm/vfp_helper.c:297:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#1404: FILE: target/arm/vfp_helper.c:298:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#1405: FILE: target/arm/vfp_helper.c:299:
+FLOAT_CONVS(si, d, float64, 64, )
ERROR: space prohibited before that close parenthesis ')'
#1447: FILE: target/arm/vfp_helper.c:341:
+ get_float_rounding_mode(fpst), )
ERROR: space prohibited before that close parenthesis ')'
#1452: FILE: target/arm/vfp_helper.c:346:
+ get_float_rounding_mode(fpst), )
WARNING: Block comments use a leading /* on a separate line
#1552: FILE: target/arm/vfp_helper.c:446:
+/* Set the current fp rounding mode and return the old one.
WARNING: Block comments use a leading /* on a separate line
#1565: FILE: target/arm/vfp_helper.c:459:
+/* Set the current fp rounding mode in the standard fp status and return
WARNING: Block comments use a leading /* on a separate line
#1585: FILE: target/arm/vfp_helper.c:479:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1598: FILE: target/arm/vfp_helper.c:492:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1611: FILE: target/arm/vfp_helper.c:505:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1624: FILE: target/arm/vfp_helper.c:518:
+ /* Squash FZ16 to 0 for the duration of conversion. In this case,
WARNING: Block comments use a leading /* on a separate line
#1669: FILE: target/arm/vfp_helper.c:563:
+/* Constants 256 and 512 are used in some helpers; we avoid relying on
WARNING: Block comments use a trailing */ on a separate line
#1670: FILE: target/arm/vfp_helper.c:564:
+ * int->float conversions at run-time. */
WARNING: Block comments use a leading /* on a separate line
#1677: FILE: target/arm/vfp_helper.c:571:
+/* Reciprocal functions
WARNING: Block comments use a leading /* on a separate line
#1683: FILE: target/arm/vfp_helper.c:577:
+/* See RecipEstimate()
WARNING: Block comments use a leading /* on a separate line
#1903: FILE: target/arm/vfp_helper.c:797:
+/* The algorithm that must be used to calculate the estimate
WARNING: Block comments use a leading /* on a separate line
#1985: FILE: target/arm/vfp_helper.c:879:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#1986: FILE: target/arm/vfp_helper.c:880:
+ * preserving the parity of the exponent. */
WARNING: Block comments use a leading /* on a separate line
#2029: FILE: target/arm/vfp_helper.c:923:
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
WARNING: Block comments use a trailing */ on a separate line
#2030: FILE: target/arm/vfp_helper.c:924:
+ * preserving the parity of the exponent. */
total: 21 errors, 20 warnings, 2164 lines checked
Patch 2/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/8 Checking commit 0234b531feac (target/arm: Rearrange Floating-point data-processing (2 regs))
4/8 Checking commit e6e668123e72 (target/arm: Implement ARMv8.3-JSConv)
5/8 Checking commit b188cbbcba44 (target/arm: Add helpers for FMLAL)
6/8 Checking commit 5f63a9cb31aa (target/arm: Implement FMLAL and FMLSL for aarch64)
7/8 Checking commit ad1df52ee03e (target/arm: Implement VFMAL and VFMSL for aarch32)
8/8 Checking commit 0ff65a844d2c (target/arm: Enable ARMv8.2-FHM for -cpu max)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190215192302.27855-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-02-19 17:57 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-15 19:22 [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM Richard Henderson
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 1/8] target/arm: Restructure disas_fp_int_conv Richard Henderson
2019-02-19 15:28 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 2/8] target/arm: Split out vfp_helper.c Richard Henderson
2019-02-19 15:32 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 3/8] target/arm: Rearrange Floating-point data-processing (2 regs) Richard Henderson
2019-02-19 16:57 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 4/8] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-19 17:06 ` Peter Maydell
2019-02-15 19:22 ` [Qemu-devel] [PATCH v4 5/8] target/arm: Add helpers for FMLAL Richard Henderson
2019-02-19 17:31 ` Peter Maydell
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64 Richard Henderson
2019-02-19 17:43 ` Peter Maydell
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 7/8] target/arm: Implement VFMAL and VFMSL for aarch32 Richard Henderson
2019-02-15 19:23 ` [Qemu-devel] [PATCH v4 8/8] target/arm: Enable ARMv8.2-FHM for -cpu max Richard Henderson
2019-02-19 17:13 ` Peter Maydell
2019-02-15 19:54 ` [Qemu-devel] [PATCH v4 0/8] target/arm: Implement ARMv8.3-JSConv & ARMv8.2-FHM no-reply
2019-02-15 19:57 ` no-reply
2019-02-19 15:58 ` no-reply
2019-02-19 16:02 ` no-reply
2019-02-19 17:28 ` no-reply
2019-02-19 17:32 ` no-reply
2019-02-19 17:46 ` Peter Maydell
2019-02-19 17:53 ` no-reply
2019-02-19 17:57 ` no-reply
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