* [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-02-22 12:39 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-02-22 12:39 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Verify that our list of nonpriv registers exist and are writable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
1 file changed, 135 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..32b8c0bc8 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", GEN9, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +818,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-02-22 12:39 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-02-22 12:39 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Verify that our list of nonpriv registers exist and are writable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
1 file changed, 135 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..32b8c0bc8 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", GEN9, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +818,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-22 12:39 ` [igt-dev] " Chris Wilson
(?)
@ 2019-02-22 13:17 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-02-22 13:17 UTC (permalink / raw)
To: igt-dev
== Series Details ==
Series: i915/gem_ctx_isolation: Sanitycheck nonpriv access
URL : https://patchwork.freedesktop.org/series/57091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5654 -> IGTPW_2489
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57091/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_2489 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@memory-alloc:
- fi-ivb-3520m: NOTRUN -> SKIP [fdo#109271] +48
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182] +1
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_pm_rpm@module-reload:
- {fi-icl-y}: INCOMPLETE [fdo#108840] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (43 -> 39)
------------------------------
Additional (2): fi-ivb-3520m fi-skl-6700k2
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* IGT: IGT_4851 -> IGTPW_2489
CI_DRM_5654: 30c7f283790b433aa311ef7a7d2b6b428886fb9a @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2489: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2489/
IGT_4851: 2b7dd10a4e2ea0cabff68421fd15e96c99be3cad @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_ctx_isolation@bcs0-nonpriv
+igt@gem_ctx_isolation@rcs0-nonpriv
+igt@gem_ctx_isolation@vcs0-nonpriv
+igt@gem_ctx_isolation@vcs1-nonpriv
+igt@gem_ctx_isolation@vecs0-nonpriv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2489/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-22 12:39 ` [igt-dev] " Chris Wilson
(?)
(?)
@ 2019-02-22 23:10 ` Patchwork
2019-02-23 9:43 ` Chris Wilson
` (3 more replies)
-1 siblings, 4 replies; 19+ messages in thread
From: Patchwork @ 2019-02-22 23:10 UTC (permalink / raw)
To: igt-dev
== Series Details ==
Series: i915/gem_ctx_isolation: Sanitycheck nonpriv access
URL : https://patchwork.freedesktop.org/series/57091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5654_full -> IGTPW_2489_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_2489_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2489_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57091/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2489_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_isolation@rcs0-dirty-switch:
- shard-glk: PASS -> FAIL +1
* igt@gem_ctx_isolation@rcs0-reset:
- shard-apl: PASS -> FAIL
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: PASS -> FAIL
- shard-apl: NOTRUN -> FAIL
New tests
---------
New tests have been introduced between CI_DRM_5654_full and IGTPW_2489_full:
### New IGT tests (5) ###
* igt@gem_ctx_isolation@bcs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_ctx_isolation@rcs0-nonpriv:
- Statuses : 3 pass(s) 1 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_ctx_isolation@vcs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_ctx_isolation@vcs1-nonpriv:
- Statuses : 1 pass(s) 4 skip(s)
- Exec time: [0.0, 0.05] s
* igt@gem_ctx_isolation@vecs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
Known issues
------------
Here are the changes found in IGTPW_2489_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-dirty-switch:
- shard-apl: PASS -> FAIL [fdo#109472]
- shard-kbl: PASS -> FAIL [fdo#109472]
* {igt@gem_ctx_isolation@vecs0-nonpriv} (NEW):
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +4
* igt@gem_ctx_param@invalid-param-get:
- shard-kbl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_userptr_blits@process-exit-gtt:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +25
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-e:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] +1
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-64x21-onscreen:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: PASS -> FAIL [fdo#109350]
- shard-glk: PASS -> FAIL [fdo#109350]
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
- shard-snb: PASS -> SKIP [fdo#109271]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-kbl: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-kbl: PASS -> FAIL [fdo#103167] +1
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +71
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167] +7
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +51
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +23
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +7
- shard-apl: PASS -> FAIL [fdo#103166] +5
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-kbl: PASS -> FAIL [fdo#103166] +3
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-apl: PASS -> FAIL [fdo#105010]
- shard-glk: NOTRUN -> FAIL [fdo#105010]
- shard-kbl: PASS -> FAIL [fdo#105010]
#### Possible fixes ####
* igt@kms_color@pipe-a-degamma:
- shard-kbl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_color@pipe-a-gamma:
- shard-kbl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-kbl: FAIL [fdo#103232] -> PASS +1
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS +1
- shard-kbl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +3
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_vblank@pipe-b-query-idle-hang:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS +1
* igt@testdisplay:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108739]: https://bugs.freedesktop.org/show_bug.cgi?id=108739
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109472]: https://bugs.freedesktop.org/show_bug.cgi?id=109472
[fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* IGT: IGT_4851 -> IGTPW_2489
* Piglit: piglit_4509 -> None
CI_DRM_5654: 30c7f283790b433aa311ef7a7d2b6b428886fb9a @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2489: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2489/
IGT_4851: 2b7dd10a4e2ea0cabff68421fd15e96c99be3cad @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2489/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-22 23:10 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-02-23 9:43 ` Chris Wilson
2019-02-23 9:45 ` [igt-dev] " Chris Wilson
` (2 subsequent siblings)
3 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-02-23 9:43 UTC (permalink / raw)
To: Patchwork, igt-dev
Quoting Patchwork (2019-02-22 23:10:31)
> == Series Details ==
>
> Series: i915/gem_ctx_isolation: Sanitycheck nonpriv access
> URL : https://patchwork.freedesktop.org/series/57091/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5654_full -> IGTPW_2489_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with IGTPW_2489_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_2489_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://patchwork.freedesktop.org/api/1.0/series/57091/revisions/1/mbox/
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in IGTPW_2489_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_ctx_isolation@rcs0-dirty-switch:
> - shard-glk: PASS -> FAIL +1
>
> * igt@gem_ctx_isolation@rcs0-reset:
> - shard-apl: PASS -> FAIL
>
> * igt@gem_ctx_isolation@rcs0-s3:
> - shard-kbl: PASS -> FAIL
> - shard-apl: NOTRUN -> FAIL
So L3SQCREG4 is also not context saved but whitelisted. So anybody is
free to severely hinder performance of the rest of the system.
Sigh. I must push gem_ctx_isolation into a selftest so that we check the
whitelist before being merged.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-22 23:10 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-02-23 9:45 ` Chris Wilson
2019-02-23 9:45 ` [igt-dev] " Chris Wilson
` (2 subsequent siblings)
3 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-02-23 9:45 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Verify that our list of nonpriv registers exist and are writable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
1 file changed, 135 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..991a997ff 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +818,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-02-23 9:45 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-02-23 9:45 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Verify that our list of nonpriv registers exist and are writable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
1 file changed, 135 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..991a997ff 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +818,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2)
2019-02-22 23:10 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2019-02-23 9:43 ` Chris Wilson
2019-02-23 9:45 ` [igt-dev] " Chris Wilson
@ 2019-02-23 10:19 ` Patchwork
2019-02-23 12:31 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-02-23 10:19 UTC (permalink / raw)
To: igt-dev
== Series Details ==
Series: i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2)
URL : https://patchwork.freedesktop.org/series/57091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5656 -> IGTPW_2500
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57091/revisions/2/mbox/
Known issues
------------
Here are the changes found in IGTPW_2500 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614]
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (40 -> 39)
------------------------------
Additional (3): fi-icl-y fi-hsw-peppy fi-skl-6700k2
Missing (4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* IGT: IGT_4853 -> IGTPW_2500
CI_DRM_5656: 002eb37fb0113b1b5e017c842890e1c3601b8631 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2500: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2500/
IGT_4853: 8afdfd8fa9ce17043d9105dedca46ad4555fdcdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_ctx_isolation@bcs0-nonpriv
+igt@gem_ctx_isolation@rcs0-nonpriv
+igt@gem_ctx_isolation@vcs0-nonpriv
+igt@gem_ctx_isolation@vcs1-nonpriv
+igt@gem_ctx_isolation@vecs0-nonpriv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2500/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2)
2019-02-22 23:10 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
` (2 preceding siblings ...)
2019-02-23 10:19 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2) Patchwork
@ 2019-02-23 12:31 ` Patchwork
3 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-02-23 12:31 UTC (permalink / raw)
To: igt-dev
== Series Details ==
Series: i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2)
URL : https://patchwork.freedesktop.org/series/57091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5656_full -> IGTPW_2500_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57091/revisions/2/mbox/
New tests
---------
New tests have been introduced between CI_DRM_5656_full and IGTPW_2500_full:
### New IGT tests (5) ###
* igt@gem_ctx_isolation@bcs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_ctx_isolation@rcs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.15] s
* igt@gem_ctx_isolation@vcs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_ctx_isolation@vcs1-nonpriv:
- Statuses : 1 pass(s) 4 skip(s)
- Exec time: [0.0, 0.04] s
* igt@gem_ctx_isolation@vecs0-nonpriv:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.14] s
Known issues
------------
Here are the changes found in IGTPW_2500_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* {igt@gem_ctx_isolation@vcs1-nonpriv} (NEW):
- shard-glk: NOTRUN -> SKIP [fdo#109271] +11
* {igt@gem_ctx_isolation@vecs0-nonpriv} (NEW):
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +4
* igt@gem_exec_suspend@basic-s3:
- shard-snb: NOTRUN -> INCOMPLETE [fdo#105411]
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-modeset-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-modeset-hang-newfb-render-e:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-glk: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] +1
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-kbl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: NOTRUN -> FAIL [fdo#105454] / [fdo#106509]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> FAIL [fdo#103167]
- shard-kbl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +30
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +7
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +212
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- shard-snb: PASS -> SKIP [fdo#109271] +1
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +20
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-glk: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +5
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@perf_pmu@most-busy-idle-check-all-vcs1:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +35
#### Possible fixes ####
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
- shard-kbl: FAIL [fdo#107725] / [fdo#108145] -> PASS
* igt@kms_color@pipe-c-legacy-gamma:
- shard-glk: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-kbl: FAIL [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-glk: FAIL [fdo#109350] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-kbl: FAIL [fdo#103167] -> PASS +1
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-kbl: FAIL [fdo#103166] -> PASS
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-hsw: FAIL [fdo#104894] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-modeset-hang:
- shard-apl: FAIL [fdo#104894] -> PASS
* igt@perf_pmu@rc6:
- shard-kbl: SKIP [fdo#109271] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108739]: https://bugs.freedesktop.org/show_bug.cgi?id=108739
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* IGT: IGT_4853 -> IGTPW_2500
* Piglit: piglit_4509 -> None
CI_DRM_5656: 002eb37fb0113b1b5e017c842890e1c3601b8631 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2500: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2500/
IGT_4853: 8afdfd8fa9ce17043d9105dedca46ad4555fdcdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2500/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-23 9:45 ` [igt-dev] " Chris Wilson
@ 2019-03-01 0:36 ` Dale B Stimson
-1 siblings, 0 replies; 19+ messages in thread
From: Dale B Stimson @ 2019-03-01 0:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On Sat, Feb 23, 2019 at 09:45:10AM +0000, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
> 1 file changed, 135 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 839d49ad..991a997f 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -59,16 +59,23 @@ enum {
>
> static const struct named_register {
> const char *name;
> - unsigned int gen_mask;
> - unsigned int engine_mask;
> - uint32_t offset;
> + unsigned int gen_mask; /* on which gen the register exists */
> + unsigned int engine_mask; /* preferred engine / powerwell */
> + uint32_t offset; /* address of register, from bottom of mmio bar */
> uint32_t count;
> uint32_t ignore_bits;
> + uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> + {
> + "INSTPM",
> + GEN6, RCS0, 0x20c0,
> + .ignore_bits = BIT(8) /* ro counter */,
> + .write_mask = BIT(8) /* rsvd varies between gen */,
> + .masked = true,
> + },
> { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> @@ -78,7 +85,7 @@ static const struct named_register {
> { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
I can't find a reason for adding ".write_mask = ~0x3".
Among other places, I've looked in:
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part2_0.pdf
> { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
> { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> @@ -86,7 +93,7 @@ static const struct named_register {
> { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
> { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> @@ -94,45 +101,45 @@ static const struct named_register {
> { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
Same comment as for "PS_INVOCATION_COUNT_0" above.
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
Same comment as for "PS_INVOCATION_COUNT_0" above.
> { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> - { "GT_MODE", GEN8, RCS0, 0x7008 },
> - { "L3_Config", GEN7, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> + { "L3_Config", GEN8, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
It looks to me like TD_CTL should not be ".masked = true", as docs state
"reserved" and "31:16 MBZ".
> { "TD_CTL2", GEN8, RCS0, 0xe404 },
> - { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> - { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> - { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> - { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
> { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
> { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
> - { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
> - { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
> - { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
> - { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
> + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
> { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
> - { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
> - { "L3SQREG1", GEN8, RCS0, 0xb010 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> + { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
>
> { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> - { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
> + { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> @@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
> return false;
> }
>
> +static void tmpl_regs(int fd,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t handle,
> + uint32_t value)
> +{
> + const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> + const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + unsigned int regs_size;
> + uint32_t *regs;
> +
> + regs_size = NUM_REGS * sizeof(uint32_t);
> + regs_size = PAGE_ALIGN(regs_size);
> +
> + regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
> + gem_set_domain(fd, handle,
> + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> +
> + for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + if (!(r->engine_mask & engine_bit))
> + continue;
> + if (!(r->gen_mask & gen_bit))
> + continue;
> + for (unsigned count = r->count ?: 1, offset = r->offset;
> + count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x &= 0xffff;
> + regs[offset/sizeof(*regs)] = x;
> + }
> + }
> + munmap(regs, regs_size);
> +}
> +
> static uint32_t read_regs(int fd,
> uint32_t ctx,
> const struct intel_execution_engine2 *e,
> @@ -294,12 +337,15 @@ static void write_regs(int fd,
> continue;
> for (unsigned count = r->count ?: 1, offset = r->offset;
> count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x |= 0xffffu << 16;
> +
> *b++ = 0x22 << 23 | 1; /* LRI */
> *b++ = offset;
> - if (r->masked)
> - *b++ = value | 0xffffu << 16;
> - else
> - *b++ = value;
> + *b++ = x;
> }
> }
> *b++ = MI_BATCH_BUFFER_END;
> @@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> num_errors, who);
> }
>
> +static void nonpriv(int fd,
> + const struct intel_execution_engine2 *e,
> + unsigned int flags)
> +{
> + static const uint32_t values[] = {
> + 0x0,
> + 0xffffffff,
> + 0xcccccccc,
> + 0x33333333,
> + 0x55555555,
> + 0xaaaaaaaa,
> + 0xdeadbeef
> + };
> + unsigned int engine =
> + gem_class_instance_to_eb_flags(fd, e->class, e->instance);
> + unsigned int num_values = ARRAY_SIZE(values);
> +
> + /* Sigh -- we need cmdparser access to our own registers! */
> + igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> +
> + gem_quiescent_gpu(fd);
> +
> + for (int v = 0; v < num_values; v++) {
> + igt_spin_t *spin = NULL;
> + uint32_t ctx, regs[2], tmpl;
> +
> + ctx = gem_context_create(fd);
> + tmpl = read_regs(fd, ctx, e, flags);
> + regs[0] = read_regs(fd, ctx, e, flags);
> +
> + tmpl_regs(fd, ctx, e, tmpl, values[v]);
> +
> + spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
> +
> + igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
> + __func__, v, values[v]);
> + write_regs(fd, ctx, e, flags, values[v]);
> +
> + regs[1] = read_regs(fd, ctx, e, flags);
> +
> + /*
> + * Restore the original register values before the HW idles.
> + * Or else it may never restart!
> + */
> + restore_regs(fd, ctx, e, flags, regs[0]);
> +
> + igt_spin_batch_free(fd, spin);
> +
> + compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> +
> + for (int n = 0; n < ARRAY_SIZE(regs); n++)
> + gem_close(fd, regs[n]);
> + gem_context_destroy(fd, ctx);
> + gem_close(fd, tmpl);
> + }
> +}
> +
> static void isolation(int fd,
> const struct intel_execution_engine2 *e,
> unsigned int flags)
> @@ -715,6 +818,9 @@ igt_main
> igt_fork_hang_detector(fd);
> }
>
> + igt_subtest_f("%s-nonpriv", e->name)
> + nonpriv(fd, e, 0);
> +
> igt_subtest_f("%s-clean", e->name)
> isolation(fd, e, 0);
> igt_subtest_f("%s-dirty-create", e->name)
> --
> 2.21.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-03-01 0:36 ` Dale B Stimson
0 siblings, 0 replies; 19+ messages in thread
From: Dale B Stimson @ 2019-03-01 0:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx, Tvrtko Ursulin
On Sat, Feb 23, 2019 at 09:45:10AM +0000, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
> 1 file changed, 135 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 839d49ad..991a997f 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -59,16 +59,23 @@ enum {
>
> static const struct named_register {
> const char *name;
> - unsigned int gen_mask;
> - unsigned int engine_mask;
> - uint32_t offset;
> + unsigned int gen_mask; /* on which gen the register exists */
> + unsigned int engine_mask; /* preferred engine / powerwell */
> + uint32_t offset; /* address of register, from bottom of mmio bar */
> uint32_t count;
> uint32_t ignore_bits;
> + uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> + {
> + "INSTPM",
> + GEN6, RCS0, 0x20c0,
> + .ignore_bits = BIT(8) /* ro counter */,
> + .write_mask = BIT(8) /* rsvd varies between gen */,
> + .masked = true,
> + },
> { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> @@ -78,7 +85,7 @@ static const struct named_register {
> { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
I can't find a reason for adding ".write_mask = ~0x3".
Among other places, I've looked in:
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part2_0.pdf
> { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
> { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> @@ -86,7 +93,7 @@ static const struct named_register {
> { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
> { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> @@ -94,45 +101,45 @@ static const struct named_register {
> { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
Same comment as for "PS_INVOCATION_COUNT_0" above.
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
Same comment as for "PS_INVOCATION_COUNT_0" above.
> { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> - { "GT_MODE", GEN8, RCS0, 0x7008 },
> - { "L3_Config", GEN7, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> + { "L3_Config", GEN8, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
It looks to me like TD_CTL should not be ".masked = true", as docs state
"reserved" and "31:16 MBZ".
> { "TD_CTL2", GEN8, RCS0, 0xe404 },
> - { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> - { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> - { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> - { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
> { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
> { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
> - { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
> - { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
> - { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
> - { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
> + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
> { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
> - { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
> - { "L3SQREG1", GEN8, RCS0, 0xb010 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> + { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
>
> { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> - { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
> + { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> @@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
> return false;
> }
>
> +static void tmpl_regs(int fd,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t handle,
> + uint32_t value)
> +{
> + const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> + const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + unsigned int regs_size;
> + uint32_t *regs;
> +
> + regs_size = NUM_REGS * sizeof(uint32_t);
> + regs_size = PAGE_ALIGN(regs_size);
> +
> + regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
> + gem_set_domain(fd, handle,
> + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> +
> + for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + if (!(r->engine_mask & engine_bit))
> + continue;
> + if (!(r->gen_mask & gen_bit))
> + continue;
> + for (unsigned count = r->count ?: 1, offset = r->offset;
> + count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x &= 0xffff;
> + regs[offset/sizeof(*regs)] = x;
> + }
> + }
> + munmap(regs, regs_size);
> +}
> +
> static uint32_t read_regs(int fd,
> uint32_t ctx,
> const struct intel_execution_engine2 *e,
> @@ -294,12 +337,15 @@ static void write_regs(int fd,
> continue;
> for (unsigned count = r->count ?: 1, offset = r->offset;
> count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x |= 0xffffu << 16;
> +
> *b++ = 0x22 << 23 | 1; /* LRI */
> *b++ = offset;
> - if (r->masked)
> - *b++ = value | 0xffffu << 16;
> - else
> - *b++ = value;
> + *b++ = x;
> }
> }
> *b++ = MI_BATCH_BUFFER_END;
> @@ -474,6 +520,63 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> num_errors, who);
> }
>
> +static void nonpriv(int fd,
> + const struct intel_execution_engine2 *e,
> + unsigned int flags)
> +{
> + static const uint32_t values[] = {
> + 0x0,
> + 0xffffffff,
> + 0xcccccccc,
> + 0x33333333,
> + 0x55555555,
> + 0xaaaaaaaa,
> + 0xdeadbeef
> + };
> + unsigned int engine =
> + gem_class_instance_to_eb_flags(fd, e->class, e->instance);
> + unsigned int num_values = ARRAY_SIZE(values);
> +
> + /* Sigh -- we need cmdparser access to our own registers! */
> + igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> +
> + gem_quiescent_gpu(fd);
> +
> + for (int v = 0; v < num_values; v++) {
> + igt_spin_t *spin = NULL;
> + uint32_t ctx, regs[2], tmpl;
> +
> + ctx = gem_context_create(fd);
> + tmpl = read_regs(fd, ctx, e, flags);
> + regs[0] = read_regs(fd, ctx, e, flags);
> +
> + tmpl_regs(fd, ctx, e, tmpl, values[v]);
> +
> + spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
> +
> + igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
> + __func__, v, values[v]);
> + write_regs(fd, ctx, e, flags, values[v]);
> +
> + regs[1] = read_regs(fd, ctx, e, flags);
> +
> + /*
> + * Restore the original register values before the HW idles.
> + * Or else it may never restart!
> + */
> + restore_regs(fd, ctx, e, flags, regs[0]);
> +
> + igt_spin_batch_free(fd, spin);
> +
> + compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> +
> + for (int n = 0; n < ARRAY_SIZE(regs); n++)
> + gem_close(fd, regs[n]);
> + gem_context_destroy(fd, ctx);
> + gem_close(fd, tmpl);
> + }
> +}
> +
> static void isolation(int fd,
> const struct intel_execution_engine2 *e,
> unsigned int flags)
> @@ -715,6 +818,9 @@ igt_main
> igt_fork_hang_detector(fd);
> }
>
> + igt_subtest_f("%s-nonpriv", e->name)
> + nonpriv(fd, e, 0);
> +
> igt_subtest_f("%s-clean", e->name)
> isolation(fd, e, 0);
> igt_subtest_f("%s-dirty-create", e->name)
> --
> 2.21.0
>
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-03-01 0:36 ` [igt-dev] " Dale B Stimson
@ 2019-03-01 7:59 ` Chris Wilson
-1 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-01 7:59 UTC (permalink / raw)
To: Dale B Stimson; +Cc: igt-dev, intel-gfx
Quoting Dale B Stimson (2019-03-01 00:36:10)
> On Sat, Feb 23, 2019 at 09:45:10AM +0000, Chris Wilson wrote:
> > Verify that our list of nonpriv registers exist and are writable.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Dale B Stimson <dale.b.stimson@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
> > 1 file changed, 135 insertions(+), 29 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 839d49ad..991a997f 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -59,16 +59,23 @@ enum {
> >
> > static const struct named_register {
> > const char *name;
> > - unsigned int gen_mask;
> > - unsigned int engine_mask;
> > - uint32_t offset;
> > + unsigned int gen_mask; /* on which gen the register exists */
> > + unsigned int engine_mask; /* preferred engine / powerwell */
> > + uint32_t offset; /* address of register, from bottom of mmio bar */
> > uint32_t count;
> > uint32_t ignore_bits;
> > + uint32_t write_mask; /* some registers bits do not exist */
> > bool masked;
> > } nonpriv_registers[] = {
> > { "NOPID", NOCTX, RCS0, 0x2094 },
> > { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> > - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> > + {
> > + "INSTPM",
> > + GEN6, RCS0, 0x20c0,
> > + .ignore_bits = BIT(8) /* ro counter */,
> > + .write_mask = BIT(8) /* rsvd varies between gen */,
> > + .masked = true,
> > + },
> > { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> > { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> > { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> > @@ -78,7 +85,7 @@ static const struct named_register {
> > { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> > { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> > { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> > - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> > + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
>
> I can't find a reason for adding ".write_mask = ~0x3".
Observed behaviour on byt.
> > { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> > - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> > - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> > - { "GT_MODE", GEN8, RCS0, 0x7008 },
> > - { "L3_Config", GEN7, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400 },
> > + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > + { "L3_Config", GEN8, RCS0, 0x7034 },
> > + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
>
> It looks to me like TD_CTL should not be ".masked = true", as docs state
> "reserved" and "31:16 MBZ".
Ah, side-effect of not using asymmetric 31-16, 15-0.
Looks like it should be .write_mask=0xffff instead.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-03-01 7:59 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-01 7:59 UTC (permalink / raw)
To: Dale B Stimson; +Cc: igt-dev, intel-gfx, Tvrtko Ursulin
Quoting Dale B Stimson (2019-03-01 00:36:10)
> On Sat, Feb 23, 2019 at 09:45:10AM +0000, Chris Wilson wrote:
> > Verify that our list of nonpriv registers exist and are writable.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Dale B Stimson <dale.b.stimson@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
> > 1 file changed, 135 insertions(+), 29 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 839d49ad..991a997f 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -59,16 +59,23 @@ enum {
> >
> > static const struct named_register {
> > const char *name;
> > - unsigned int gen_mask;
> > - unsigned int engine_mask;
> > - uint32_t offset;
> > + unsigned int gen_mask; /* on which gen the register exists */
> > + unsigned int engine_mask; /* preferred engine / powerwell */
> > + uint32_t offset; /* address of register, from bottom of mmio bar */
> > uint32_t count;
> > uint32_t ignore_bits;
> > + uint32_t write_mask; /* some registers bits do not exist */
> > bool masked;
> > } nonpriv_registers[] = {
> > { "NOPID", NOCTX, RCS0, 0x2094 },
> > { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> > - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> > + {
> > + "INSTPM",
> > + GEN6, RCS0, 0x20c0,
> > + .ignore_bits = BIT(8) /* ro counter */,
> > + .write_mask = BIT(8) /* rsvd varies between gen */,
> > + .masked = true,
> > + },
> > { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> > { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> > { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> > @@ -78,7 +85,7 @@ static const struct named_register {
> > { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> > { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> > { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> > - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> > + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
>
> I can't find a reason for adding ".write_mask = ~0x3".
Observed behaviour on byt.
> > { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> > - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> > - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> > - { "GT_MODE", GEN8, RCS0, 0x7008 },
> > - { "L3_Config", GEN7, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400 },
> > + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > + { "L3_Config", GEN8, RCS0, 0x7034 },
> > + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
>
> It looks to me like TD_CTL should not be ".masked = true", as docs state
> "reserved" and "31:16 MBZ".
Ah, side-effect of not using asymmetric 31-16, 15-0.
Looks like it should be .write_mask=0xffff instead.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-02-22 12:39 ` [igt-dev] " Chris Wilson
@ 2019-03-01 8:19 ` Chris Wilson
-1 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-01 8:19 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Verify that our list of nonpriv registers exist and are writable.
v2: TD_CTL has a write_mask of 0xffff instead of being a masked
register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 167 +++++++++++++++++++++++++++------
1 file changed, 138 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..e50cc9a72 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,66 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xf0f00f0f,
+ 0xa0a00303,
+ 0x0505c0c0,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- hsw: we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +821,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-03-01 8:19 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-01 8:19 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Verify that our list of nonpriv registers exist and are writable.
v2: TD_CTL has a write_mask of 0xffff instead of being a masked
register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/i915/gem_ctx_isolation.c | 167 +++++++++++++++++++++++++++------
1 file changed, 138 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..e50cc9a72 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
@@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x &= 0xffff;
+ regs[offset/sizeof(*regs)] = x;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -294,12 +337,15 @@ static void write_regs(int fd,
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
+ uint32_t x = value;
+ if (r->write_mask)
+ x &= r->write_mask;
+ if (r->masked)
+ x |= 0xffffu << 16;
+
*b++ = 0x22 << 23 | 1; /* LRI */
*b++ = offset;
- if (r->masked)
- *b++ = value | 0xffffu << 16;
- else
- *b++ = value;
+ *b++ = x;
}
}
*b++ = MI_BATCH_BUFFER_END;
@@ -474,6 +520,66 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xf0f00f0f,
+ 0xa0a00303,
+ 0x0505c0c0,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ /* Sigh -- hsw: we need cmdparser access to our own registers! */
+ igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +821,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-03-01 8:19 ` [igt-dev] " Chris Wilson
@ 2019-03-02 0:53 ` Dale B Stimson
-1 siblings, 0 replies; 19+ messages in thread
From: Dale B Stimson @ 2019-03-02 0:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
Reviewed-By: Dale B Stimson <dale.b.stimson@intel.com>
On Fri, Mar 01, 2019 at 08:19:19AM +0000, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> v2: TD_CTL has a write_mask of 0xffff instead of being a masked
> register.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 167 +++++++++++++++++++++++++++------
> 1 file changed, 138 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 839d49ade..e50cc9a72 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -59,16 +59,23 @@ enum {
>
> static const struct named_register {
> const char *name;
> - unsigned int gen_mask;
> - unsigned int engine_mask;
> - uint32_t offset;
> + unsigned int gen_mask; /* on which gen the register exists */
> + unsigned int engine_mask; /* preferred engine / powerwell */
> + uint32_t offset; /* address of register, from bottom of mmio bar */
> uint32_t count;
> uint32_t ignore_bits;
> + uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> + {
> + "INSTPM",
> + GEN6, RCS0, 0x20c0,
> + .ignore_bits = BIT(8) /* ro counter */,
> + .write_mask = BIT(8) /* rsvd varies between gen */,
> + .masked = true,
> + },
> { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> @@ -78,7 +85,7 @@ static const struct named_register {
> { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
> { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> @@ -86,7 +93,7 @@ static const struct named_register {
> { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
> { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> @@ -94,45 +101,45 @@ static const struct named_register {
> { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> - { "GT_MODE", GEN8, RCS0, 0x7008 },
> - { "L3_Config", GEN7, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> + { "L3_Config", GEN8, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
> { "TD_CTL2", GEN8, RCS0, 0xe404 },
> - { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> - { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> - { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> - { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
> { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
> { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
> - { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
> - { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
> - { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
> - { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
> + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
> { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
> - { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
> - { "L3SQREG1", GEN8, RCS0, 0xb010 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> + { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
>
> { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> - { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
> + { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> @@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
> return false;
> }
>
> +static void tmpl_regs(int fd,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t handle,
> + uint32_t value)
> +{
> + const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> + const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + unsigned int regs_size;
> + uint32_t *regs;
> +
> + regs_size = NUM_REGS * sizeof(uint32_t);
> + regs_size = PAGE_ALIGN(regs_size);
> +
> + regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
> + gem_set_domain(fd, handle,
> + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> +
> + for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + if (!(r->engine_mask & engine_bit))
> + continue;
> + if (!(r->gen_mask & gen_bit))
> + continue;
> + for (unsigned count = r->count ?: 1, offset = r->offset;
> + count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x &= 0xffff;
> + regs[offset/sizeof(*regs)] = x;
> + }
> + }
> + munmap(regs, regs_size);
> +}
> +
> static uint32_t read_regs(int fd,
> uint32_t ctx,
> const struct intel_execution_engine2 *e,
> @@ -294,12 +337,15 @@ static void write_regs(int fd,
> continue;
> for (unsigned count = r->count ?: 1, offset = r->offset;
> count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x |= 0xffffu << 16;
> +
> *b++ = 0x22 << 23 | 1; /* LRI */
> *b++ = offset;
> - if (r->masked)
> - *b++ = value | 0xffffu << 16;
> - else
> - *b++ = value;
> + *b++ = x;
> }
> }
> *b++ = MI_BATCH_BUFFER_END;
> @@ -474,6 +520,66 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> num_errors, who);
> }
>
> +static void nonpriv(int fd,
> + const struct intel_execution_engine2 *e,
> + unsigned int flags)
> +{
> + static const uint32_t values[] = {
> + 0x0,
> + 0xffffffff,
> + 0xcccccccc,
> + 0x33333333,
> + 0x55555555,
> + 0xaaaaaaaa,
> + 0xf0f00f0f,
> + 0xa0a00303,
> + 0x0505c0c0,
> + 0xdeadbeef
> + };
> + unsigned int engine =
> + gem_class_instance_to_eb_flags(fd, e->class, e->instance);
> + unsigned int num_values = ARRAY_SIZE(values);
> +
> + /* Sigh -- hsw: we need cmdparser access to our own registers! */
> + igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> +
> + gem_quiescent_gpu(fd);
> +
> + for (int v = 0; v < num_values; v++) {
> + igt_spin_t *spin = NULL;
> + uint32_t ctx, regs[2], tmpl;
> +
> + ctx = gem_context_create(fd);
> + tmpl = read_regs(fd, ctx, e, flags);
> + regs[0] = read_regs(fd, ctx, e, flags);
> +
> + tmpl_regs(fd, ctx, e, tmpl, values[v]);
> +
> + spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
> +
> + igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
> + __func__, v, values[v]);
> + write_regs(fd, ctx, e, flags, values[v]);
> +
> + regs[1] = read_regs(fd, ctx, e, flags);
> +
> + /*
> + * Restore the original register values before the HW idles.
> + * Or else it may never restart!
> + */
> + restore_regs(fd, ctx, e, flags, regs[0]);
> +
> + igt_spin_batch_free(fd, spin);
> +
> + compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> +
> + for (int n = 0; n < ARRAY_SIZE(regs); n++)
> + gem_close(fd, regs[n]);
> + gem_context_destroy(fd, ctx);
> + gem_close(fd, tmpl);
> + }
> +}
> +
> static void isolation(int fd,
> const struct intel_execution_engine2 *e,
> unsigned int flags)
> @@ -715,6 +821,9 @@ igt_main
> igt_fork_hang_detector(fd);
> }
>
> + igt_subtest_f("%s-nonpriv", e->name)
> + nonpriv(fd, e, 0);
> +
> igt_subtest_f("%s-clean", e->name)
> isolation(fd, e, 0);
> igt_subtest_f("%s-dirty-create", e->name)
> --
> 2.20.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-03-02 0:53 ` Dale B Stimson
0 siblings, 0 replies; 19+ messages in thread
From: Dale B Stimson @ 2019-03-02 0:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx, Tvrtko Ursulin
Reviewed-By: Dale B Stimson <dale.b.stimson@intel.com>
On Fri, Mar 01, 2019 at 08:19:19AM +0000, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> v2: TD_CTL has a write_mask of 0xffff instead of being a masked
> register.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 167 +++++++++++++++++++++++++++------
> 1 file changed, 138 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 839d49ade..e50cc9a72 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -59,16 +59,23 @@ enum {
>
> static const struct named_register {
> const char *name;
> - unsigned int gen_mask;
> - unsigned int engine_mask;
> - uint32_t offset;
> + unsigned int gen_mask; /* on which gen the register exists */
> + unsigned int engine_mask; /* preferred engine / powerwell */
> + uint32_t offset; /* address of register, from bottom of mmio bar */
> uint32_t count;
> uint32_t ignore_bits;
> + uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> + {
> + "INSTPM",
> + GEN6, RCS0, 0x20c0,
> + .ignore_bits = BIT(8) /* ro counter */,
> + .write_mask = BIT(8) /* rsvd varies between gen */,
> + .masked = true,
> + },
> { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> @@ -78,7 +85,7 @@ static const struct named_register {
> { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
> { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> @@ -86,7 +93,7 @@ static const struct named_register {
> { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
> { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> @@ -94,45 +101,45 @@ static const struct named_register {
> { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> - { "GT_MODE", GEN8, RCS0, 0x7008 },
> - { "L3_Config", GEN7, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> + { "L3_Config", GEN8, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
> { "TD_CTL2", GEN8, RCS0, 0xe404 },
> - { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> - { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> - { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> - { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
> { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
> { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
> - { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
> - { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
> - { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
> - { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
> + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .write_mask = ~0x3 },
> + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .write_mask = ~0x3 },
> { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
> - { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
> - { "L3SQREG1", GEN8, RCS0, 0xb010 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> + { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
>
> { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> - { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
> + { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> @@ -191,6 +198,42 @@ static bool ignore_register(uint32_t offset)
> return false;
> }
>
> +static void tmpl_regs(int fd,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t handle,
> + uint32_t value)
> +{
> + const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> + const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + unsigned int regs_size;
> + uint32_t *regs;
> +
> + regs_size = NUM_REGS * sizeof(uint32_t);
> + regs_size = PAGE_ALIGN(regs_size);
> +
> + regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
> + gem_set_domain(fd, handle,
> + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> +
> + for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + if (!(r->engine_mask & engine_bit))
> + continue;
> + if (!(r->gen_mask & gen_bit))
> + continue;
> + for (unsigned count = r->count ?: 1, offset = r->offset;
> + count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x &= 0xffff;
> + regs[offset/sizeof(*regs)] = x;
> + }
> + }
> + munmap(regs, regs_size);
> +}
> +
> static uint32_t read_regs(int fd,
> uint32_t ctx,
> const struct intel_execution_engine2 *e,
> @@ -294,12 +337,15 @@ static void write_regs(int fd,
> continue;
> for (unsigned count = r->count ?: 1, offset = r->offset;
> count--; offset += 4) {
> + uint32_t x = value;
> + if (r->write_mask)
> + x &= r->write_mask;
> + if (r->masked)
> + x |= 0xffffu << 16;
> +
> *b++ = 0x22 << 23 | 1; /* LRI */
> *b++ = offset;
> - if (r->masked)
> - *b++ = value | 0xffffu << 16;
> - else
> - *b++ = value;
> + *b++ = x;
> }
> }
> *b++ = MI_BATCH_BUFFER_END;
> @@ -474,6 +520,66 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> num_errors, who);
> }
>
> +static void nonpriv(int fd,
> + const struct intel_execution_engine2 *e,
> + unsigned int flags)
> +{
> + static const uint32_t values[] = {
> + 0x0,
> + 0xffffffff,
> + 0xcccccccc,
> + 0x33333333,
> + 0x55555555,
> + 0xaaaaaaaa,
> + 0xf0f00f0f,
> + 0xa0a00303,
> + 0x0505c0c0,
> + 0xdeadbeef
> + };
> + unsigned int engine =
> + gem_class_instance_to_eb_flags(fd, e->class, e->instance);
> + unsigned int num_values = ARRAY_SIZE(values);
> +
> + /* Sigh -- hsw: we need cmdparser access to our own registers! */
> + igt_skip_on(intel_gen(intel_get_drm_devid(fd)) < 8);
> +
> + gem_quiescent_gpu(fd);
> +
> + for (int v = 0; v < num_values; v++) {
> + igt_spin_t *spin = NULL;
> + uint32_t ctx, regs[2], tmpl;
> +
> + ctx = gem_context_create(fd);
> + tmpl = read_regs(fd, ctx, e, flags);
> + regs[0] = read_regs(fd, ctx, e, flags);
> +
> + tmpl_regs(fd, ctx, e, tmpl, values[v]);
> +
> + spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
> +
> + igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
> + __func__, v, values[v]);
> + write_regs(fd, ctx, e, flags, values[v]);
> +
> + regs[1] = read_regs(fd, ctx, e, flags);
> +
> + /*
> + * Restore the original register values before the HW idles.
> + * Or else it may never restart!
> + */
> + restore_regs(fd, ctx, e, flags, regs[0]);
> +
> + igt_spin_batch_free(fd, spin);
> +
> + compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> +
> + for (int n = 0; n < ARRAY_SIZE(regs); n++)
> + gem_close(fd, regs[n]);
> + gem_context_destroy(fd, ctx);
> + gem_close(fd, tmpl);
> + }
> +}
> +
> static void isolation(int fd,
> const struct intel_execution_engine2 *e,
> unsigned int flags)
> @@ -715,6 +821,9 @@ igt_main
> igt_fork_hang_detector(fd);
> }
>
> + igt_subtest_f("%s-nonpriv", e->name)
> + nonpriv(fd, e, 0);
> +
> igt_subtest_f("%s-clean", e->name)
> isolation(fd, e, 0);
> igt_subtest_f("%s-dirty-create", e->name)
> --
> 2.20.1
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
2019-03-02 0:53 ` [igt-dev] " Dale B Stimson
@ 2019-03-02 9:36 ` Chris Wilson
-1 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-02 9:36 UTC (permalink / raw)
To: Dale B Stimson; +Cc: igt-dev, intel-gfx
Quoting Dale B Stimson (2019-03-02 00:53:44)
> Reviewed-By: Dale B Stimson <dale.b.stimson@intel.com>
Ta, plonked it in. Can you respin your patch and confirm that the
registers added are valid for icl?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
@ 2019-03-02 9:36 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-02 9:36 UTC (permalink / raw)
To: Dale B Stimson; +Cc: igt-dev, intel-gfx, Tvrtko Ursulin
Quoting Dale B Stimson (2019-03-02 00:53:44)
> Reviewed-By: Dale B Stimson <dale.b.stimson@intel.com>
Ta, plonked it in. Can you respin your patch and confirm that the
registers added are valid for icl?
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2019-03-02 9:36 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-22 12:39 [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access Chris Wilson
2019-02-22 12:39 ` [igt-dev] " Chris Wilson
2019-02-22 13:17 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-02-22 23:10 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2019-02-23 9:43 ` Chris Wilson
2019-02-23 9:45 ` [PATCH i-g-t] " Chris Wilson
2019-02-23 9:45 ` [igt-dev] " Chris Wilson
2019-03-01 0:36 ` Dale B Stimson
2019-03-01 0:36 ` [igt-dev] " Dale B Stimson
2019-03-01 7:59 ` Chris Wilson
2019-03-01 7:59 ` [igt-dev] " Chris Wilson
2019-02-23 10:19 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Sanitycheck nonpriv access (rev2) Patchwork
2019-02-23 12:31 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2019-03-01 8:19 ` [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access Chris Wilson
2019-03-01 8:19 ` [igt-dev] " Chris Wilson
2019-03-02 0:53 ` Dale B Stimson
2019-03-02 0:53 ` [igt-dev] " Dale B Stimson
2019-03-02 9:36 ` Chris Wilson
2019-03-02 9:36 ` [igt-dev] " Chris Wilson
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