* [PATCH v2 00/10] Compartmentalize uncore code
@ 2019-03-19 18:35 Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 01/10] drm/i915: always use masks on FW regs Daniele Ceraolo Spurio
` (14 more replies)
0 siblings, 15 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Compared to v1 [1], there is a new patch for further simplification of
low-level fw get/put by always using the bitmasks since the upper bits
of the fw reg are reserved on gen6 and I couldn't find any reason
writing them wouldn't work in the git history.
I put together a small selftest to trybot this on snb [2], if people
think it is worth adding it to the tree I can clean it up and send it
for review.
Apart from the above, addresses the review comments, the only
non-trivial one being moving the mmio setup under uncore.
[1] https://patchwork.freedesktop.org/series/57962/
[2] https://patchwork.freedesktop.org/patch/292852/?series=58159&rev=1
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Daniele Ceraolo Spurio (10):
drm/i915: always use masks on FW regs
drm/i915: use intel_uncore in fw get/put internal paths
drm/i915: use intel_uncore for all forcewake get/put
drm/i915: make more uncore function work on intel_uncore
drm/i915: make find_fw_domain work on intel_uncore
drm/i915: reduce the dev_priv->uncore dance in uncore.c
drm/i915: move regs pointer inside the uncore structure
drm/i915: make raw access function work on uncore
drm/i915: add uncore flags
drm/i915: switch uncore mmio funcs to use intel_uncore
drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 17 +-
drivers/gpu/drm/i915/i915_drv.c | 73 +-
drivers/gpu/drm/i915/i915_drv.h | 46 +-
drivers/gpu/drm/i915/i915_gem.c | 20 +-
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/i915_perf.c | 6 +-
drivers/gpu/drm/i915/i915_reset.c | 12 +-
drivers/gpu/drm/i915/i915_vgpu.c | 7 +-
drivers/gpu/drm/i915/intel_display.c | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_guc.c | 8 +-
drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 52 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +-
drivers/gpu/drm/i915/intel_uncore.c | 795 +++++++++---------
drivers/gpu/drm/i915/intel_uncore.h | 71 +-
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 10 +-
drivers/gpu/drm/i915/selftests/mock_uncore.h | 2 +-
26 files changed, 615 insertions(+), 593 deletions(-)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 01/10] drm/i915: always use masks on FW regs
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 23:14 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 02/10] drm/i915: use intel_uncore in fw get/put internal paths Daniele Ceraolo Spurio
` (13 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Upper bits are reserved on gen6, so no issue if we write them. Note that
we're already doing this in the non-MT case of IVB, which uses the same
register.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_uncore.c | 44 +++++++++++------------------
drivers/gpu/drm/i915/intel_uncore.h | 4 ---
2 files changed, 16 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7129eebc333b..b4cea3cf3915 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -59,18 +59,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
}
#define fw_ack(d) readl((d)->reg_ack)
-#define fw_set(d, val) writel((val), (d)->reg_set)
+#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
+#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
static inline void
-fw_domain_reset(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
{
/*
* We don't really know if the powerwell for the forcewake domain we are
* trying to reset here does exist at this point (engines could be fused
* off in ICL+), so no waiting for acks
*/
- fw_set(d, uncore->fw_reset);
+ /* WaRsClearFWBitsAtReset:bdw,skl */
+ fw_clear(d, 0xffff);
}
static inline void
@@ -146,14 +147,14 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
do {
wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
- fw_set(d, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
+ fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
/* Give gt some time to relax before the polling frenzy */
udelay(10 * pass);
wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
ack_detected = (fw_ack(d) & ack_bit) == value;
- fw_set(d, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
+ fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
} while (!ack_detected && pass++ < 10);
DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
@@ -176,10 +177,9 @@ fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
}
static inline void
-fw_domain_get(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_get(const struct intel_uncore_forcewake_domain *d)
{
- fw_set(d, uncore->fw_set);
+ fw_set(d, FORCEWAKE_KERNEL);
}
static inline void
@@ -201,10 +201,9 @@ fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
}
static inline void
-fw_domain_put(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_put(const struct intel_uncore_forcewake_domain *d)
{
- fw_set(d, uncore->fw_clear);
+ fw_clear(d, FORCEWAKE_KERNEL);
}
static void
@@ -218,7 +217,7 @@ fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
fw_domain_wait_ack_clear(d);
- fw_domain_get(uncore, d);
+ fw_domain_get(d);
}
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
@@ -239,7 +238,7 @@ fw_domains_get_with_fallback(struct drm_i915_private *i915,
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
fw_domain_wait_ack_clear_fallback(d);
- fw_domain_get(uncore, d);
+ fw_domain_get(d);
}
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
@@ -258,7 +257,7 @@ fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
- fw_domain_put(uncore, d);
+ fw_domain_put(d);
uncore->fw_domains_active &= ~fw_domains;
}
@@ -277,7 +276,7 @@ fw_domains_reset(struct drm_i915_private *i915,
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
- fw_domain_reset(uncore, d);
+ fw_domain_reset(d);
}
static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
@@ -1371,7 +1370,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
uncore->fw_domains |= BIT(domain_id);
- fw_domain_reset(uncore, d);
+ fw_domain_reset(d);
}
static void fw_domain_fini(struct drm_i915_private *dev_priv,
@@ -1396,17 +1395,6 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
return;
- if (IS_GEN(dev_priv, 6)) {
- dev_priv->uncore.fw_reset = 0;
- dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
- dev_priv->uncore.fw_clear = 0;
- } else {
- /* WaRsClearFWBitsAtReset:bdw,skl */
- dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
- dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
- dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
- }
-
if (INTEL_GEN(dev_priv) >= 11) {
int i;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b0a95469babf..579a7f6b8445 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -106,10 +106,6 @@ struct intel_uncore {
enum forcewake_domains fw_domains_active;
enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
- u32 fw_set;
- u32 fw_clear;
- u32 fw_reset;
-
struct intel_uncore_forcewake_domain {
enum forcewake_domain_id id;
enum forcewake_domains mask;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 02/10] drm/i915: use intel_uncore in fw get/put internal paths
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 01/10] drm/i915: always use masks on FW regs Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put Daniele Ceraolo Spurio
` (12 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Get/put functions used outside of uncore.c are updated in the next
patch for a nicer split.
v2: use dev_priv where we still have it (Paulo)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_uncore.c | 191 +++++++++---------
drivers/gpu/drm/i915/intel_uncore.h | 17 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
6 files changed, 117 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 08683dca7775..a52b7cf1525d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1414,13 +1414,14 @@ static int ironlake_drpc_info(struct seq_file *m)
static int i915_forcewake_domains(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *fw_domain;
unsigned int tmp;
seq_printf(m, "user.bypass_count = %u\n",
- i915->uncore.user_forcewake.count);
+ uncore->user_forcewake.count);
- for_each_fw_domain(fw_domain, i915, tmp)
+ for_each_fw_domain(fw_domain, uncore, tmp)
seq_printf(m, "%s.wake_count = %u\n",
intel_uncore_forcewake_domain_to_str(fw_domain->id),
READ_ONCE(fw_domain->wake_count));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a3b00ecc58c9..98fe40c7be71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2914,7 +2914,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_opregion_notify_adapter(dev_priv, PCI_D1);
}
- assert_forcewakes_inactive(dev_priv);
+ assert_forcewakes_inactive(&dev_priv->uncore);
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
intel_hpd_poll_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c65c2e6649df..64f0e13d6912 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2102,6 +2102,11 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
return container_of(huc, struct drm_i915_private, huc);
}
+static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
+{
+ return container_of(uncore, struct drm_i915_private, uncore);
+}
+
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__, id__) \
for ((id__) = 0; \
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b4cea3cf3915..ebbb9af970dc 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -207,66 +207,62 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
fw_domain_wait_ack_clear(d);
fw_domain_get(d);
}
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_wait_ack_set(d);
uncore->fw_domains_active |= fw_domains;
}
static void
-fw_domains_get_with_fallback(struct drm_i915_private *i915,
+fw_domains_get_with_fallback(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
fw_domain_wait_ack_clear_fallback(d);
fw_domain_get(d);
}
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_wait_ack_set_fallback(d);
uncore->fw_domains_active |= fw_domains;
}
static void
-fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
+fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_put(d);
uncore->fw_domains_active &= ~fw_domains;
}
static void
-fw_domains_reset(struct drm_i915_private *i915,
+fw_domains_reset(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -275,7 +271,7 @@ fw_domains_reset(struct drm_i915_private *i915,
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_reset(d);
}
@@ -299,13 +295,13 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
"GT thread status wait timed out\n");
}
-static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
+static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- fw_domains_get(dev_priv, fw_domains);
+ fw_domains_get(uncore, fw_domains);
/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
- __gen6_gt_wait_for_thread_c0(dev_priv);
+ __gen6_gt_wait_for_thread_c0(uncore_to_i915(uncore));
}
static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
@@ -343,30 +339,29 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
{
struct intel_uncore_forcewake_domain *domain =
container_of(timer, struct intel_uncore_forcewake_domain, timer);
- struct drm_i915_private *dev_priv =
- container_of(domain, struct drm_i915_private, uncore.fw_domain[domain->id]);
+ struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
unsigned long irqflags;
- assert_rpm_device_not_suspended(dev_priv);
+ assert_rpm_device_not_suspended(uncore_to_i915(uncore));
if (xchg(&domain->active, false))
return HRTIMER_RESTART;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ spin_lock_irqsave(&uncore->lock, irqflags);
if (WARN_ON(domain->wake_count == 0))
domain->wake_count++;
if (--domain->wake_count == 0)
- dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
+ uncore->funcs.force_wake_put(uncore, domain->mask);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
return HRTIMER_NORESTART;
}
/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
static unsigned int
-intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
+intel_uncore_forcewake_reset(struct intel_uncore *uncore)
{
unsigned long irqflags;
struct intel_uncore_forcewake_domain *domain;
@@ -384,7 +379,7 @@ intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
active_domains = 0;
- for_each_fw_domain(domain, dev_priv, tmp) {
+ for_each_fw_domain(domain, uncore, tmp) {
smp_store_mb(domain->active, false);
if (hrtimer_cancel(&domain->timer) == 0)
continue;
@@ -392,9 +387,9 @@ intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
intel_uncore_fw_release_timer(&domain->timer);
}
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ spin_lock_irqsave(&uncore->lock, irqflags);
- for_each_fw_domain(domain, dev_priv, tmp) {
+ for_each_fw_domain(domain, uncore, tmp) {
if (hrtimer_active(&domain->timer))
active_domains |= domain->mask;
}
@@ -407,20 +402,20 @@ intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
break;
}
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
cond_resched();
}
WARN_ON(active_domains);
- fw = dev_priv->uncore.fw_domains_active;
+ fw = uncore->fw_domains_active;
if (fw)
- dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
+ uncore->funcs.force_wake_put(uncore, fw);
- fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains);
- assert_forcewakes_inactive(dev_priv);
+ fw_domains_reset(uncore, uncore->fw_domains);
+ assert_forcewakes_inactive(uncore);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
return fw; /* track the lost user forcewake domains */
}
@@ -546,10 +541,10 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
}
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(dev_priv);
+ intel_uncore_forcewake_reset(&dev_priv->uncore);
if (restore_forcewake) {
spin_lock_irq(&dev_priv->uncore.lock);
- dev_priv->uncore.funcs.force_wake_get(dev_priv,
+ dev_priv->uncore.funcs.force_wake_get(&dev_priv->uncore,
restore_forcewake);
if (IS_GEN_RANGE(dev_priv, 6, 7))
@@ -566,7 +561,7 @@ void intel_uncore_suspend(struct drm_i915_private *dev_priv)
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
&dev_priv->uncore.pmic_bus_access_nb);
dev_priv->uncore.fw_domains_saved =
- intel_uncore_forcewake_reset(dev_priv);
+ intel_uncore_forcewake_reset(&dev_priv->uncore);
iosf_mbi_punit_release();
}
@@ -594,15 +589,15 @@ void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
intel_sanitize_gt_powersave(dev_priv);
}
-static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- fw_domains &= dev_priv->uncore.fw_domains;
+ fw_domains &= uncore->fw_domains;
- for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
+ for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
if (domain->wake_count++) {
fw_domains &= ~domain->mask;
domain->active = true;
@@ -610,7 +605,7 @@ static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
}
if (fw_domains)
- dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+ uncore->funcs.force_wake_get(uncore, fw_domains);
}
/**
@@ -629,16 +624,17 @@ static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
enum forcewake_domains fw_domains)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long irqflags;
- if (!dev_priv->uncore.funcs.force_wake_get)
+ if (!uncore->funcs.force_wake_get)
return;
assert_rpm_wakelock_held(dev_priv);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- __intel_uncore_forcewake_get(dev_priv, fw_domains);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_get(uncore, fw_domains);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
}
/**
@@ -651,20 +647,22 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
*/
void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->uncore.lock);
- if (!dev_priv->uncore.user_forcewake.count++) {
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ spin_lock_irq(&uncore->lock);
+ if (!uncore->user_forcewake.count++) {
intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
/* Save and disable mmio debugging for the user bypass */
- dev_priv->uncore.user_forcewake.saved_mmio_check =
- dev_priv->uncore.unclaimed_mmio_check;
- dev_priv->uncore.user_forcewake.saved_mmio_debug =
+ uncore->user_forcewake.saved_mmio_check =
+ uncore->unclaimed_mmio_check;
+ uncore->user_forcewake.saved_mmio_debug =
i915_modparams.mmio_debug;
- dev_priv->uncore.unclaimed_mmio_check = 0;
+ uncore->unclaimed_mmio_check = 0;
i915_modparams.mmio_debug = 0;
}
- spin_unlock_irq(&dev_priv->uncore.lock);
+ spin_unlock_irq(&uncore->lock);
}
/**
@@ -676,20 +674,22 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
*/
void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->uncore.lock);
- if (!--dev_priv->uncore.user_forcewake.count) {
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ spin_lock_irq(&uncore->lock);
+ if (!--uncore->user_forcewake.count) {
if (intel_uncore_unclaimed_mmio(dev_priv))
dev_info(dev_priv->drm.dev,
"Invalid mmio detected during user access\n");
- dev_priv->uncore.unclaimed_mmio_check =
- dev_priv->uncore.user_forcewake.saved_mmio_check;
+ uncore->unclaimed_mmio_check =
+ uncore->user_forcewake.saved_mmio_check;
i915_modparams.mmio_debug =
- dev_priv->uncore.user_forcewake.saved_mmio_debug;
+ uncore->user_forcewake.saved_mmio_debug;
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
}
- spin_unlock_irq(&dev_priv->uncore.lock);
+ spin_unlock_irq(&uncore->lock);
}
/**
@@ -703,23 +703,25 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
enum forcewake_domains fw_domains)
{
- lockdep_assert_held(&dev_priv->uncore.lock);
+ struct intel_uncore *uncore = &dev_priv->uncore;
- if (!dev_priv->uncore.funcs.force_wake_get)
+ lockdep_assert_held(&uncore->lock);
+
+ if (!uncore->funcs.force_wake_get)
return;
- __intel_uncore_forcewake_get(dev_priv, fw_domains);
+ __intel_uncore_forcewake_get(uncore, fw_domains);
}
-static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- fw_domains &= dev_priv->uncore.fw_domains;
+ fw_domains &= uncore->fw_domains;
- for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
+ for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
if (WARN_ON(domain->wake_count == 0))
continue;
@@ -743,14 +745,15 @@ static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
enum forcewake_domains fw_domains)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long irqflags;
- if (!dev_priv->uncore.funcs.force_wake_put)
+ if (!uncore->funcs.force_wake_put)
return;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- __intel_uncore_forcewake_put(dev_priv, fw_domains);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
}
/**
@@ -764,36 +767,38 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
enum forcewake_domains fw_domains)
{
- lockdep_assert_held(&dev_priv->uncore.lock);
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ lockdep_assert_held(&uncore->lock);
- if (!dev_priv->uncore.funcs.force_wake_put)
+ if (!uncore->funcs.force_wake_put)
return;
- __intel_uncore_forcewake_put(dev_priv, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains);
}
-void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
+void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!dev_priv->uncore.funcs.force_wake_get)
+ if (!uncore->funcs.force_wake_get)
return;
- WARN(dev_priv->uncore.fw_domains_active,
+ WARN(uncore->fw_domains_active,
"Expected all fw_domains to be inactive, but %08x are still on\n",
- dev_priv->uncore.fw_domains_active);
+ uncore->fw_domains_active);
}
-void assert_forcewakes_active(struct drm_i915_private *dev_priv,
+void assert_forcewakes_active(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- if (!dev_priv->uncore.funcs.force_wake_get)
+ if (!uncore->funcs.force_wake_get)
return;
- assert_rpm_wakelock_held(dev_priv);
+ assert_rpm_wakelock_held(uncore_to_i915(uncore));
- fw_domains &= dev_priv->uncore.fw_domains;
- WARN(fw_domains & ~dev_priv->uncore.fw_domains_active,
+ fw_domains &= uncore->fw_domains;
+ WARN(fw_domains & ~uncore->fw_domains_active,
"Expected %08x fw_domains to be active, but %08x are off\n",
- fw_domains, fw_domains & ~dev_priv->uncore.fw_domains_active);
+ fw_domains, fw_domains & ~uncore->fw_domains_active);
}
/* We give fast paths for the really cool registers */
@@ -1157,32 +1162,32 @@ __gen2_read(64)
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
-static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
+static noinline void ___force_wake_auto(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- GEM_BUG_ON(fw_domains & ~dev_priv->uncore.fw_domains);
+ GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp)
+ for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
fw_domain_arm_timer(domain);
- dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+ uncore->funcs.force_wake_get(uncore, fw_domains);
}
-static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
+static inline void __force_wake_auto(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
if (WARN_ON(!fw_domains))
return;
/* Turn on all requested but inactive supported forcewake domains. */
- fw_domains &= dev_priv->uncore.fw_domains;
- fw_domains &= ~dev_priv->uncore.fw_domains_active;
+ fw_domains &= uncore->fw_domains;
+ fw_domains &= ~uncore->fw_domains_active;
if (fw_domains)
- ___force_wake_auto(dev_priv, fw_domains);
+ ___force_wake_auto(uncore, fw_domains);
}
#define __gen_read(func, x) \
@@ -1192,7 +1197,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
GEN6_READ_HEADER(x); \
fw_engine = __##func##_reg_read_fw_domains(offset); \
if (fw_engine) \
- __force_wake_auto(dev_priv, fw_engine); \
+ __force_wake_auto(&dev_priv->uncore, fw_engine); \
val = __raw_i915_read##x(dev_priv, reg); \
GEN6_READ_FOOTER; \
}
@@ -1284,7 +1289,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
GEN6_WRITE_HEADER; \
fw_engine = __##func##_reg_write_fw_domains(offset); \
if (fw_engine) \
- __force_wake_auto(dev_priv, fw_engine); \
+ __force_wake_auto(&dev_priv->uncore, fw_engine); \
__raw_i915_write##x(dev_priv, reg, val); \
GEN6_WRITE_FOOTER; \
}
@@ -1478,9 +1483,9 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
spin_lock_irq(&dev_priv->uncore.lock);
- fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_RENDER);
+ fw_domains_get_with_thread_status(&dev_priv->uncore, FORCEWAKE_RENDER);
ecobus = __raw_i915_read32(dev_priv, ECOBUS);
- fw_domains_put(dev_priv, FORCEWAKE_RENDER);
+ fw_domains_put(&dev_priv->uncore, FORCEWAKE_RENDER);
spin_unlock_irq(&dev_priv->uncore.lock);
if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
@@ -1634,7 +1639,7 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
&dev_priv->uncore.pmic_bus_access_nb);
- intel_uncore_forcewake_reset(dev_priv);
+ intel_uncore_forcewake_reset(&dev_priv->uncore);
iosf_mbi_punit_release();
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 579a7f6b8445..73b1bd9a391d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -32,6 +32,7 @@
#include "i915_reg.h"
struct drm_i915_private;
+struct intel_uncore;
enum forcewake_domain_id {
FW_DOMAIN_ID_RENDER = 0,
@@ -62,9 +63,9 @@ enum forcewake_domains {
};
struct intel_uncore_funcs {
- void (*force_wake_get)(struct drm_i915_private *dev_priv,
+ void (*force_wake_get)(struct intel_uncore *uncore,
enum forcewake_domains domains);
- void (*force_wake_put)(struct drm_i915_private *dev_priv,
+ void (*force_wake_put)(struct intel_uncore *uncore,
enum forcewake_domains domains);
u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
@@ -127,12 +128,12 @@ struct intel_uncore {
};
/* Iterate over initialised fw domains */
-#define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
+#define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
for (tmp__ = (mask__); \
- tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
+ tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
-#define for_each_fw_domain(domain__, dev_priv__, tmp__) \
- for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
+#define for_each_fw_domain(domain__, uncore__, tmp__) \
+ for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
static inline struct intel_uncore *
forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
@@ -151,8 +152,8 @@ void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
-void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
-void assert_forcewakes_active(struct drm_i915_private *dev_priv,
+void assert_forcewakes_inactive(struct intel_uncore *uncore);
+void assert_forcewakes_active(struct intel_uncore *uncore,
enum forcewake_domains fw_domains);
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 81d9d31042a9..1c15f8d146aa 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -160,7 +160,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
i915_reg_t reg = { offset };
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(dev_priv);
+ intel_uncore_forcewake_reset(&dev_priv->uncore);
iosf_mbi_punit_release();
check_for_unclaimed_mmio(dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 01/10] drm/i915: always use masks on FW regs Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 02/10] drm/i915: use intel_uncore in fw get/put internal paths Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 23:48 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 04/10] drm/i915: make more uncore function work on intel_uncore Daniele Ceraolo Spurio
` (11 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Now that the internal code all works on intel_uncore, flip the
external-facing interface.
v2: fix GVT.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 12 ++---
drivers/gpu/drm/i915/i915_gem.c | 20 +++----
drivers/gpu/drm/i915/i915_perf.c | 6 +--
drivers/gpu/drm/i915/i915_reset.c | 12 ++---
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_guc.c | 8 +--
drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 52 +++++++++----------
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +--
drivers/gpu/drm/i915/intel_uncore.c | 52 ++++++++-----------
drivers/gpu/drm/i915/intel_uncore.h | 12 ++---
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 4 +-
17 files changed, 105 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index f64c76dd11d4..a00a807a1d55 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -356,7 +356,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
fw |= FORCEWAKE_RENDER;
- intel_uncore_forcewake_get(dev_priv, fw);
+ intel_uncore_forcewake_get(&dev_priv->uncore, fw);
I915_WRITE_FW(reg, 0x1);
@@ -365,7 +365,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
else
vgpu_vreg_t(vgpu, reg) = 0;
- intel_uncore_forcewake_put(dev_priv, fw);
+ intel_uncore_forcewake_put(&dev_priv->uncore, fw);
gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}
@@ -552,9 +552,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
* performace for batch mmio read/write, so we need
* handle forcewake mannually.
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
switch_mmio(pre, next, ring_id);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
/**
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 7550e09939ae..3faf2438b9bc 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -988,7 +988,7 @@ static int workload_thread(void *priv)
workload->ring_id, workload);
if (need_force_wake)
- intel_uncore_forcewake_get(gvt->dev_priv,
+ intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
ret = dispatch_workload(workload);
@@ -1010,7 +1010,7 @@ static int workload_thread(void *priv)
complete_current_workload(gvt, ring_id);
if (need_force_wake)
- intel_uncore_forcewake_put(gvt->dev_priv,
+ intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
intel_runtime_pm_put_unchecked(gvt->dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a52b7cf1525d..0dd8b3fa7fb9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1094,7 +1094,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
}
/* RPSTAT1 is in the GT power well */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
reqf = I915_READ(GEN6_RPNSWREQ);
if (INTEL_GEN(dev_priv) >= 9)
@@ -1122,7 +1122,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
cagf = intel_gpu_freq(dev_priv,
intel_get_cagf(dev_priv, rpstat));
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
if (INTEL_GEN(dev_priv) >= 11) {
pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
@@ -2060,12 +2060,12 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
u32 rpup, rpupei;
u32 rpdown, rpdownei;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
rps_power_to_str(rps->power.mode));
@@ -4251,7 +4251,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
return 0;
file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);
- intel_uncore_forcewake_user_get(i915);
+ intel_uncore_forcewake_user_get(&i915->uncore);
return 0;
}
@@ -4263,7 +4263,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
if (INTEL_GEN(i915) < 6)
return 0;
- intel_uncore_forcewake_user_put(i915);
+ intel_uncore_forcewake_user_put(&i915->uncore);
intel_runtime_pm_put(i915,
(intel_wakeref_t)(uintptr_t)file->private_data);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7086c8d4726..49dcf7ec6287 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4318,7 +4318,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
GEM_TRACE("\n");
wakeref = intel_runtime_pm_get(i915);
- intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
/*
* As we have just resumed the machine and woken the device up from
@@ -4339,7 +4339,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
*/
intel_engines_sanitize(i915, false);
- intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(i915, wakeref);
mutex_lock(&i915->drm.struct_mutex);
@@ -4438,7 +4438,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
WARN_ON(i915->gt.awake);
mutex_lock(&i915->drm.struct_mutex);
- intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
i915_gem_restore_gtt_mappings(i915);
i915_gem_restore_fences(i915);
@@ -4460,7 +4460,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
goto err_wedged;
out_unlock:
- intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
mutex_unlock(&i915->drm.struct_mutex);
return;
@@ -4549,7 +4549,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
dev_priv->gt.last_init_time = ktime_get();
/* Double layer security blanket, see i915_gem_init() */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
@@ -4604,14 +4604,14 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto cleanup_uc;
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
return 0;
cleanup_uc:
intel_uc_fini_hw(dev_priv);
out:
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
return ret;
}
@@ -4815,7 +4815,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
* just magically go away.
*/
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
ret = i915_gem_init_ggtt(dev_priv);
if (ret) {
@@ -4877,7 +4877,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_init_hw;
}
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
return 0;
@@ -4912,7 +4912,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
i915_gem_fini_scratch(dev_priv);
err_ggtt:
err_unlock:
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
err_uc_misc:
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9b0292a38865..e0fcb982a14f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1364,7 +1364,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
free_oa_buffer(dev_priv);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv, stream->wakeref);
if (stream->ctx)
@@ -2093,7 +2093,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
* references will effectively disable RC6.
*/
stream->wakeref = intel_runtime_pm_get(dev_priv);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
ret = alloc_oa_buffer(dev_priv);
if (ret)
@@ -2127,7 +2127,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
err_oa_buf_alloc:
put_oa_config(dev_priv, stream->oa_config);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv, stream->wakeref);
err_config:
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index fb86d5ca5d8b..0aea19cefe4a 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -569,7 +569,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
* If the power well sleeps during the reset, the reset
* request may be dropped and never completes (causing -EIO).
*/
- intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
/*
* We stop engines, otherwise we might get failed reset and a
@@ -593,7 +593,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
ret = reset(i915, engine_mask, retry);
preempt_enable();
}
- intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
return ret;
}
@@ -622,9 +622,9 @@ int intel_reset_guc(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(i915, guc_domain);
- intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
return ret;
}
@@ -642,7 +642,7 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
* written to the powercontext is undefined and so we may lose
* GPU state upon resume, i.e. fail to restart after a reset.
*/
- intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&engine->i915->uncore, FORCEWAKE_ALL);
engine->reset.prepare(engine);
}
@@ -713,7 +713,7 @@ static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
static void reset_finish_engine(struct intel_engine_cs *engine)
{
engine->reset.finish(engine);
- intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&engine->i915->uncore, FORCEWAKE_ALL);
}
struct i915_gpu_restart {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf2af75..d4fcad136120 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9503,7 +9503,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
* Make sure we're not on PC8 state before disabling PC8, otherwise
* we'll hang the machine. To prevent PC8 state, just enable force_wake.
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
if (val & LCPLL_POWER_DOWN_ALLOW) {
val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -9535,7 +9535,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
DRM_ERROR("Switching back to LCPLL failed\n");
}
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 652c1b3ba190..588c640b5a57 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -919,7 +919,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
FW_REG_READ | FW_REG_WRITE);
spin_lock_irq(&dev_priv->uncore.lock);
- intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+ intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
@@ -937,7 +937,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
- intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+ intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
spin_unlock_irq(&dev_priv->uncore.lock);
return ret;
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 8ecb47087457..a59448a56f55 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -369,14 +369,14 @@ void intel_guc_init_params(struct intel_guc *guc)
* they are power context saved so it's ok to release forcewake
* when we are done here and take it again at xfer time.
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
I915_WRITE(SOFT_SCRATCH(0), 0);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
}
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
@@ -414,7 +414,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
mutex_lock(&guc->send_mutex);
- intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
+ intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);
for (i = 0; i < len; i++)
I915_WRITE(guc_send_reg(guc, i), action[i]);
@@ -454,7 +454,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
ret = INTEL_GUC_MSG_TO_DATA(status);
out:
- intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
+ intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);
mutex_unlock(&guc->send_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 13ff7003c6be..792a551450c7 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -241,7 +241,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
guc_prepare_xfer(guc);
@@ -254,7 +254,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
ret = guc_xfer_ucode(guc, vma);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 7d7bfc7f7ca7..92799b8502f5 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -112,7 +112,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Set the source address for the uCode */
offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
@@ -140,7 +140,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
/* Disable the bits once DMA is over */
I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d73b13ca57a0..007529dd161c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6737,9 +6737,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
* punit into committing the voltage change) as that takes a lot less
* power than the render powerwell.
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
err = valleyview_set_rps(dev_priv, val);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
if (err)
DRM_ERROR("Failed to set RPS for idle\n");
@@ -6889,11 +6889,11 @@ static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
{
/* We're doing forcewake before Disabling RC6,
* This what the BIOS expects when going into suspend */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
I915_WRITE(GEN6_RC_CONTROL, 0);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -7052,7 +7052,7 @@ static void reset_rps(struct drm_i915_private *dev_priv,
/* See the Gen9_GT_PM_Programming_Guide doc for the below */
static void gen9_enable_rps(struct drm_i915_private *dev_priv)
{
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Program defaults and thresholds for RPS */
if (IS_GEN(dev_priv, 9))
@@ -7070,7 +7070,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
* RP_INTERRUPT_LIMITS & RPNSWREQ registers */
reset_rps(dev_priv, gen6_set_rps);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -7084,7 +7084,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
/* 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7161,7 +7161,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN9_PG_ENABLE,
GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
@@ -7174,7 +7174,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
/* 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7195,14 +7195,14 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_RC6_ENABLE);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen8_enable_rps(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* 1 Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RPNSWREQ,
@@ -7235,7 +7235,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
@@ -7255,7 +7255,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GTFIFODBG, gtfifodbg);
}
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7303,7 +7303,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
}
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -7314,7 +7314,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
* Perhaps there might be some value in exposing these to
* userspace...
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Power down if completely idle for over 50ms */
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
@@ -7322,7 +7322,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -7745,7 +7745,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
/* 1a & 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7777,14 +7777,14 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
rc6_mode = GEN7_RC_CTL_TO_MODE;
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
{
u32 val;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* 1: Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
@@ -7819,7 +7819,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
@@ -7837,7 +7837,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GTFIFODBG, gtfifodbg);
}
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7862,14 +7862,14 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL,
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
{
u32 val;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
@@ -7903,7 +7903,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static unsigned long intel_pxfreq(u32 vidfreq)
@@ -9955,7 +9955,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
spin_lock_irqsave(&dev_priv->uncore.lock, flags);
- intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+ intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -9996,7 +9996,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
- intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+ intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
return mul_u64_u32_div(time_hw, mul, div);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f26f5cc1584c..3641175baa72 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -644,7 +644,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
struct intel_ring *ring = engine->buffer;
int ret = 0;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
if (!stop_ring(engine)) {
/* G45 ring initialization often fails to reset head to zero */
@@ -731,7 +731,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
/* Papering over lost _interrupts_ immediately following the restart */
intel_engine_queue_breadcrumbs(engine);
out:
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
return ret;
}
@@ -2079,7 +2079,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
{
struct drm_i915_private *dev_priv = request->i915;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
/* Every tail move must follow the sequence below */
@@ -2109,7 +2109,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
static int mi_flush_dw(struct i915_request *rq, u32 flags)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ebbb9af970dc..2e50697e72b4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -610,7 +610,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
/**
* intel_uncore_forcewake_get - grab forcewake domain references
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
* @fw_domains: forcewake domains to get reference on
*
* This function can be used get GT's forcewake domain references.
@@ -621,16 +621,15 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
* call to intel_unforce_forcewake_put(). Usually caller wants all the domains
* to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
*/
-void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_get(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long irqflags;
if (!uncore->funcs.force_wake_get)
return;
- assert_rpm_wakelock_held(dev_priv);
+ assert_rpm_wakelock_held(uncore_to_i915(uncore));
spin_lock_irqsave(&uncore->lock, irqflags);
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -639,19 +638,17 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
/**
* intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
*
* This function is a wrapper around intel_uncore_forcewake_get() to acquire
* the GT powerwell and in the process disable our debugging for the
* duration of userspace's bypass.
*/
-void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
+void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
spin_lock_irq(&uncore->lock);
if (!uncore->user_forcewake.count++) {
- intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
/* Save and disable mmio debugging for the user bypass */
uncore->user_forcewake.saved_mmio_check =
@@ -667,19 +664,19 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
/**
* intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
*
* This function complements intel_uncore_forcewake_user_get() and releases
* the GT powerwell taken on behalf of the userspace bypass.
*/
-void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
+void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
spin_lock_irq(&uncore->lock);
if (!--uncore->user_forcewake.count) {
- if (intel_uncore_unclaimed_mmio(dev_priv))
- dev_info(dev_priv->drm.dev,
+ if (intel_uncore_unclaimed_mmio(i915))
+ dev_info(i915->drm.dev,
"Invalid mmio detected during user access\n");
uncore->unclaimed_mmio_check =
@@ -687,24 +684,22 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
i915_modparams.mmio_debug =
uncore->user_forcewake.saved_mmio_debug;
- intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
}
spin_unlock_irq(&uncore->lock);
}
/**
* intel_uncore_forcewake_get__locked - grab forcewake domain references
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
* @fw_domains: forcewake domains to get reference on
*
* See intel_uncore_forcewake_get(). This variant places the onus
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
*/
-void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
lockdep_assert_held(&uncore->lock);
if (!uncore->funcs.force_wake_get)
@@ -736,16 +731,15 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
/**
* intel_uncore_forcewake_put - release a forcewake domain reference
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
* @fw_domains: forcewake domains to put references
*
* This function drops the device-level forcewakes for specified
* domains obtained by intel_uncore_forcewake_get().
*/
-void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_put(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long irqflags;
if (!uncore->funcs.force_wake_put)
@@ -758,17 +752,15 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
/**
* intel_uncore_forcewake_put__locked - grab forcewake domain references
- * @dev_priv: i915 device instance
+ * @uncore: the intel_uncore structure
* @fw_domains: forcewake domains to get reference on
*
* See intel_uncore_forcewake_put(). This variant places the onus
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
*/
-void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
lockdep_assert_held(&uncore->lock);
if (!uncore->funcs.force_wake_put)
@@ -1535,11 +1527,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
* the access.
*/
disable_rpm_wakeref_asserts(dev_priv);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
enable_rpm_wakeref_asserts(dev_priv);
break;
case MBI_PMIC_BUS_ACCESS_END:
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
break;
}
@@ -1796,13 +1788,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
might_sleep_if(slow_timeout_ms);
spin_lock_irq(&dev_priv->uncore.lock);
- intel_uncore_forcewake_get__locked(dev_priv, fw);
+ intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
ret = __intel_wait_for_register_fw(dev_priv,
reg, mask, value,
fast_timeout_us, 0, ®_value);
- intel_uncore_forcewake_put__locked(dev_priv, fw);
+ intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
spin_unlock_irq(&dev_priv->uncore.lock);
if (ret && slow_timeout_ms)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 73b1bd9a391d..b9010184a780 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -163,20 +163,20 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
#define FW_REG_READ (1)
#define FW_REG_WRITE (2)
-void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_get(struct intel_uncore *uncore,
enum forcewake_domains domains);
-void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_put(struct intel_uncore *uncore,
enum forcewake_domains domains);
/* Like above but the caller must manage the uncore.lock itself.
* Must be used with I915_READ_FW and friends.
*/
-void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
enum forcewake_domains domains);
-void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
+void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
enum forcewake_domains domains);
-void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
-void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
+void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
+void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
int __intel_wait_for_register(struct drm_i915_private *dev_priv,
i915_reg_t reg,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 283e9a4ef3ca..e758bbf50617 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -927,7 +927,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
fw = wal_get_fw_for_rmw(dev_priv, wal);
spin_lock_irqsave(&dev_priv->uncore.lock, flags);
- intel_uncore_forcewake_get__locked(dev_priv, fw);
+ intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
u32 val = I915_READ_FW(wa->reg);
@@ -938,7 +938,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
I915_WRITE_FW(wa->reg, val);
}
- intel_uncore_forcewake_put__locked(dev_priv, fw);
+ intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
}
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 1c15f8d146aa..69aa260b479d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -142,7 +142,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
if (!valid)
return -ENOMEM;
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
check_for_unclaimed_mmio(dev_priv);
for (offset = 0; offset < FW_RANGE; offset += 4) {
@@ -153,7 +153,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
set_bit(offset, valid);
}
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
err = 0;
for_each_set_bit(offset, valid, FW_RANGE) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 04/10] drm/i915: make more uncore function work on intel_uncore
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 05/10] drm/i915: make find_fw_domain " Daniele Ceraolo Spurio
` (10 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Move the init, fini, prune, suspend, resume function to work on
intel_uncore instead of dev_priv.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 20 +-
drivers/gpu/drm/i915/intel_uncore.c | 273 +++++++++---------
drivers/gpu/drm/i915/intel_uncore.h | 12 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 6 +-
drivers/gpu/drm/i915/selftests/mock_uncore.h | 2 +-
6 files changed, 159 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 98fe40c7be71..5561488ecfcd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -993,11 +993,11 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
if (ret < 0)
goto err_bridge;
- intel_uncore_init(dev_priv);
+ intel_uncore_init(&dev_priv->uncore);
intel_device_info_init_mmio(dev_priv);
- intel_uncore_prune(dev_priv);
+ intel_uncore_prune(&dev_priv->uncore);
intel_uc_init_mmio(dev_priv);
@@ -1010,7 +1010,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
return 0;
err_uncore:
- intel_uncore_fini(dev_priv);
+ intel_uncore_fini(&dev_priv->uncore);
i915_mmio_cleanup(dev_priv);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1024,7 +1024,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
- intel_uncore_fini(dev_priv);
+ intel_uncore_fini(&dev_priv->uncore);
i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -2086,7 +2086,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
i915_gem_suspend_late(dev_priv);
- intel_uncore_suspend(dev_priv);
+ intel_uncore_suspend(&dev_priv->uncore);
intel_power_domains_suspend(dev_priv,
get_suspend_mode(dev_priv, hibernation));
@@ -2282,7 +2282,9 @@ static int i915_drm_resume_early(struct drm_device *dev)
DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
ret);
- intel_uncore_resume_early(dev_priv);
+ intel_uncore_resume_early(&dev_priv->uncore);
+
+ i915_check_and_clear_faults(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
@@ -2852,7 +2854,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_runtime_pm_disable_interrupts(dev_priv);
- intel_uncore_suspend(dev_priv);
+ intel_uncore_suspend(&dev_priv->uncore);
ret = 0;
if (INTEL_GEN(dev_priv) >= 11) {
@@ -2869,7 +2871,7 @@ static int intel_runtime_suspend(struct device *kdev)
if (ret) {
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
- intel_uncore_runtime_resume(dev_priv);
+ intel_uncore_runtime_resume(&dev_priv->uncore);
intel_runtime_pm_enable_interrupts(dev_priv);
@@ -2966,7 +2968,7 @@ static int intel_runtime_resume(struct device *kdev)
ret = vlv_resume_prepare(dev_priv, true);
}
- intel_uncore_runtime_resume(dev_priv);
+ intel_uncore_runtime_resume(&dev_priv->uncore);
intel_runtime_pm_enable_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2e50697e72b4..d58f96ea774c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -525,62 +525,58 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
return ret;
}
-static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
+static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
unsigned int restore_forcewake)
{
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(dev_priv))
+ if (check_for_unclaimed_mmio(i915))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
- if (IS_CHERRYVIEW(dev_priv)) {
- __raw_i915_write32(dev_priv, GTFIFOCTL,
- __raw_i915_read32(dev_priv, GTFIFOCTL) |
+ if (IS_CHERRYVIEW(i915)) {
+ __raw_i915_write32(i915, GTFIFOCTL,
+ __raw_i915_read32(i915, GTFIFOCTL) |
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
GT_FIFO_CTL_RC6_POLICY_STALL);
}
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(&dev_priv->uncore);
+ intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
- spin_lock_irq(&dev_priv->uncore.lock);
- dev_priv->uncore.funcs.force_wake_get(&dev_priv->uncore,
- restore_forcewake);
-
- if (IS_GEN_RANGE(dev_priv, 6, 7))
- dev_priv->uncore.fifo_count =
- fifo_free_entries(dev_priv);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ spin_lock_irq(&uncore->lock);
+ uncore->funcs.force_wake_get(uncore, restore_forcewake);
+
+ if (IS_GEN_RANGE(i915, 6, 7))
+ uncore->fifo_count = fifo_free_entries(i915);
+ spin_unlock_irq(&uncore->lock);
}
iosf_mbi_punit_release();
}
-void intel_uncore_suspend(struct drm_i915_private *dev_priv)
+void intel_uncore_suspend(struct intel_uncore *uncore)
{
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
- &dev_priv->uncore.pmic_bus_access_nb);
- dev_priv->uncore.fw_domains_saved =
- intel_uncore_forcewake_reset(&dev_priv->uncore);
+ &uncore->pmic_bus_access_nb);
+ uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
iosf_mbi_punit_release();
}
-void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
+void intel_uncore_resume_early(struct intel_uncore *uncore)
{
unsigned int restore_forcewake;
- restore_forcewake = fetch_and_zero(&dev_priv->uncore.fw_domains_saved);
- __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
+ restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
+ __intel_uncore_early_sanitize(uncore, restore_forcewake);
- iosf_mbi_register_pmic_bus_access_notifier(
- &dev_priv->uncore.pmic_bus_access_nb);
- i915_check_and_clear_faults(dev_priv);
+ iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
}
-void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv)
+void intel_uncore_runtime_resume(struct intel_uncore *uncore)
{
- iosf_mbi_register_pmic_bus_access_notifier(
- &dev_priv->uncore.pmic_bus_access_nb);
+ iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
}
void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
@@ -1309,29 +1305,29 @@ __gen6_write(32)
#undef GEN6_WRITE_FOOTER
#undef GEN6_WRITE_HEADER
-#define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \
+#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
do { \
- (i915)->uncore.funcs.mmio_writeb = x##_write8; \
- (i915)->uncore.funcs.mmio_writew = x##_write16; \
- (i915)->uncore.funcs.mmio_writel = x##_write32; \
+ (uncore)->funcs.mmio_writeb = x##_write8; \
+ (uncore)->funcs.mmio_writew = x##_write16; \
+ (uncore)->funcs.mmio_writel = x##_write32; \
} while (0)
-#define ASSIGN_READ_MMIO_VFUNCS(i915, x) \
+#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
do { \
- (i915)->uncore.funcs.mmio_readb = x##_read8; \
- (i915)->uncore.funcs.mmio_readw = x##_read16; \
- (i915)->uncore.funcs.mmio_readl = x##_read32; \
- (i915)->uncore.funcs.mmio_readq = x##_read64; \
+ (uncore)->funcs.mmio_readb = x##_read8; \
+ (uncore)->funcs.mmio_readw = x##_read16; \
+ (uncore)->funcs.mmio_readl = x##_read32; \
+ (uncore)->funcs.mmio_readq = x##_read64; \
} while (0)
-static void fw_domain_init(struct drm_i915_private *dev_priv,
+static void fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
i915_reg_t reg_set,
i915_reg_t reg_ack)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
struct intel_uncore_forcewake_domain *d;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
return;
@@ -1344,8 +1340,8 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
WARN_ON(!i915_mmio_reg_valid(reg_ack));
d->wake_count = 0;
- d->reg_set = dev_priv->regs + i915_mmio_reg_offset(reg_set);
- d->reg_ack = dev_priv->regs + i915_mmio_reg_offset(reg_ack);
+ d->reg_set = i915->regs + i915_mmio_reg_offset(reg_set);
+ d->reg_ack = i915->regs + i915_mmio_reg_offset(reg_ack);
d->id = domain_id;
@@ -1370,7 +1366,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
fw_domain_reset(d);
}
-static void fw_domain_fini(struct drm_i915_private *dev_priv,
+static void fw_domain_fini(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id)
{
struct intel_uncore_forcewake_domain *d;
@@ -1378,74 +1374,76 @@ static void fw_domain_fini(struct drm_i915_private *dev_priv,
if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
return;
- d = &dev_priv->uncore.fw_domain[domain_id];
+ d = &uncore->fw_domain[domain_id];
WARN_ON(d->wake_count);
WARN_ON(hrtimer_cancel(&d->timer));
memset(d, 0, sizeof(*d));
- dev_priv->uncore.fw_domains &= ~BIT(domain_id);
+ uncore->fw_domains &= ~BIT(domain_id);
}
-static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
+static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
{
- if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
+ if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
return;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(i915) >= 11) {
int i;
- dev_priv->uncore.funcs.force_wake_get =
+ uncore->funcs.force_wake_get =
fw_domains_get_with_fallback;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ uncore->funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
FORCEWAKE_ACK_RENDER_GEN9);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
+ fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
FORCEWAKE_BLITTER_GEN9,
FORCEWAKE_ACK_BLITTER_GEN9);
for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(dev_priv, _VCS(i)))
+ if (!HAS_ENGINE(i915, _VCS(i)))
continue;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
+ fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
FORCEWAKE_MEDIA_VDBOX_GEN11(i),
FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
}
for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(dev_priv, _VECS(i)))
+ if (!HAS_ENGINE(i915, _VECS(i)))
continue;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
+ fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
FORCEWAKE_MEDIA_VEBOX_GEN11(i),
FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
}
- } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
- dev_priv->uncore.funcs.force_wake_get =
+ } else if (IS_GEN_RANGE(i915, 9, 10)) {
+ uncore->funcs.force_wake_get =
fw_domains_get_with_fallback;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ uncore->funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
FORCEWAKE_ACK_RENDER_GEN9);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
+ fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
FORCEWAKE_BLITTER_GEN9,
FORCEWAKE_ACK_BLITTER_GEN9);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
+ fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ uncore->funcs.force_wake_get = fw_domains_get;
+ uncore->funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
+ fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
- } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- dev_priv->uncore.funcs.force_wake_get =
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ uncore->funcs.force_wake_get =
fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ uncore->funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
- } else if (IS_IVYBRIDGE(dev_priv)) {
+ } else if (IS_IVYBRIDGE(i915)) {
u32 ecobus;
/* IVB configs may use multi-threaded forcewake */
@@ -1457,9 +1455,9 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
* (correctly) interpreted by the test below as MT
* forcewake being disabled.
*/
- dev_priv->uncore.funcs.force_wake_get =
+ uncore->funcs.force_wake_get =
fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+ uncore->funcs.force_wake_put = fw_domains_put;
/* We need to init first for ECOBUS access and then
* determine later if we want to reinit, in case of MT access is
@@ -1468,41 +1466,41 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
* before the ecobus check.
*/
- __raw_i915_write32(dev_priv, FORCEWAKE, 0);
- __raw_posting_read(dev_priv, ECOBUS);
+ __raw_i915_write32(i915, FORCEWAKE, 0);
+ __raw_posting_read(i915, ECOBUS);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
- spin_lock_irq(&dev_priv->uncore.lock);
- fw_domains_get_with_thread_status(&dev_priv->uncore, FORCEWAKE_RENDER);
- ecobus = __raw_i915_read32(dev_priv, ECOBUS);
- fw_domains_put(&dev_priv->uncore, FORCEWAKE_RENDER);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ spin_lock_irq(&uncore->lock);
+ fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
+ ecobus = __raw_i915_read32(i915, ECOBUS);
+ fw_domains_put(uncore, FORCEWAKE_RENDER);
+ spin_unlock_irq(&uncore->lock);
if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
DRM_INFO("when using vblank-synced partial screen updates.\n");
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE, FORCEWAKE_ACK);
}
- } else if (IS_GEN(dev_priv, 6)) {
- dev_priv->uncore.funcs.force_wake_get =
+ } else if (IS_GEN(i915, 6)) {
+ uncore->funcs.force_wake_get =
fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ uncore->funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE, FORCEWAKE_ACK);
}
/* All future platforms are expected to require complex power gating */
- WARN_ON(dev_priv->uncore.fw_domains == 0);
+ WARN_ON(uncore->fw_domains == 0);
}
-#define ASSIGN_FW_DOMAINS_TABLE(d) \
+#define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
{ \
- dev_priv->uncore.fw_domains_table = \
+ (uncore)->fw_domains_table = \
(struct intel_forcewake_range *)(d); \
- dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
+ (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
}
static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
@@ -1538,55 +1536,56 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
-void intel_uncore_init(struct drm_i915_private *dev_priv)
+void intel_uncore_init(struct intel_uncore *uncore)
{
- i915_check_vgpu(dev_priv);
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
- intel_uncore_edram_detect(dev_priv);
- intel_uncore_fw_domains_init(dev_priv);
- __intel_uncore_early_sanitize(dev_priv, 0);
+ i915_check_vgpu(i915);
- dev_priv->uncore.unclaimed_mmio_check = 1;
- dev_priv->uncore.pmic_bus_access_nb.notifier_call =
- i915_pmic_bus_access_notifier;
+ intel_uncore_edram_detect(i915);
+ intel_uncore_fw_domains_init(uncore);
+ __intel_uncore_early_sanitize(uncore, 0);
- if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
- } else if (IS_GEN(dev_priv, 5)) {
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
- } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
+ uncore->unclaimed_mmio_check = 1;
+ uncore->pmic_bus_access_nb.notifier_call =
+ i915_pmic_bus_access_notifier;
- if (IS_VALLEYVIEW(dev_priv)) {
- ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
+ if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
+ } else if (IS_GEN(i915, 5)) {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+ } else if (IS_GEN_RANGE(i915, 6, 7)) {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
+
+ if (IS_VALLEYVIEW(i915)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else {
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
}
- } else if (IS_GEN(dev_priv, 8)) {
- if (IS_CHERRYVIEW(dev_priv)) {
- ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
+ } else if (IS_GEN(i915, 8)) {
+ if (IS_CHERRYVIEW(i915)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else {
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
}
- } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
- ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
+ } else if (IS_GEN_RANGE(i915, 9, 10)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else {
- ASSIGN_FW_DOMAINS_TABLE(__gen11_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen11_fwtable);
- ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen11_fwtable);
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
}
- iosf_mbi_register_pmic_bus_access_notifier(
- &dev_priv->uncore.pmic_bus_access_nb);
+ iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
}
/*
@@ -1594,44 +1593,46 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
* the forcewake domains. Prune them, to make sure they only reference existing
* engines.
*/
-void intel_uncore_prune(struct drm_i915_private *dev_priv)
+void intel_uncore_prune(struct intel_uncore *uncore)
{
- if (INTEL_GEN(dev_priv) >= 11) {
- enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
+ if (INTEL_GEN(i915) >= 11) {
+ enum forcewake_domains fw_domains = uncore->fw_domains;
enum forcewake_domain_id domain_id;
int i;
for (i = 0; i < I915_MAX_VCS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
- if (HAS_ENGINE(dev_priv, _VCS(i)))
+ if (HAS_ENGINE(i915, _VCS(i)))
continue;
if (fw_domains & BIT(domain_id))
- fw_domain_fini(dev_priv, domain_id);
+ fw_domain_fini(uncore, domain_id);
}
for (i = 0; i < I915_MAX_VECS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
- if (HAS_ENGINE(dev_priv, _VECS(i)))
+ if (HAS_ENGINE(i915, _VECS(i)))
continue;
if (fw_domains & BIT(domain_id))
- fw_domain_fini(dev_priv, domain_id);
+ fw_domain_fini(uncore, domain_id);
}
}
}
-void intel_uncore_fini(struct drm_i915_private *dev_priv)
+void intel_uncore_fini(struct intel_uncore *uncore)
{
/* Paranoia: make sure we have disabled everything before we exit. */
- intel_uncore_sanitize(dev_priv);
+ intel_uncore_sanitize(uncore_to_i915(uncore));
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
- &dev_priv->uncore.pmic_bus_access_nb);
- intel_uncore_forcewake_reset(&dev_priv->uncore);
+ &uncore->pmic_bus_access_nb);
+ intel_uncore_forcewake_reset(uncore);
iosf_mbi_punit_release();
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b9010184a780..b1b596c81451 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -142,14 +142,14 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
}
void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
-void intel_uncore_init(struct drm_i915_private *dev_priv);
-void intel_uncore_prune(struct drm_i915_private *dev_priv);
+void intel_uncore_init(struct intel_uncore *uncore);
+void intel_uncore_prune(struct intel_uncore *uncore);
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
-void intel_uncore_fini(struct drm_i915_private *dev_priv);
-void intel_uncore_suspend(struct drm_i915_private *dev_priv);
-void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
-void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
+void intel_uncore_fini(struct intel_uncore *uncore);
+void intel_uncore_suspend(struct intel_uncore *uncore);
+void intel_uncore_resume_early(struct intel_uncore *uncore);
+void intel_uncore_runtime_resume(struct intel_uncore *uncore);
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
void assert_forcewakes_inactive(struct intel_uncore *uncore);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 54cfb611c0aa..60bbf8b4df40 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -182,7 +182,7 @@ struct drm_i915_private *mock_gem_device(void)
I915_GTT_PAGE_SIZE_64K |
I915_GTT_PAGE_SIZE_2M;
- mock_uncore_init(i915);
+ mock_uncore_init(&i915->uncore);
i915_gem_init__mm(i915);
init_waitqueue_head(&i915->gpu_error.wait_queue);
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index 8ef14c7e5e38..c3896c1fd551 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -39,8 +39,8 @@ __nop_read(16)
__nop_read(32)
__nop_read(64)
-void mock_uncore_init(struct drm_i915_private *i915)
+void mock_uncore_init(struct intel_uncore *uncore)
{
- ASSIGN_WRITE_MMIO_VFUNCS(i915, nop);
- ASSIGN_READ_MMIO_VFUNCS(i915, nop);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, nop);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, nop);
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.h b/drivers/gpu/drm/i915/selftests/mock_uncore.h
index d79aa3ca4d51..dacb36b5ffcd 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.h
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.h
@@ -25,6 +25,6 @@
#ifndef __MOCK_UNCORE_H
#define __MOCK_UNCORE_H
-void mock_uncore_init(struct drm_i915_private *i915);
+void mock_uncore_init(struct intel_uncore *uncore);
#endif /* !__MOCK_UNCORE_H */
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 05/10] drm/i915: make find_fw_domain work on intel_uncore
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 04/10] drm/i915: make more uncore function work on intel_uncore Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 06/10] drm/i915: reduce the dev_priv->uncore dance in uncore.c Daniele Ceraolo Spurio
` (9 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Remove unneeded usage of dev_priv from 1 extra function.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d58f96ea774c..62ee4bc6b7a6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -835,13 +835,13 @@ static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
})
static enum forcewake_domains
-find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
+find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
entry = BSEARCH(offset,
- dev_priv->uncore.fw_domains_table,
- dev_priv->uncore.fw_domains_table_entries,
+ uncore->fw_domains_table,
+ uncore->fw_domains_table_entries,
fw_range_cmp);
if (!entry)
@@ -853,11 +853,11 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
* translate it here to the list of available domains.
*/
if (entry->domains == FORCEWAKE_ALL)
- return dev_priv->uncore.fw_domains;
+ return uncore->fw_domains;
- WARN(entry->domains & ~dev_priv->uncore.fw_domains,
+ WARN(entry->domains & ~uncore->fw_domains,
"Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
- entry->domains & ~dev_priv->uncore.fw_domains, offset);
+ entry->domains & ~uncore->fw_domains, offset);
return entry->domains;
}
@@ -885,7 +885,7 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -893,7 +893,7 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -979,7 +979,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -987,7 +987,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 06/10] drm/i915: reduce the dev_priv->uncore dance in uncore.c
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 05/10] drm/i915: make find_fw_domain " Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure Daniele Ceraolo Spurio
` (8 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Use a local variable where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 79 ++++++++++++++++-------------
1 file changed, 43 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 62ee4bc6b7a6..bb9a10cc6904 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -313,6 +313,7 @@ static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 n;
/* On VLV, FIFO will be shared by both SW and HW.
@@ -320,7 +321,7 @@ static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv))
n = fifo_free_entries(dev_priv);
else
- n = dev_priv->uncore.fifo_count;
+ n = uncore->fifo_count;
if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
@@ -331,7 +332,7 @@ static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
}
}
- dev_priv->uncore.fifo_count = n - 1;
+ uncore->fifo_count = n - 1;
}
static enum hrtimer_restart
@@ -795,7 +796,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
#define GEN11_NEEDS_FORCE_WAKE(reg) \
((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
-#define __gen6_reg_read_fw_domains(offset) \
+#define __gen6_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
if (NEEDS_FORCE_WAKE(offset)) \
@@ -881,19 +882,19 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_read_fw_domains(offset) \
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-#define __gen11_fwtable_reg_read_fw_domains(offset) \
+#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
@@ -945,7 +946,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
-#define __gen8_reg_write_fw_domains(offset) \
+#define __gen8_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
@@ -975,19 +976,19 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_write_fw_domains(offset) \
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-#define __gen11_fwtable_reg_write_fw_domains(offset) \
+#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
@@ -1137,16 +1138,17 @@ __gen2_read(64)
#undef GEN2_READ_HEADER
#define GEN6_READ_HEADER(x) \
+ struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
u##x val = 0; \
assert_rpm_wakelock_held(dev_priv); \
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
+ spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(dev_priv, reg, true, true)
#define GEN6_READ_FOOTER \
unclaimed_reg_debug(dev_priv, reg, true, false); \
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+ spin_unlock_irqrestore(&uncore->lock, irqflags); \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
@@ -1183,9 +1185,9 @@ static u##x \
func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_READ_HEADER(x); \
- fw_engine = __##func##_reg_read_fw_domains(offset); \
+ fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
if (fw_engine) \
- __force_wake_auto(&dev_priv->uncore, fw_engine); \
+ __force_wake_auto(uncore, fw_engine); \
val = __raw_i915_read##x(dev_priv, reg); \
GEN6_READ_FOOTER; \
}
@@ -1249,16 +1251,17 @@ __gen2_write(32)
#undef GEN2_WRITE_HEADER
#define GEN6_WRITE_HEADER \
+ struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(dev_priv); \
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
+ spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(dev_priv, reg, false, true)
#define GEN6_WRITE_FOOTER \
unclaimed_reg_debug(dev_priv, reg, false, false); \
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
+ spin_unlock_irqrestore(&uncore->lock, irqflags)
#define __gen6_write(x) \
static void \
@@ -1275,9 +1278,9 @@ static void \
func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_WRITE_HEADER; \
- fw_engine = __##func##_reg_write_fw_domains(offset); \
+ fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
if (fw_engine) \
- __force_wake_auto(&dev_priv->uncore, fw_engine); \
+ __force_wake_auto(uncore, fw_engine); \
__raw_i915_write##x(dev_priv, reg, val); \
GEN6_WRITE_FOOTER; \
}
@@ -1781,6 +1784,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
unsigned int slow_timeout_ms,
u32 *out_value)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned fw =
intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
u32 reg_value;
@@ -1788,15 +1792,15 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
might_sleep_if(slow_timeout_ms);
- spin_lock_irq(&dev_priv->uncore.lock);
- intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw);
ret = __intel_wait_for_register_fw(dev_priv,
reg, mask, value,
fast_timeout_us, 0, ®_value);
- intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ intel_uncore_forcewake_put__locked(uncore, fw);
+ spin_unlock_irq(&uncore->lock);
if (ret && slow_timeout_ms)
ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
@@ -1820,11 +1824,12 @@ bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
bool
intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
- spin_lock_irq(&dev_priv->uncore.lock);
+ spin_lock_irq(&uncore->lock);
- if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
+ if (unlikely(uncore->unclaimed_mmio_check <= 0))
goto out;
if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
@@ -1834,12 +1839,12 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
"Please use i915.mmio_debug=N for more information.\n");
i915_modparams.mmio_debug++;
}
- dev_priv->uncore.unclaimed_mmio_check--;
+ uncore->unclaimed_mmio_check--;
ret = true;
}
out:
- spin_unlock_irq(&dev_priv->uncore.lock);
+ spin_unlock_irq(&uncore->lock);
return ret;
}
@@ -1848,21 +1853,22 @@ static enum forcewake_domains
intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
i915_reg_t reg)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 offset = i915_mmio_reg_offset(reg);
enum forcewake_domains fw_domains;
if (INTEL_GEN(dev_priv) >= 11) {
- fw_domains = __gen11_fwtable_reg_read_fw_domains(offset);
+ fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
} else if (HAS_FWTABLE(dev_priv)) {
- fw_domains = __fwtable_reg_read_fw_domains(offset);
+ fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
} else if (INTEL_GEN(dev_priv) >= 6) {
- fw_domains = __gen6_reg_read_fw_domains(offset);
+ fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
} else {
WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
fw_domains = 0;
}
- WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
+ WARN_ON(fw_domains & ~uncore->fw_domains);
return fw_domains;
}
@@ -1871,15 +1877,16 @@ static enum forcewake_domains
intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
i915_reg_t reg)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 offset = i915_mmio_reg_offset(reg);
enum forcewake_domains fw_domains;
if (INTEL_GEN(dev_priv) >= 11) {
- fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
+ fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
} else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
- fw_domains = __fwtable_reg_write_fw_domains(offset);
+ fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
} else if (IS_GEN(dev_priv, 8)) {
- fw_domains = __gen8_reg_write_fw_domains(offset);
+ fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
fw_domains = FORCEWAKE_RENDER;
} else {
@@ -1887,7 +1894,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
fw_domains = 0;
}
- WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
+ WARN_ON(fw_domains & ~uncore->fw_domains);
return fw_domains;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 06/10] drm/i915: reduce the dev_priv->uncore dance in uncore.c Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-20 0:03 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 08/10] drm/i915: make raw access function work on uncore Daniele Ceraolo Spurio
` (7 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This will allow futher simplifications in the uncore handling.
v2: move register access setup under uncore (Chris)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 49 +++-----------------------
drivers/gpu/drm/i915/i915_drv.h | 6 ++--
drivers/gpu/drm/i915/i915_irq.c | 22 ++++++------
drivers/gpu/drm/i915/intel_lrc.c | 6 ++--
drivers/gpu/drm/i915/intel_uncore.c | 54 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_uncore.h | 4 ++-
6 files changed, 74 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5561488ecfcd..ca41a3da1918 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -930,46 +930,6 @@ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
i915_engines_cleanup(dev_priv);
}
-static int i915_mmio_setup(struct drm_i915_private *dev_priv)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
- int mmio_bar;
- int mmio_size;
-
- mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
- /*
- * Before gen4, the registers and the GTT are behind different BARs.
- * However, from gen4 onwards, the registers and the GTT are shared
- * in the same BAR, so we want to restrict this ioremap from
- * clobbering the GTT which we want ioremap_wc instead. Fortunately,
- * the register BAR remains the same size for all the earlier
- * generations up to Ironlake.
- */
- if (INTEL_GEN(dev_priv) < 5)
- mmio_size = 512 * 1024;
- else
- mmio_size = 2 * 1024 * 1024;
- dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
- if (dev_priv->regs == NULL) {
- DRM_ERROR("failed to map registers\n");
-
- return -EIO;
- }
-
- /* Try to make sure MCHBAR is enabled before poking at it */
- intel_setup_mchbar(dev_priv);
-
- return 0;
-}
-
-static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
-
- intel_teardown_mchbar(dev_priv);
- pci_iounmap(pdev, dev_priv->regs);
-}
-
/**
* i915_driver_init_mmio - setup device MMIO
* @dev_priv: device private
@@ -989,11 +949,12 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
if (i915_get_bridge_dev(dev_priv))
return -EIO;
- ret = i915_mmio_setup(dev_priv);
+ ret = intel_uncore_init(&dev_priv->uncore);
if (ret < 0)
goto err_bridge;
- intel_uncore_init(&dev_priv->uncore);
+ /* Try to make sure MCHBAR is enabled before poking at it */
+ intel_setup_mchbar(dev_priv);
intel_device_info_init_mmio(dev_priv);
@@ -1010,8 +971,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
return 0;
err_uncore:
+ intel_teardown_mchbar(dev_priv);
intel_uncore_fini(&dev_priv->uncore);
- i915_mmio_cleanup(dev_priv);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1024,8 +985,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
+ intel_teardown_mchbar(dev_priv);
intel_uncore_fini(&dev_priv->uncore);
- i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64f0e13d6912..58a77b01fe71 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1505,8 +1505,6 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
- void __iomem *regs;
-
struct intel_uncore uncore;
struct i915_virtual_gpu vgpu;
@@ -3488,14 +3486,14 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
i915_reg_t reg) \
{ \
- return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
+ return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
}
#define __raw_write(x, s) \
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
i915_reg_t reg, uint##x##_t val) \
{ \
- write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
+ write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
}
__raw_read(8, b)
__raw_read(16, w)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 82d487189a34..1686c0c973f7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -268,7 +268,7 @@ static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
const unsigned int bank,
const unsigned int bit)
{
- void __iomem * const regs = i915->regs;
+ void __iomem * const regs = i915->uncore.regs;
u32 dw;
lockdep_assert_held(&i915->irq_lock);
@@ -1471,7 +1471,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
static void gen8_gt_irq_ack(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
- void __iomem * const regs = i915->regs;
+ void __iomem * const regs = i915->uncore.regs;
#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
GEN8_GT_BCS_IRQ | \
@@ -2868,7 +2868,7 @@ static inline void gen8_master_intr_enable(void __iomem * const regs)
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
struct drm_i915_private *dev_priv = to_i915(arg);
- void __iomem * const regs = dev_priv->regs;
+ void __iomem * const regs = dev_priv->uncore.regs;
u32 master_ctl;
u32 gt_iir[4];
@@ -2902,7 +2902,7 @@ static u32
gen11_gt_engine_identity(struct drm_i915_private * const i915,
const unsigned int bank, const unsigned int bit)
{
- void __iomem * const regs = i915->regs;
+ void __iomem * const regs = i915->uncore.regs;
u32 timeout_ts;
u32 ident;
@@ -2986,7 +2986,7 @@ static void
gen11_gt_bank_handler(struct drm_i915_private * const i915,
const unsigned int bank)
{
- void __iomem * const regs = i915->regs;
+ void __iomem * const regs = i915->uncore.regs;
unsigned long intr_dw;
unsigned int bit;
@@ -3029,7 +3029,7 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
static u32
gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
{
- void __iomem * const regs = dev_priv->regs;
+ void __iomem * const regs = dev_priv->uncore.regs;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -3070,7 +3070,7 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = to_i915(arg);
- void __iomem * const regs = i915->regs;
+ void __iomem * const regs = i915->uncore.regs;
u32 master_ctl;
u32 gu_misc_iir;
@@ -3351,7 +3351,7 @@ static void gen8_irq_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
int pipe;
- gen8_master_intr_disable(dev_priv->regs);
+ gen8_master_intr_disable(dev_priv->uncore.regs);
gen8_gt_irq_reset(dev_priv);
@@ -3393,7 +3393,7 @@ static void gen11_irq_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
- gen11_master_intr_disable(dev_priv->regs);
+ gen11_master_intr_disable(dev_priv->uncore.regs);
gen11_gt_irq_reset(dev_priv);
@@ -3998,7 +3998,7 @@ static int gen8_irq_postinstall(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev);
- gen8_master_intr_enable(dev_priv->regs);
+ gen8_master_intr_enable(dev_priv->uncore.regs);
return 0;
}
@@ -4060,7 +4060,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
- gen11_master_intr_enable(dev_priv->regs);
+ gen11_master_intr_enable(dev_priv->uncore.regs);
POSTING_READ(GEN11_GFX_MSTR_IRQ);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e54e0064b2d6..721ae4b166d5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2413,12 +2413,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
intel_engine_init_workarounds(engine);
if (HAS_LOGICAL_RING_ELSQ(i915)) {
- execlists->submit_reg = i915->regs +
+ execlists->submit_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
- execlists->ctrl_reg = i915->regs +
+ execlists->ctrl_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
} else {
- execlists->submit_reg = i915->regs +
+ execlists->submit_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_ELSP(engine));
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index bb9a10cc6904..e60856069971 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1330,7 +1330,6 @@ static void fw_domain_init(struct intel_uncore *uncore,
i915_reg_t reg_ack)
{
struct intel_uncore_forcewake_domain *d;
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
return;
@@ -1343,8 +1342,8 @@ static void fw_domain_init(struct intel_uncore *uncore,
WARN_ON(!i915_mmio_reg_valid(reg_ack));
d->wake_count = 0;
- d->reg_set = i915->regs + i915_mmio_reg_offset(reg_set);
- d->reg_ack = i915->regs + i915_mmio_reg_offset(reg_ack);
+ d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
+ d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
d->id = domain_id;
@@ -1539,9 +1538,53 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
-void intel_uncore_init(struct intel_uncore *uncore)
+static int uncore_mmio_setup(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore_to_i915(uncore);
+ struct pci_dev *pdev = i915->drm.pdev;
+ int mmio_bar;
+ int mmio_size;
+
+ mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
+ /*
+ * Before gen4, the registers and the GTT are behind different BARs.
+ * However, from gen4 onwards, the registers and the GTT are shared
+ * in the same BAR, so we want to restrict this ioremap from
+ * clobbering the GTT which we want ioremap_wc instead. Fortunately,
+ * the register BAR remains the same size for all the earlier
+ * generations up to Ironlake.
+ */
+ if (INTEL_GEN(i915) < 5)
+ mmio_size = 512 * 1024;
+ else
+ mmio_size = 2 * 1024 * 1024;
+ uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
+ if (uncore->regs == NULL) {
+ DRM_ERROR("failed to map registers\n");
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void uncore_mmio_cleanup(struct intel_uncore *uncore)
+{
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+ struct pci_dev *pdev = i915->drm.pdev;
+
+ pci_iounmap(pdev, uncore->regs);
+}
+
+
+int intel_uncore_init(struct intel_uncore *uncore)
+{
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+ int ret;
+
+ ret = uncore_mmio_setup(uncore);
+ if (ret)
+ return ret;
i915_check_vgpu(i915);
@@ -1589,6 +1632,8 @@ void intel_uncore_init(struct intel_uncore *uncore)
}
iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
+
+ return 0;
}
/*
@@ -1637,6 +1682,7 @@ void intel_uncore_fini(struct intel_uncore *uncore)
&uncore->pmic_bus_access_nb);
intel_uncore_forcewake_reset(uncore);
iosf_mbi_punit_release();
+ uncore_mmio_cleanup(uncore);
}
static const struct reg_whitelist {
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b1b596c81451..d345e5ab04a5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -93,6 +93,8 @@ struct intel_forcewake_range {
};
struct intel_uncore {
+ void __iomem *regs;
+
spinlock_t lock; /** lock is also taken in irq contexts. */
const struct intel_forcewake_range *fw_domains_table;
@@ -142,7 +144,7 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
}
void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
-void intel_uncore_init(struct intel_uncore *uncore);
+int intel_uncore_init(struct intel_uncore *uncore);
void intel_uncore_prune(struct intel_uncore *uncore);
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 08/10] drm/i915: make raw access function work on uncore
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 09/10] drm/i915: add uncore flags Daniele Ceraolo Spurio
` (6 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This allows us to ditch i915 in some more places.
v2: use local var in check_vgpu (Paulo)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++---
drivers/gpu/drm/i915/i915_vgpu.c | 7 ++-
drivers/gpu/drm/i915/intel_uncore.c | 90 +++++++++++++++--------------
3 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 58a77b01fe71..fb77420370e4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3483,17 +3483,17 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
+static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
i915_reg_t reg) \
{ \
- return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
+ return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
}
#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
+static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
i915_reg_t reg, uint##x##_t val) \
{ \
- write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
+ write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
}
__raw_read(8, b)
__raw_read(16, w)
@@ -3534,9 +3534,9 @@ __raw_write(64, q)
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
-#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
-#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
-#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
+#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
+#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
/* "Broadcast RGB" property */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 3b2d83f704e3..3d0b493e4200 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -60,22 +60,23 @@
*/
void i915_check_vgpu(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u64 magic;
u16 version_major;
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
- magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
+ magic = __raw_i915_read64(uncore, vgtif_reg(magic));
if (magic != VGT_MAGIC)
return;
- version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
+ version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
if (version_major < VGT_VERSION_MAJOR) {
DRM_INFO("VGT interface version mismatch!\n");
return;
}
- dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
+ dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
dev_priv->vgpu.active = true;
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e60856069971..1816eeae3ba9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -31,7 +31,7 @@
#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define GT_FIFO_TIMEOUT_MS 10
-#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
+#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
static const char * const forcewake_domain_names[] = {
"render",
@@ -275,23 +275,23 @@ fw_domains_reset(struct intel_uncore *uncore,
fw_domain_reset(d);
}
-static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
+static inline u32 gt_thread_status(struct intel_uncore *uncore)
{
u32 val;
- val = __raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG);
+ val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
return val;
}
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
+static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
{
/*
* w/a for a sporadic read returning 0 by waiting for the GT
* thread to wake up.
*/
- WARN_ONCE(wait_for_atomic_us(gt_thread_status(dev_priv) == 0, 5000),
+ WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
"GT thread status wait timed out\n");
}
@@ -301,30 +301,29 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
fw_domains_get(uncore, fw_domains);
/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
- __gen6_gt_wait_for_thread_c0(uncore_to_i915(uncore));
+ __gen6_gt_wait_for_thread_c0(uncore);
}
-static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
+static inline u32 fifo_free_entries(struct intel_uncore *uncore)
{
- u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
+ u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
return count & GT_FIFO_FREE_ENTRIES_MASK;
}
-static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
+static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
u32 n;
/* On VLV, FIFO will be shared by both SW and HW.
* So, we need to read the FREE_ENTRIES everytime */
- if (IS_VALLEYVIEW(dev_priv))
- n = fifo_free_entries(dev_priv);
+ if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
+ n = fifo_free_entries(uncore);
else
n = uncore->fifo_count;
if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
- if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
+ if (wait_for_atomic((n = fifo_free_entries(uncore)) >
GT_FIFO_NUM_RESERVED_ENTRIES,
GT_FIFO_TIMEOUT_MS)) {
DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
@@ -452,7 +451,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv) ||
INTEL_GEN(dev_priv) >= 9) {
- dev_priv->edram_cap = __raw_i915_read32(dev_priv,
+ dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
HSW_EDRAM_CAP);
/* NB: We can't write IDICR yet because we do not have gt funcs
@@ -467,43 +466,43 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
}
static bool
-fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
+fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
u32 dbg;
- dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
+ dbg = __raw_i915_read32(uncore, FPGA_DBG);
if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
return false;
- __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ __raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
return true;
}
static bool
-vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
+vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
u32 cer;
- cer = __raw_i915_read32(dev_priv, CLAIM_ER);
+ cer = __raw_i915_read32(uncore, CLAIM_ER);
if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
return false;
- __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
+ __raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
return true;
}
static bool
-gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
+gen6_check_for_fifo_debug(struct intel_uncore *uncore)
{
u32 fifodbg;
- fifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
+ fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
if (unlikely(fifodbg)) {
DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
- __raw_i915_write32(dev_priv, GTFIFODBG, fifodbg);
+ __raw_i915_write32(uncore, GTFIFODBG, fifodbg);
}
return fifodbg;
@@ -512,16 +511,17 @@ gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
static bool
check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
- ret |= fpga_check_for_unclaimed_mmio(dev_priv);
+ ret |= fpga_check_for_unclaimed_mmio(uncore);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- ret |= vlv_check_for_unclaimed_mmio(dev_priv);
+ ret |= vlv_check_for_unclaimed_mmio(uncore);
if (IS_GEN_RANGE(dev_priv, 6, 7))
- ret |= gen6_check_for_fifo_debug(dev_priv);
+ ret |= gen6_check_for_fifo_debug(uncore);
return ret;
}
@@ -537,8 +537,8 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
/* WaDisableShadowRegForCpd:chv */
if (IS_CHERRYVIEW(i915)) {
- __raw_i915_write32(i915, GTFIFOCTL,
- __raw_i915_read32(i915, GTFIFOCTL) |
+ __raw_i915_write32(uncore, GTFIFOCTL,
+ __raw_i915_read32(uncore, GTFIFOCTL) |
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
GT_FIFO_CTL_RC6_POLICY_STALL);
}
@@ -550,7 +550,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
uncore->funcs.force_wake_get(uncore, restore_forcewake);
if (IS_GEN_RANGE(i915, 6, 7))
- uncore->fifo_count = fifo_free_entries(i915);
+ uncore->fifo_count = fifo_free_entries(uncore);
spin_unlock_irq(&uncore->lock);
}
iosf_mbi_punit_release();
@@ -1063,12 +1063,12 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
};
static void
-ilk_dummy_write(struct drm_i915_private *dev_priv)
+ilk_dummy_write(struct intel_uncore *uncore)
{
/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
* the chip from rc6 before touching it for real. MI_MODE is masked,
* hence harmless to write 0 into. */
- __raw_i915_write32(dev_priv, MI_MODE, 0);
+ __raw_i915_write32(uncore, MI_MODE, 0);
}
static void
@@ -1098,6 +1098,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
}
#define GEN2_READ_HEADER(x) \
+ struct intel_uncore *uncore = &dev_priv->uncore; \
u##x val = 0; \
assert_rpm_wakelock_held(dev_priv);
@@ -1109,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
static u##x \
gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
- val = __raw_i915_read##x(dev_priv, reg); \
+ val = __raw_i915_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
}
@@ -1117,8 +1118,8 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
static u##x \
gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
- ilk_dummy_write(dev_priv); \
- val = __raw_i915_read##x(dev_priv, reg); \
+ ilk_dummy_write(uncore); \
+ val = __raw_i915_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
}
@@ -1188,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
if (fw_engine) \
__force_wake_auto(uncore, fw_engine); \
- val = __raw_i915_read##x(dev_priv, reg); \
+ val = __raw_i915_read##x(uncore, reg); \
GEN6_READ_FOOTER; \
}
#define __gen6_read(x) __gen_read(gen6, x)
@@ -1215,6 +1216,7 @@ __gen6_read(64)
#undef GEN6_READ_HEADER
#define GEN2_WRITE_HEADER \
+ struct intel_uncore *uncore = &dev_priv->uncore; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(dev_priv); \
@@ -1224,7 +1226,7 @@ __gen6_read(64)
static void \
gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
- __raw_i915_write##x(dev_priv, reg, val); \
+ __raw_i915_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
}
@@ -1232,8 +1234,8 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
static void \
gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
- ilk_dummy_write(dev_priv); \
- __raw_i915_write##x(dev_priv, reg, val); \
+ ilk_dummy_write(uncore); \
+ __raw_i915_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
}
@@ -1268,8 +1270,8 @@ static void \
gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
GEN6_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE(offset)) \
- __gen6_gt_wait_for_fifo(dev_priv); \
- __raw_i915_write##x(dev_priv, reg, val); \
+ __gen6_gt_wait_for_fifo(uncore); \
+ __raw_i915_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
@@ -1281,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
if (fw_engine) \
__force_wake_auto(uncore, fw_engine); \
- __raw_i915_write##x(dev_priv, reg, val); \
+ __raw_i915_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
#define __gen8_write(x) __gen_write(gen8, x)
@@ -1468,15 +1470,15 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
* before the ecobus check.
*/
- __raw_i915_write32(i915, FORCEWAKE, 0);
- __raw_posting_read(i915, ECOBUS);
+ __raw_i915_write32(uncore, FORCEWAKE, 0);
+ __raw_posting_read(uncore, ECOBUS);
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
spin_lock_irq(&uncore->lock);
fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
- ecobus = __raw_i915_read32(i915, ECOBUS);
+ ecobus = __raw_i915_read32(uncore, ECOBUS);
fw_domains_put(uncore, FORCEWAKE_RENDER);
spin_unlock_irq(&uncore->lock);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 09/10] drm/i915: add uncore flags
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 08/10] drm/i915: make raw access function work on uncore Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-20 0:56 ` Paulo Zanoni
2019-03-21 0:26 ` Chris Wilson
2019-03-19 18:35 ` [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
` (5 subsequent siblings)
14 siblings, 2 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Save some uncore properties to avoid having to jump back to
dev_priv every time
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 82 ++++++++++---------
drivers/gpu/drm/i915/intel_uncore.h | 10 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 ++--
6 files changed, 65 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ca41a3da1918..c609bcac8577 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2849,7 +2849,7 @@ static int intel_runtime_suspend(struct device *kdev)
enable_rpm_wakeref_asserts(dev_priv);
intel_runtime_pm_cleanup(dev_priv);
- if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
+ if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
dev_priv->runtime_pm.suspended = true;
@@ -2903,7 +2903,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_opregion_notify_adapter(dev_priv, PCI_D0);
dev_priv->runtime_pm.suspended = false;
- if (intel_uncore_unclaimed_mmio(dev_priv))
+ if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
if (INTEL_GEN(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d4fcad136120..cfe379e938e6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13517,7 +13517,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
* so enable debugging for the next modeset - and hope we catch
* the culprit.
*/
- intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
}
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 57ed49dc19c4..125662c64934 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -270,7 +270,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
* periodically arm the mmio checker to see if we are triggering
* any invalid access.
*/
- intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
for_each_engine(engine, dev_priv, id) {
struct hangcheck hc;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1816eeae3ba9..26b28afb4500 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -509,18 +509,17 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
}
static bool
-check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
+check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
- if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
+ if (uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED)
ret |= fpga_check_for_unclaimed_mmio(uncore);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ if (uncore->flags & UNCORE_HAS_DBG_UNCLAIMED)
ret |= vlv_check_for_unclaimed_mmio(uncore);
- if (IS_GEN_RANGE(dev_priv, 6, 7))
+ if (uncore->flags & UNCORE_HAS_FIFO)
ret |= gen6_check_for_fifo_debug(uncore);
return ret;
@@ -529,14 +528,12 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
unsigned int restore_forcewake)
{
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
-
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(i915))
+ if (check_for_unclaimed_mmio(uncore))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
- if (IS_CHERRYVIEW(i915)) {
+ if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
__raw_i915_write32(uncore, GTFIFOCTL,
__raw_i915_read32(uncore, GTFIFOCTL) |
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
@@ -549,7 +546,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
spin_lock_irq(&uncore->lock);
uncore->funcs.force_wake_get(uncore, restore_forcewake);
- if (IS_GEN_RANGE(i915, 6, 7))
+ if (uncore->flags & UNCORE_HAS_FIFO)
uncore->fifo_count = fifo_free_entries(uncore);
spin_unlock_irq(&uncore->lock);
}
@@ -668,12 +665,10 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
*/
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
-
spin_lock_irq(&uncore->lock);
if (!--uncore->user_forcewake.count) {
- if (intel_uncore_unclaimed_mmio(i915))
- dev_info(i915->drm.dev,
+ if (intel_uncore_unclaimed_mmio(uncore))
+ dev_info(uncore_to_i915(uncore)->drm.dev,
"Invalid mmio detected during user access\n");
uncore->unclaimed_mmio_check =
@@ -1072,12 +1067,12 @@ ilk_dummy_write(struct intel_uncore *uncore)
}
static void
-__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+__unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
const bool before)
{
- if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
+ if (WARN(check_for_unclaimed_mmio(uncore) && !before,
"Unclaimed %s register 0x%x\n",
read ? "read from" : "write to",
i915_mmio_reg_offset(reg)))
@@ -1086,7 +1081,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
}
static inline void
-unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
const bool before)
@@ -1094,7 +1089,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
if (likely(!i915_modparams.mmio_debug))
return;
- __unclaimed_reg_debug(dev_priv, reg, read, before);
+ __unclaimed_reg_debug(uncore, reg, read, before);
}
#define GEN2_READ_HEADER(x) \
@@ -1145,10 +1140,10 @@ __gen2_read(64)
u##x val = 0; \
assert_rpm_wakelock_held(dev_priv); \
spin_lock_irqsave(&uncore->lock, irqflags); \
- unclaimed_reg_debug(dev_priv, reg, true, true)
+ unclaimed_reg_debug(uncore, reg, true, true)
#define GEN6_READ_FOOTER \
- unclaimed_reg_debug(dev_priv, reg, true, false); \
+ unclaimed_reg_debug(uncore, reg, true, false); \
spin_unlock_irqrestore(&uncore->lock, irqflags); \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
@@ -1259,10 +1254,10 @@ __gen2_write(32)
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(dev_priv); \
spin_lock_irqsave(&uncore->lock, irqflags); \
- unclaimed_reg_debug(dev_priv, reg, false, true)
+ unclaimed_reg_debug(uncore, reg, false, true)
#define GEN6_WRITE_FOOTER \
- unclaimed_reg_debug(dev_priv, reg, false, false); \
+ unclaimed_reg_debug(uncore, reg, false, false); \
spin_unlock_irqrestore(&uncore->lock, irqflags)
#define __gen6_write(x) \
@@ -1391,7 +1386,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore_to_i915(uncore);
- if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
+ if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
return;
if (INTEL_GEN(i915) >= 11) {
@@ -1590,6 +1585,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
i915_check_vgpu(i915);
+ if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
+ uncore->flags |= UNCORE_HAS_FORCEWAKE;
+
intel_uncore_edram_detect(i915);
intel_uncore_fw_domains_init(uncore);
__intel_uncore_early_sanitize(uncore, 0);
@@ -1598,12 +1596,14 @@ int intel_uncore_init(struct intel_uncore *uncore)
uncore->pmic_bus_access_nb.notifier_call =
i915_pmic_bus_access_notifier;
- if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
- } else if (IS_GEN(i915, 5)) {
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+ if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
+ if (IS_GEN(i915, 5)) {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+ } else {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
+ }
} else if (IS_GEN_RANGE(i915, 6, 7)) {
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
@@ -1633,6 +1633,15 @@ int intel_uncore_init(struct intel_uncore *uncore)
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
}
+ if (HAS_FPGA_DBG_UNCLAIMED(i915))
+ uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
+
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
+
+ if (IS_GEN_RANGE(i915, 6, 7))
+ uncore->flags |= UNCORE_HAS_FIFO;
+
iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
return 0;
@@ -1864,15 +1873,14 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
return ret;
}
-bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
+bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
{
- return check_for_unclaimed_mmio(dev_priv);
+ return check_for_unclaimed_mmio(uncore);
}
bool
-intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
+intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
spin_lock_irq(&uncore->lock);
@@ -1880,7 +1888,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
if (unlikely(uncore->unclaimed_mmio_check <= 0))
goto out;
- if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
+ if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
if (!i915_modparams.mmio_debug) {
DRM_DEBUG("Unclaimed register detected, "
"enabling oneshot unclaimed register reporting. "
@@ -1912,7 +1920,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
} else if (INTEL_GEN(dev_priv) >= 6) {
fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
} else {
- WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+ WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
fw_domains = 0;
}
@@ -1938,7 +1946,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
fw_domains = FORCEWAKE_RENDER;
} else {
- WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+ WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
fw_domains = 0;
}
@@ -1969,7 +1977,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
WARN_ON(!op);
- if (intel_vgpu_active(dev_priv))
+ if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
return 0;
if (op & FW_REG_READ)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index d345e5ab04a5..6df6586bb603 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -127,6 +127,12 @@ struct intel_uncore {
} user_forcewake;
int unclaimed_mmio_check;
+
+ u32 flags;
+#define UNCORE_HAS_FORCEWAKE BIT(0)
+#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
+#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
+#define UNCORE_HAS_FIFO BIT(3)
};
/* Iterate over initialised fw domains */
@@ -146,8 +152,8 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
int intel_uncore_init(struct intel_uncore *uncore);
void intel_uncore_prune(struct intel_uncore *uncore);
-bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
-bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
+bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
+bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_fini(struct intel_uncore *uncore);
void intel_uncore_suspend(struct intel_uncore *uncore);
void intel_uncore_resume_early(struct intel_uncore *uncore);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 69aa260b479d..d2c6a03fb29c 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -122,6 +122,7 @@ int intel_uncore_mock_selftests(void)
static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_priv)
{
#define FW_RANGE 0x40000
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long *valid;
u32 offset;
int err;
@@ -142,31 +143,31 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
if (!valid)
return -ENOMEM;
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- check_for_unclaimed_mmio(dev_priv);
+ check_for_unclaimed_mmio(uncore);
for (offset = 0; offset < FW_RANGE; offset += 4) {
i915_reg_t reg = { offset };
(void)I915_READ_FW(reg);
- if (!check_for_unclaimed_mmio(dev_priv))
+ if (!check_for_unclaimed_mmio(uncore))
set_bit(offset, valid);
}
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
err = 0;
for_each_set_bit(offset, valid, FW_RANGE) {
i915_reg_t reg = { offset };
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(&dev_priv->uncore);
+ intel_uncore_forcewake_reset(uncore);
iosf_mbi_punit_release();
- check_for_unclaimed_mmio(dev_priv);
+ check_for_unclaimed_mmio(uncore);
(void)I915_READ(reg);
- if (check_for_unclaimed_mmio(dev_priv)) {
+ if (check_for_unclaimed_mmio(uncore)) {
pr_err("Unclaimed mmio read to register 0x%04x\n",
offset);
err = -EINVAL;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 09/10] drm/i915: add uncore flags Daniele Ceraolo Spurio
@ 2019-03-19 18:35 ` Daniele Ceraolo Spurio
2019-03-19 19:11 ` Chris Wilson
2019-03-19 18:55 ` ✗ Fi.CI.CHECKPATCH: warning for Compartmentalize uncore code (rev2) Patchwork
` (4 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-19 18:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The full read/write ops can now work on the intel_uncore struct
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 25 ++++++++++---------
drivers/gpu/drm/i915/intel_uncore.c | 26 +++++++++-----------
drivers/gpu/drm/i915/intel_uncore.h | 14 +++++------
drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +--
4 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fb77420370e4..9fe66b62787c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3440,18 +3440,21 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}
-#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
-#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
+#define __I915_REG_OP(op, reg, ...) \
+ dev_priv->uncore.funcs.mmio_##op(&dev_priv->uncore, (reg), ##__VA_ARGS__)
-#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
-#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
-#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
-#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
+#define I915_READ8(reg) __I915_REG_OP(readb, (reg), true)
+#define I915_WRITE8(reg, val) __I915_REG_OP(writeb, (reg), (val), true)
-#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
-#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
-#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
-#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
+#define I915_READ16(reg) __I915_REG_OP(readw, (reg), true)
+#define I915_WRITE16(reg, val) __I915_REG_OP(writew, (reg), (val), true)
+#define I915_READ16_NOTRACE(reg) __I915_REG_OP(readw, (reg), false)
+#define I915_WRITE16_NOTRACE(reg, val) __I915_REG_OP(writew, (reg), (val), false)
+
+#define I915_READ(reg) __I915_REG_OP(readl, (reg), true)
+#define I915_WRITE(reg, val) __I915_REG_OP(writel, (reg), (val), true)
+#define I915_READ_NOTRACE(reg) __I915_REG_OP(readl, (reg), false)
+#define I915_WRITE_NOTRACE(reg, val) __I915_REG_OP(writel, (reg), (val), false)
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
* will be implemented using 2 32-bit writes in an arbitrary order with
@@ -3467,7 +3470,7 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
*
* You have been warned.
*/
-#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
+#define I915_READ64(reg) __I915_REG_OP(readq, (reg), true)
#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
u32 upper, lower, old_upper, loop = 0; \
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 26b28afb4500..155a06aaa5f5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1093,9 +1093,8 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
}
#define GEN2_READ_HEADER(x) \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u##x val = 0; \
- assert_rpm_wakelock_held(dev_priv);
+ assert_rpm_wakelock_held(uncore_to_i915(uncore));
#define GEN2_READ_FOOTER \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
@@ -1103,7 +1102,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
#define __gen2_read(x) \
static u##x \
-gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
val = __raw_i915_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
@@ -1111,7 +1110,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
#define __gen5_read(x) \
static u##x \
-gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
ilk_dummy_write(uncore); \
val = __raw_i915_read##x(uncore, reg); \
@@ -1134,11 +1133,10 @@ __gen2_read(64)
#undef GEN2_READ_HEADER
#define GEN6_READ_HEADER(x) \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
u##x val = 0; \
- assert_rpm_wakelock_held(dev_priv); \
+ assert_rpm_wakelock_held(uncore_to_i915(uncore)); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, true, true)
@@ -1178,7 +1176,7 @@ static inline void __force_wake_auto(struct intel_uncore *uncore,
#define __gen_read(func, x) \
static u##x \
-func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_READ_HEADER(x); \
fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
@@ -1211,15 +1209,14 @@ __gen6_read(64)
#undef GEN6_READ_HEADER
#define GEN2_WRITE_HEADER \
- struct intel_uncore *uncore = &dev_priv->uncore; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
- assert_rpm_wakelock_held(dev_priv); \
+ assert_rpm_wakelock_held(uncore_to_i915(uncore)); \
#define GEN2_WRITE_FOOTER
#define __gen2_write(x) \
static void \
-gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
__raw_i915_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
@@ -1227,7 +1224,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
#define __gen5_write(x) \
static void \
-gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
ilk_dummy_write(uncore); \
__raw_i915_write##x(uncore, reg, val); \
@@ -1248,11 +1245,10 @@ __gen2_write(32)
#undef GEN2_WRITE_HEADER
#define GEN6_WRITE_HEADER \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
- assert_rpm_wakelock_held(dev_priv); \
+ assert_rpm_wakelock_held(uncore_to_i915(uncore)); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, false, true)
@@ -1262,7 +1258,7 @@ __gen2_write(32)
#define __gen6_write(x) \
static void \
-gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN6_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE(offset)) \
__gen6_gt_wait_for_fifo(uncore); \
@@ -1272,7 +1268,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
#define __gen_write(func, x) \
static void \
-func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_WRITE_HEADER; \
fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 6df6586bb603..09dfea8d66e3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -68,20 +68,20 @@ struct intel_uncore_funcs {
void (*force_wake_put)(struct intel_uncore *uncore,
enum forcewake_domains domains);
- u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
+ u8 (*mmio_readb)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
+ u16 (*mmio_readw)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
+ u32 (*mmio_readl)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
+ u64 (*mmio_readq)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- void (*mmio_writeb)(struct drm_i915_private *dev_priv,
+ void (*mmio_writeb)(struct intel_uncore *uncore,
i915_reg_t r, u8 val, bool trace);
- void (*mmio_writew)(struct drm_i915_private *dev_priv,
+ void (*mmio_writew)(struct intel_uncore *uncore,
i915_reg_t r, u16 val, bool trace);
- void (*mmio_writel)(struct drm_i915_private *dev_priv,
+ void (*mmio_writel)(struct intel_uncore *uncore,
i915_reg_t r, u32 val, bool trace);
};
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index c3896c1fd551..ff8999c63a12 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -26,14 +26,14 @@
#define __nop_write(x) \
static void \
-nop_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { }
+nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
__nop_write(8)
__nop_write(16)
__nop_write(32)
#define __nop_read(x) \
static u##x \
-nop_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { return 0; }
+nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
__nop_read(8)
__nop_read(16)
__nop_read(32)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Compartmentalize uncore code (rev2)
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2019-03-19 18:35 ` [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
@ 2019-03-19 18:55 ` Patchwork
2019-03-19 18:59 ` [PATCH v2 00/10] Compartmentalize uncore code Chris Wilson
` (3 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-03-19 18:55 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Compartmentalize uncore code (rev2)
URL : https://patchwork.freedesktop.org/series/57962/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7eeb92fc30c1 drm/i915: always use masks on FW regs
e02d7bd59410 drm/i915: use intel_uncore in fw get/put internal paths
-:600: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tmp__' - possible side-effects?
#600: FILE: drivers/gpu/drm/i915/intel_uncore.h:131:
+#define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
for (tmp__ = (mask__); \
+ tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
-:607: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore__' - possible side-effects?
#607: FILE: drivers/gpu/drm/i915/intel_uncore.h:135:
+#define for_each_fw_domain(domain__, uncore__, tmp__) \
+ for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
total: 0 errors, 0 warnings, 2 checks, 567 lines checked
1e88e185db7a drm/i915: use intel_uncore for all forcewake get/put
-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/gvt/scheduler.c:992:
+ intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
-:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#67: FILE: drivers/gpu/drm/i915/gvt/scheduler.c:1014:
+ intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
total: 0 errors, 0 warnings, 2 checks, 786 lines checked
a42b363d5c3f drm/i915: make more uncore function work on intel_uncore
-:191: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible side-effects?
#191: FILE: drivers/gpu/drm/i915/intel_uncore.c:1308:
+#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
do { \
+ (uncore)->funcs.mmio_writeb = x##_write8; \
+ (uncore)->funcs.mmio_writew = x##_write16; \
+ (uncore)->funcs.mmio_writel = x##_write32; \
} while (0)
-:202: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible side-effects?
#202: FILE: drivers/gpu/drm/i915/intel_uncore.c:1315:
+#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
do { \
+ (uncore)->funcs.mmio_readb = x##_read8; \
+ (uncore)->funcs.mmio_readw = x##_read16; \
+ (uncore)->funcs.mmio_readl = x##_read32; \
+ (uncore)->funcs.mmio_readq = x##_read64; \
} while (0)
-:414: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible side-effects?
#414: FILE: drivers/gpu/drm/i915/intel_uncore.c:1499:
+#define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
{ \
+ (uncore)->fw_domains_table = \
(struct intel_forcewake_range *)(d); \
+ (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
}
-:414: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'd' - possible side-effects?
#414: FILE: drivers/gpu/drm/i915/intel_uncore.c:1499:
+#define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
{ \
+ (uncore)->fw_domains_table = \
(struct intel_forcewake_range *)(d); \
+ (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
}
total: 0 errors, 0 warnings, 4 checks, 583 lines checked
603b151c1f69 drm/i915: make find_fw_domain work on intel_uncore
13ecd23c0131 drm/i915: reduce the dev_priv->uncore dance in uncore.c
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/intel_uncore.c:885:
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/intel_uncore.c:893:
+#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#80: FILE: drivers/gpu/drm/i915/intel_uncore.c:949:
+#define __gen8_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
-:89: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#89: FILE: drivers/gpu/drm/i915/intel_uncore.c:979:
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-:99: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#99: FILE: drivers/gpu/drm/i915/intel_uncore.c:987:
+#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
total: 0 errors, 0 warnings, 5 checks, 252 lines checked
4c09e145044b drm/i915: move regs pointer inside the uncore structure
-:302: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!uncore->regs"
#302: FILE: drivers/gpu/drm/i915/intel_uncore.c:1562:
+ if (uncore->regs == NULL) {
-:319: CHECK:LINE_SPACING: Please don't use multiple blank lines
#319: FILE: drivers/gpu/drm/i915/intel_uncore.c:1579:
+
+
total: 0 errors, 0 warnings, 2 checks, 307 lines checked
dfd2240515bb drm/i915: make raw access function work on uncore
-:93: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#93: FILE: drivers/gpu/drm/i915/intel_uncore.c:34:
+#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
-:159: ERROR:ASSIGN_IN_IF: do not use assignment in if condition
#159: FILE: drivers/gpu/drm/i915/intel_uncore.c:326:
+ if (wait_for_atomic((n = fifo_free_entries(uncore)) >
total: 2 errors, 0 warnings, 0 checks, 337 lines checked
09373cd53e61 drm/i915: add uncore flags
d3c15f3a0fd8 drm/i915: switch uncore mmio funcs to use intel_uncore
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 00/10] Compartmentalize uncore code
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2019-03-19 18:55 ` ✗ Fi.CI.CHECKPATCH: warning for Compartmentalize uncore code (rev2) Patchwork
@ 2019-03-19 18:59 ` Chris Wilson
2019-03-20 11:34 ` Chris Wilson
2019-03-19 19:00 ` ✗ Fi.CI.SPARSE: warning for Compartmentalize uncore code (rev2) Patchwork
` (2 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2019-03-19 18:59 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:33)
> Compared to v1 [1], there is a new patch for further simplification of
> low-level fw get/put by always using the bitmasks since the upper bits
> of the fw reg are reserved on gen6 and I couldn't find any reason
> writing them wouldn't work in the git history.
> I put together a small selftest to trybot this on snb [2], if people
> think it is worth adding it to the tree I can clean it up and send it
> for review.
>
> Apart from the above, addresses the review comments, the only
> non-trivial one being moving the mmio setup under uncore.
>
> [1] https://patchwork.freedesktop.org/series/57962/
> [2] https://patchwork.freedesktop.org/patch/292852/?series=58159&rev=1
I thought so. You just need to verify that the fw count is zero at the
start of the loop and then flush the hrtimer instead of the imprecise
usleep().
Certainly worth checking out whether we can abuse the reserved bits :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Compartmentalize uncore code (rev2)
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (11 preceding siblings ...)
2019-03-19 18:59 ` [PATCH v2 00/10] Compartmentalize uncore code Chris Wilson
@ 2019-03-19 19:00 ` Patchwork
2019-03-19 19:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-20 5:53 ` ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-03-19 19:00 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Compartmentalize uncore code (rev2)
URL : https://patchwork.freedesktop.org/series/57962/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: always use masks on FW regs
Okay!
Commit: drm/i915: use intel_uncore in fw get/put internal paths
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3563:16: warning: expression using sizeof(void)
Commit: drm/i915: use intel_uncore for all forcewake get/put
Okay!
Commit: drm/i915: make more uncore function work on intel_uncore
Okay!
Commit: drm/i915: make find_fw_domain work on intel_uncore
Okay!
Commit: drm/i915: reduce the dev_priv->uncore dance in uncore.c
Okay!
Commit: drm/i915: move regs pointer inside the uncore structure
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3563:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3561:16: warning: expression using sizeof(void)
Commit: drm/i915: make raw access function work on uncore
Okay!
Commit: drm/i915: add uncore flags
Okay!
Commit: drm/i915: switch uncore mmio funcs to use intel_uncore
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3561:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3564:16: warning: expression using sizeof(void)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore
2019-03-19 18:35 ` [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
@ 2019-03-19 19:11 ` Chris Wilson
0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-03-19 19:11 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:43)
> The full read/write ops can now work on the intel_uncore struct
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 25 ++++++++++---------
> drivers/gpu/drm/i915/intel_uncore.c | 26 +++++++++-----------
> drivers/gpu/drm/i915/intel_uncore.h | 14 +++++------
> drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +--
> 4 files changed, 34 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fb77420370e4..9fe66b62787c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3440,18 +3440,21 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
> }
>
> -#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
> -#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
> +#define __I915_REG_OP(op, reg, ...) \
> + dev_priv->uncore.funcs.mmio_##op(&dev_priv->uncore, (reg), ##__VA_ARGS__)
No uncore?
No inlines for intel_uncore_read8..32?
While you are here, give us the tools to transition away from the
implicit parameter of I915_READ() into something sustainable.
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for Compartmentalize uncore code (rev2)
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (12 preceding siblings ...)
2019-03-19 19:00 ` ✗ Fi.CI.SPARSE: warning for Compartmentalize uncore code (rev2) Patchwork
@ 2019-03-19 19:39 ` Patchwork
2019-03-20 5:53 ` ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-03-19 19:39 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Compartmentalize uncore code (rev2)
URL : https://patchwork.freedesktop.org/series/57962/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5774 -> Patchwork_12517
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57962/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_12517 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@gtt-bsd2:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_contexts:
- fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (41 -> 40)
------------------------------
Additional (6): fi-bxt-j4205 fi-gdg-551 fi-icl-u3 fi-skl-lmem fi-byt-n2820 fi-byt-clapper
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-ctg-p8600 fi-icl-y fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5774 -> Patchwork_12517
CI_DRM_5774: eb58badf383e72d54ba48b8570ce7169c1419f6a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4890: 6d4d6949a099521003de252358601d22115e27ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12517: d3c15f3a0fd87cfeb9868ed308abe1e28bc969e1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d3c15f3a0fd8 drm/i915: switch uncore mmio funcs to use intel_uncore
09373cd53e61 drm/i915: add uncore flags
dfd2240515bb drm/i915: make raw access function work on uncore
4c09e145044b drm/i915: move regs pointer inside the uncore structure
13ecd23c0131 drm/i915: reduce the dev_priv->uncore dance in uncore.c
603b151c1f69 drm/i915: make find_fw_domain work on intel_uncore
a42b363d5c3f drm/i915: make more uncore function work on intel_uncore
1e88e185db7a drm/i915: use intel_uncore for all forcewake get/put
e02d7bd59410 drm/i915: use intel_uncore in fw get/put internal paths
7eeb92fc30c1 drm/i915: always use masks on FW regs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12517/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 01/10] drm/i915: always use masks on FW regs
2019-03-19 18:35 ` [PATCH v2 01/10] drm/i915: always use masks on FW regs Daniele Ceraolo Spurio
@ 2019-03-19 23:14 ` Paulo Zanoni
0 siblings, 0 replies; 24+ messages in thread
From: Paulo Zanoni @ 2019-03-19 23:14 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> Upper bits are reserved on gen6, so no issue if we write them. Note that
> we're already doing this in the non-MT case of IVB, which uses the same
> register.
If, and only if, you can guarantee that writing ones to the reserved
bits in gen6 is not an issue, then everything else looks correct:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
I also couldn't find information about WaRsClearFWBitsAtReset. Don't we
need to update its tags to include the most recent platforms and
ivb/hsw/vlv?
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 44 +++++++++++------------------
> drivers/gpu/drm/i915/intel_uncore.h | 4 ---
> 2 files changed, 16 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 7129eebc333b..b4cea3cf3915 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -59,18 +59,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
> }
>
> #define fw_ack(d) readl((d)->reg_ack)
> -#define fw_set(d, val) writel((val), (d)->reg_set)
> +#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
> +#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
>
> static inline void
> -fw_domain_reset(const struct intel_uncore *uncore,
> - const struct intel_uncore_forcewake_domain *d)
> +fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
> {
> /*
> * We don't really know if the powerwell for the forcewake domain we are
> * trying to reset here does exist at this point (engines could be fused
> * off in ICL+), so no waiting for acks
> */
> - fw_set(d, uncore->fw_reset);
> + /* WaRsClearFWBitsAtReset:bdw,skl */
> + fw_clear(d, 0xffff);
> }
>
> static inline void
> @@ -146,14 +147,14 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
> do {
> wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
>
> - fw_set(d, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
> + fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
> /* Give gt some time to relax before the polling frenzy */
> udelay(10 * pass);
> wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
>
> ack_detected = (fw_ack(d) & ack_bit) == value;
>
> - fw_set(d, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
> + fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
> } while (!ack_detected && pass++ < 10);
>
> DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
> @@ -176,10 +177,9 @@ fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
> }
>
> static inline void
> -fw_domain_get(const struct intel_uncore *uncore,
> - const struct intel_uncore_forcewake_domain *d)
> +fw_domain_get(const struct intel_uncore_forcewake_domain *d)
> {
> - fw_set(d, uncore->fw_set);
> + fw_set(d, FORCEWAKE_KERNEL);
> }
>
> static inline void
> @@ -201,10 +201,9 @@ fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
> }
>
> static inline void
> -fw_domain_put(const struct intel_uncore *uncore,
> - const struct intel_uncore_forcewake_domain *d)
> +fw_domain_put(const struct intel_uncore_forcewake_domain *d)
> {
> - fw_set(d, uncore->fw_clear);
> + fw_clear(d, FORCEWAKE_KERNEL);
> }
>
> static void
> @@ -218,7 +217,7 @@ fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
> fw_domain_wait_ack_clear(d);
> - fw_domain_get(uncore, d);
> + fw_domain_get(d);
> }
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp)
> @@ -239,7 +238,7 @@ fw_domains_get_with_fallback(struct drm_i915_private *i915,
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
> fw_domain_wait_ack_clear_fallback(d);
> - fw_domain_get(uncore, d);
> + fw_domain_get(d);
> }
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp)
> @@ -258,7 +257,7 @@ fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
> GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp)
> - fw_domain_put(uncore, d);
> + fw_domain_put(d);
>
> uncore->fw_domains_active &= ~fw_domains;
> }
> @@ -277,7 +276,7 @@ fw_domains_reset(struct drm_i915_private *i915,
> GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
>
> for_each_fw_domain_masked(d, fw_domains, i915, tmp)
> - fw_domain_reset(uncore, d);
> + fw_domain_reset(d);
> }
>
> static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
> @@ -1371,7 +1370,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>
> uncore->fw_domains |= BIT(domain_id);
>
> - fw_domain_reset(uncore, d);
> + fw_domain_reset(d);
> }
>
> static void fw_domain_fini(struct drm_i915_private *dev_priv,
> @@ -1396,17 +1395,6 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
> return;
>
> - if (IS_GEN(dev_priv, 6)) {
> - dev_priv->uncore.fw_reset = 0;
> - dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
> - dev_priv->uncore.fw_clear = 0;
> - } else {
> - /* WaRsClearFWBitsAtReset:bdw,skl */
> - dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
> - dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
> - dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
> - }
> -
> if (INTEL_GEN(dev_priv) >= 11) {
> int i;
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index b0a95469babf..579a7f6b8445 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -106,10 +106,6 @@ struct intel_uncore {
> enum forcewake_domains fw_domains_active;
> enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
>
> - u32 fw_set;
> - u32 fw_clear;
> - u32 fw_reset;
> -
> struct intel_uncore_forcewake_domain {
> enum forcewake_domain_id id;
> enum forcewake_domains mask;
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put
2019-03-19 18:35 ` [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put Daniele Ceraolo Spurio
@ 2019-03-19 23:48 ` Paulo Zanoni
0 siblings, 0 replies; 24+ messages in thread
From: Paulo Zanoni @ 2019-03-19 23:48 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> Now that the internal code all works on intel_uncore, flip the
> external-facing interface.
>
> v2: fix GVT.
Could maybe use some local intel_uncore variables in functions, but
let's go with the current color:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
> drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++---
> drivers/gpu/drm/i915/i915_gem.c | 20 +++----
> drivers/gpu/drm/i915/i915_perf.c | 6 +--
> drivers/gpu/drm/i915/i915_reset.c | 12 ++---
> drivers/gpu/drm/i915/intel_display.c | 4 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/intel_guc.c | 8 +--
> drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
> drivers/gpu/drm/i915/intel_huc_fw.c | 4 +-
> drivers/gpu/drm/i915/intel_pm.c | 52 +++++++++----------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +--
> drivers/gpu/drm/i915/intel_uncore.c | 52 ++++++++-----------
> drivers/gpu/drm/i915/intel_uncore.h | 12 ++---
> drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 4 +-
> 17 files changed, 105 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index f64c76dd11d4..a00a807a1d55 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -356,7 +356,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
> if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
> fw |= FORCEWAKE_RENDER;
>
> - intel_uncore_forcewake_get(dev_priv, fw);
> + intel_uncore_forcewake_get(&dev_priv->uncore, fw);
>
> I915_WRITE_FW(reg, 0x1);
>
> @@ -365,7 +365,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
> else
> vgpu_vreg_t(vgpu, reg) = 0;
>
> - intel_uncore_forcewake_put(dev_priv, fw);
> + intel_uncore_forcewake_put(&dev_priv->uncore, fw);
>
> gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
> }
> @@ -552,9 +552,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
> * performace for batch mmio read/write, so we need
> * handle forcewake mannually.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> switch_mmio(pre, next, ring_id);
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 7550e09939ae..3faf2438b9bc 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -988,7 +988,7 @@ static int workload_thread(void *priv)
> workload->ring_id, workload);
>
> if (need_force_wake)
> - intel_uncore_forcewake_get(gvt->dev_priv,
> + intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
> FORCEWAKE_ALL);
>
> ret = dispatch_workload(workload);
> @@ -1010,7 +1010,7 @@ static int workload_thread(void *priv)
> complete_current_workload(gvt, ring_id);
>
> if (need_force_wake)
> - intel_uncore_forcewake_put(gvt->dev_priv,
> + intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
> FORCEWAKE_ALL);
>
> intel_runtime_pm_put_unchecked(gvt->dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a52b7cf1525d..0dd8b3fa7fb9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1094,7 +1094,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> }
>
> /* RPSTAT1 is in the GT power well */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> reqf = I915_READ(GEN6_RPNSWREQ);
> if (INTEL_GEN(dev_priv) >= 9)
> @@ -1122,7 +1122,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> cagf = intel_gpu_freq(dev_priv,
> intel_get_cagf(dev_priv, rpstat));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> @@ -2060,12 +2060,12 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
> u32 rpup, rpupei;
> u32 rpdown, rpdownei;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
> rps_power_to_str(rps->power.mode));
> @@ -4251,7 +4251,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
> return 0;
>
> file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);
> - intel_uncore_forcewake_user_get(i915);
> + intel_uncore_forcewake_user_get(&i915->uncore);
>
> return 0;
> }
> @@ -4263,7 +4263,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
> if (INTEL_GEN(i915) < 6)
> return 0;
>
> - intel_uncore_forcewake_user_put(i915);
> + intel_uncore_forcewake_user_put(&i915->uncore);
> intel_runtime_pm_put(i915,
> (intel_wakeref_t)(uintptr_t)file->private_data);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b7086c8d4726..49dcf7ec6287 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4318,7 +4318,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> GEM_TRACE("\n");
>
> wakeref = intel_runtime_pm_get(i915);
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>
> /*
> * As we have just resumed the machine and woken the device up from
> @@ -4339,7 +4339,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> */
> intel_engines_sanitize(i915, false);
>
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(i915, wakeref);
>
> mutex_lock(&i915->drm.struct_mutex);
> @@ -4438,7 +4438,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> WARN_ON(i915->gt.awake);
>
> mutex_lock(&i915->drm.struct_mutex);
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>
> i915_gem_restore_gtt_mappings(i915);
> i915_gem_restore_fences(i915);
> @@ -4460,7 +4460,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> goto err_wedged;
>
> out_unlock:
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> mutex_unlock(&i915->drm.struct_mutex);
> return;
>
> @@ -4549,7 +4549,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> dev_priv->gt.last_init_time = ktime_get();
>
> /* Double layer security blanket, see i915_gem_init() */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> @@ -4604,14 +4604,14 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> if (ret)
> goto cleanup_uc;
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return 0;
>
> cleanup_uc:
> intel_uc_fini_hw(dev_priv);
> out:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -4815,7 +4815,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> * just magically go away.
> */
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> ret = i915_gem_init_ggtt(dev_priv);
> if (ret) {
> @@ -4877,7 +4877,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> goto err_init_hw;
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> return 0;
> @@ -4912,7 +4912,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> i915_gem_fini_scratch(dev_priv);
> err_ggtt:
> err_unlock:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> err_uc_misc:
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 9b0292a38865..e0fcb982a14f 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1364,7 +1364,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
>
> free_oa_buffer(dev_priv);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(dev_priv, stream->wakeref);
>
> if (stream->ctx)
> @@ -2093,7 +2093,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> * references will effectively disable RC6.
> */
> stream->wakeref = intel_runtime_pm_get(dev_priv);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> ret = alloc_oa_buffer(dev_priv);
> if (ret)
> @@ -2127,7 +2127,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> err_oa_buf_alloc:
> put_oa_config(dev_priv, stream->oa_config);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(dev_priv, stream->wakeref);
>
> err_config:
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index fb86d5ca5d8b..0aea19cefe4a 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -569,7 +569,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
> * If the power well sleeps during the reset, the reset
> * request may be dropped and never completes (causing -EIO).
> */
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
> for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
> /*
> * We stop engines, otherwise we might get failed reset and a
> @@ -593,7 +593,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
> ret = reset(i915, engine_mask, retry);
> preempt_enable();
> }
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -622,9 +622,9 @@ int intel_reset_guc(struct drm_i915_private *i915)
>
> GEM_BUG_ON(!HAS_GUC(i915));
>
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
> ret = gen6_hw_domain_reset(i915, guc_domain);
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -642,7 +642,7 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
> * written to the powercontext is undefined and so we may lose
> * GPU state upon resume, i.e. fail to restart after a reset.
> */
> - intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&engine->i915->uncore, FORCEWAKE_ALL);
> engine->reset.prepare(engine);
> }
>
> @@ -713,7 +713,7 @@ static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
> static void reset_finish_engine(struct intel_engine_cs *engine)
> {
> engine->reset.finish(engine);
> - intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&engine->i915->uncore, FORCEWAKE_ALL);
> }
>
> struct i915_gpu_restart {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 61acbaf2af75..d4fcad136120 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9503,7 +9503,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> * Make sure we're not on PC8 state before disabling PC8, otherwise
> * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (val & LCPLL_POWER_DOWN_ALLOW) {
> val &= ~LCPLL_POWER_DOWN_ALLOW;
> @@ -9535,7 +9535,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> DRM_ERROR("Switching back to LCPLL failed\n");
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> intel_update_cdclk(dev_priv);
> intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 652c1b3ba190..588c640b5a57 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -919,7 +919,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> FW_REG_READ | FW_REG_WRITE);
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
>
> mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>
> @@ -937,7 +937,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>
> I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 8ecb47087457..a59448a56f55 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -369,14 +369,14 @@ void intel_guc_init_params(struct intel_guc *guc)
> * they are power context saved so it's ok to release forcewake
> * when we are done here and take it again at xfer time.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
>
> I915_WRITE(SOFT_SCRATCH(0), 0);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
> }
>
> int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
> @@ -414,7 +414,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
> *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
>
> mutex_lock(&guc->send_mutex);
> - intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
> + intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);
>
> for (i = 0; i < len; i++)
> I915_WRITE(guc_send_reg(guc, i), action[i]);
> @@ -454,7 +454,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
> ret = INTEL_GUC_MSG_TO_DATA(status);
>
> out:
> - intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
> + intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);
> mutex_unlock(&guc->send_mutex);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 13ff7003c6be..792a551450c7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -241,7 +241,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
>
> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> guc_prepare_xfer(guc);
>
> @@ -254,7 +254,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
>
> ret = guc_xfer_ucode(guc, vma);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
> index 7d7bfc7f7ca7..92799b8502f5 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -112,7 +112,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
>
> GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Set the source address for the uCode */
> offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
> @@ -140,7 +140,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
> /* Disable the bits once DMA is over */
> I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d73b13ca57a0..007529dd161c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6737,9 +6737,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> * punit into committing the voltage change) as that takes a lot less
> * power than the render powerwell.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
> err = valleyview_set_rps(dev_priv, val);
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
>
> if (err)
> DRM_ERROR("Failed to set RPS for idle\n");
> @@ -6889,11 +6889,11 @@ static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
> {
> /* We're doing forcewake before Disabling RC6,
> * This what the BIOS expects when going into suspend */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> I915_WRITE(GEN6_RC_CONTROL, 0);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
> @@ -7052,7 +7052,7 @@ static void reset_rps(struct drm_i915_private *dev_priv,
> /* See the Gen9_GT_PM_Programming_Guide doc for the below */
> static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> {
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Program defaults and thresholds for RPS */
> if (IS_GEN(dev_priv, 9))
> @@ -7070,7 +7070,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7084,7 +7084,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 2a: Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7161,7 +7161,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN9_PG_ENABLE,
> GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7174,7 +7174,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 2a: Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7195,14 +7195,14 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
> GEN7_RC_CTL_TO_MODE |
> GEN6_RC_CTL_RC6_ENABLE);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen8_enable_rps(struct drm_i915_private *dev_priv)
> {
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 1 Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RPNSWREQ,
> @@ -7235,7 +7235,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7255,7 +7255,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GTFIFODBG, gtfifodbg);
> }
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* disable the counters and set deterministic thresholds */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7303,7 +7303,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> @@ -7314,7 +7314,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> * Perhaps there might be some value in exposing these to
> * userspace...
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Power down if completely idle for over 50ms */
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
> @@ -7322,7 +7322,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> @@ -7745,7 +7745,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1a & 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7777,14 +7777,14 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
> rc6_mode = GEN7_RC_CTL_TO_MODE;
> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 1: Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> @@ -7819,7 +7819,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, valleyview_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7837,7 +7837,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GTFIFODBG, gtfifodbg);
> }
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7862,14 +7862,14 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_RC_CONTROL,
> GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> @@ -7903,7 +7903,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, valleyview_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static unsigned long intel_pxfreq(u32 vidfreq)
> @@ -9955,7 +9955,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> - intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
>
> /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> @@ -9996,7 +9996,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
> spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
>
> return mul_u64_u32_div(time_hw, mul, div);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f26f5cc1584c..3641175baa72 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -644,7 +644,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> struct intel_ring *ring = engine->buffer;
> int ret = 0;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (!stop_ring(engine)) {
> /* G45 ring initialization often fails to reset head to zero */
> @@ -731,7 +731,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> /* Papering over lost _interrupts_ immediately following the restart */
> intel_engine_queue_breadcrumbs(engine);
> out:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -2079,7 +2079,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> {
> struct drm_i915_private *dev_priv = request->i915;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Every tail move must follow the sequence below */
>
> @@ -2109,7 +2109,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
> _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static int mi_flush_dw(struct i915_request *rq, u32 flags)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ebbb9af970dc..2e50697e72b4 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -610,7 +610,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
>
> /**
> * intel_uncore_forcewake_get - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * This function can be used get GT's forcewake domain references.
> @@ -621,16 +621,15 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
> * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
> * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
> */
> -void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long irqflags;
>
> if (!uncore->funcs.force_wake_get)
> return;
>
> - assert_rpm_wakelock_held(dev_priv);
> + assert_rpm_wakelock_held(uncore_to_i915(uncore));
>
> spin_lock_irqsave(&uncore->lock, irqflags);
> __intel_uncore_forcewake_get(uncore, fw_domains);
> @@ -639,19 +638,17 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
>
> /**
> * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> *
> * This function is a wrapper around intel_uncore_forcewake_get() to acquire
> * the GT powerwell and in the process disable our debugging for the
> * duration of userspace's bypass.
> */
> -void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
> +void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> spin_lock_irq(&uncore->lock);
> if (!uncore->user_forcewake.count++) {
> - intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
>
> /* Save and disable mmio debugging for the user bypass */
> uncore->user_forcewake.saved_mmio_check =
> @@ -667,19 +664,19 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
>
> /**
> * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> *
> * This function complements intel_uncore_forcewake_user_get() and releases
> * the GT powerwell taken on behalf of the userspace bypass.
> */
> -void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
> +void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> + struct drm_i915_private *i915 = uncore_to_i915(uncore);
>
> spin_lock_irq(&uncore->lock);
> if (!--uncore->user_forcewake.count) {
> - if (intel_uncore_unclaimed_mmio(dev_priv))
> - dev_info(dev_priv->drm.dev,
> + if (intel_uncore_unclaimed_mmio(i915))
> + dev_info(i915->drm.dev,
> "Invalid mmio detected during user access\n");
>
> uncore->unclaimed_mmio_check =
> @@ -687,24 +684,22 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
> i915_modparams.mmio_debug =
> uncore->user_forcewake.saved_mmio_debug;
>
> - intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
> }
> spin_unlock_irq(&uncore->lock);
> }
>
> /**
> * intel_uncore_forcewake_get__locked - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * See intel_uncore_forcewake_get(). This variant places the onus
> * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
> */
> -void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> lockdep_assert_held(&uncore->lock);
>
> if (!uncore->funcs.force_wake_get)
> @@ -736,16 +731,15 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
>
> /**
> * intel_uncore_forcewake_put - release a forcewake domain reference
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to put references
> *
> * This function drops the device-level forcewakes for specified
> * domains obtained by intel_uncore_forcewake_get().
> */
> -void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long irqflags;
>
> if (!uncore->funcs.force_wake_put)
> @@ -758,17 +752,15 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
>
> /**
> * intel_uncore_forcewake_put__locked - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * See intel_uncore_forcewake_put(). This variant places the onus
> * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
> */
> -void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> lockdep_assert_held(&uncore->lock);
>
> if (!uncore->funcs.force_wake_put)
> @@ -1535,11 +1527,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> * the access.
> */
> disable_rpm_wakeref_asserts(dev_priv);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> enable_rpm_wakeref_asserts(dev_priv);
> break;
> case MBI_PMIC_BUS_ACCESS_END:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> break;
> }
>
> @@ -1796,13 +1788,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> might_sleep_if(slow_timeout_ms);
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - intel_uncore_forcewake_get__locked(dev_priv, fw);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
>
> ret = __intel_wait_for_register_fw(dev_priv,
> reg, mask, value,
> fast_timeout_us, 0, ®_value);
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> if (ret && slow_timeout_ms)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 73b1bd9a391d..b9010184a780 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -163,20 +163,20 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
> #define FW_REG_READ (1)
> #define FW_REG_WRITE (2)
>
> -void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> -void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> /* Like above but the caller must manage the uncore.lock itself.
> * Must be used with I915_READ_FW and friends.
> */
> -void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> -void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
> enum forcewake_domains domains);
>
> -void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
> -void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
> +void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
> +void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
>
> int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> i915_reg_t reg,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 283e9a4ef3ca..e758bbf50617 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -927,7 +927,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> fw = wal_get_fw_for_rmw(dev_priv, wal);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> - intel_uncore_forcewake_get__locked(dev_priv, fw);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> u32 val = I915_READ_FW(wa->reg);
> @@ -938,7 +938,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> I915_WRITE_FW(wa->reg, val);
> }
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
> spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> }
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 1c15f8d146aa..69aa260b479d 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -142,7 +142,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
> if (!valid)
> return -ENOMEM;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> check_for_unclaimed_mmio(dev_priv);
> for (offset = 0; offset < FW_RANGE; offset += 4) {
> @@ -153,7 +153,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
> set_bit(offset, valid);
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> err = 0;
> for_each_set_bit(offset, valid, FW_RANGE) {
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure
2019-03-19 18:35 ` [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure Daniele Ceraolo Spurio
@ 2019-03-20 0:03 ` Paulo Zanoni
0 siblings, 0 replies; 24+ messages in thread
From: Paulo Zanoni @ 2019-03-20 0:03 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> This will allow futher simplifications in the uncore handling.
>
> v2: move register access setup under uncore (Chris)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 49 +++-----------------------
> drivers/gpu/drm/i915/i915_drv.h | 6 ++--
> drivers/gpu/drm/i915/i915_irq.c | 22 ++++++------
> drivers/gpu/drm/i915/intel_lrc.c | 6 ++--
> drivers/gpu/drm/i915/intel_uncore.c | 54 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_uncore.h | 4 ++-
> 6 files changed, 74 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5561488ecfcd..ca41a3da1918 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -930,46 +930,6 @@ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
> i915_engines_cleanup(dev_priv);
> }
>
> -static int i915_mmio_setup(struct drm_i915_private *dev_priv)
> -{
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> - int mmio_bar;
> - int mmio_size;
> -
> - mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
> - /*
> - * Before gen4, the registers and the GTT are behind different BARs.
> - * However, from gen4 onwards, the registers and the GTT are shared
> - * in the same BAR, so we want to restrict this ioremap from
> - * clobbering the GTT which we want ioremap_wc instead. Fortunately,
> - * the register BAR remains the same size for all the earlier
> - * generations up to Ironlake.
> - */
> - if (INTEL_GEN(dev_priv) < 5)
> - mmio_size = 512 * 1024;
> - else
> - mmio_size = 2 * 1024 * 1024;
> - dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> - if (dev_priv->regs == NULL) {
> - DRM_ERROR("failed to map registers\n");
> -
> - return -EIO;
> - }
> -
> - /* Try to make sure MCHBAR is enabled before poking at it */
> - intel_setup_mchbar(dev_priv);
> -
> - return 0;
> -}
> -
> -static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
> -{
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> -
> - intel_teardown_mchbar(dev_priv);
> - pci_iounmap(pdev, dev_priv->regs);
> -}
> -
> /**
> * i915_driver_init_mmio - setup device MMIO
> * @dev_priv: device private
> @@ -989,11 +949,12 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
> if (i915_get_bridge_dev(dev_priv))
> return -EIO;
>
> - ret = i915_mmio_setup(dev_priv);
> + ret = intel_uncore_init(&dev_priv->uncore);
> if (ret < 0)
> goto err_bridge;
>
> - intel_uncore_init(&dev_priv->uncore);
> + /* Try to make sure MCHBAR is enabled before poking at it */
> + intel_setup_mchbar(dev_priv);
>
> intel_device_info_init_mmio(dev_priv);
>
> @@ -1010,8 +971,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
> return 0;
>
> err_uncore:
> + intel_teardown_mchbar(dev_priv);
> intel_uncore_fini(&dev_priv->uncore);
> - i915_mmio_cleanup(dev_priv);
> err_bridge:
> pci_dev_put(dev_priv->bridge_dev);
>
> @@ -1024,8 +985,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
> */
> static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
> {
> + intel_teardown_mchbar(dev_priv);
> intel_uncore_fini(&dev_priv->uncore);
> - i915_mmio_cleanup(dev_priv);
> pci_dev_put(dev_priv->bridge_dev);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 64f0e13d6912..58a77b01fe71 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1505,8 +1505,6 @@ struct drm_i915_private {
> */
> resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
>
> - void __iomem *regs;
> -
> struct intel_uncore uncore;
>
> struct i915_virtual_gpu vgpu;
> @@ -3488,14 +3486,14 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
> i915_reg_t reg) \
> { \
> - return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
> + return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
> }
>
> #define __raw_write(x, s) \
> static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
> i915_reg_t reg, uint##x##_t val) \
> { \
> - write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
> + write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
> }
> __raw_read(8, b)
> __raw_read(16, w)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 82d487189a34..1686c0c973f7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -268,7 +268,7 @@ static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
> const unsigned int bank,
> const unsigned int bit)
> {
> - void __iomem * const regs = i915->regs;
> + void __iomem * const regs = i915->uncore.regs;
> u32 dw;
>
> lockdep_assert_held(&i915->irq_lock);
> @@ -1471,7 +1471,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> static void gen8_gt_irq_ack(struct drm_i915_private *i915,
> u32 master_ctl, u32 gt_iir[4])
> {
> - void __iomem * const regs = i915->regs;
> + void __iomem * const regs = i915->uncore.regs;
>
> #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> GEN8_GT_BCS_IRQ | \
> @@ -2868,7 +2868,7 @@ static inline void gen8_master_intr_enable(void __iomem * const regs)
> static irqreturn_t gen8_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private *dev_priv = to_i915(arg);
> - void __iomem * const regs = dev_priv->regs;
> + void __iomem * const regs = dev_priv->uncore.regs;
> u32 master_ctl;
> u32 gt_iir[4];
>
> @@ -2902,7 +2902,7 @@ static u32
> gen11_gt_engine_identity(struct drm_i915_private * const i915,
> const unsigned int bank, const unsigned int bit)
> {
> - void __iomem * const regs = i915->regs;
> + void __iomem * const regs = i915->uncore.regs;
> u32 timeout_ts;
> u32 ident;
>
> @@ -2986,7 +2986,7 @@ static void
> gen11_gt_bank_handler(struct drm_i915_private * const i915,
> const unsigned int bank)
> {
> - void __iomem * const regs = i915->regs;
> + void __iomem * const regs = i915->uncore.regs;
> unsigned long intr_dw;
> unsigned int bit;
>
> @@ -3029,7 +3029,7 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
> static u32
> gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
> {
> - void __iomem * const regs = dev_priv->regs;
> + void __iomem * const regs = dev_priv->uncore.regs;
> u32 iir;
>
> if (!(master_ctl & GEN11_GU_MISC_IRQ))
> @@ -3070,7 +3070,7 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = to_i915(arg);
> - void __iomem * const regs = i915->regs;
> + void __iomem * const regs = i915->uncore.regs;
> u32 master_ctl;
> u32 gu_misc_iir;
>
> @@ -3351,7 +3351,7 @@ static void gen8_irq_reset(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> int pipe;
>
> - gen8_master_intr_disable(dev_priv->regs);
> + gen8_master_intr_disable(dev_priv->uncore.regs);
>
> gen8_gt_irq_reset(dev_priv);
>
> @@ -3393,7 +3393,7 @@ static void gen11_irq_reset(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
>
> - gen11_master_intr_disable(dev_priv->regs);
> + gen11_master_intr_disable(dev_priv->uncore.regs);
>
> gen11_gt_irq_reset(dev_priv);
>
> @@ -3998,7 +3998,7 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev);
>
> - gen8_master_intr_enable(dev_priv->regs);
> + gen8_master_intr_enable(dev_priv->uncore.regs);
>
> return 0;
> }
> @@ -4060,7 +4060,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
>
> I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>
> - gen11_master_intr_enable(dev_priv->regs);
> + gen11_master_intr_enable(dev_priv->uncore.regs);
> POSTING_READ(GEN11_GFX_MSTR_IRQ);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index e54e0064b2d6..721ae4b166d5 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2413,12 +2413,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
> intel_engine_init_workarounds(engine);
>
> if (HAS_LOGICAL_RING_ELSQ(i915)) {
> - execlists->submit_reg = i915->regs +
> + execlists->submit_reg = i915->uncore.regs +
> i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
> - execlists->ctrl_reg = i915->regs +
> + execlists->ctrl_reg = i915->uncore.regs +
> i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
> } else {
> - execlists->submit_reg = i915->regs +
> + execlists->submit_reg = i915->uncore.regs +
> i915_mmio_reg_offset(RING_ELSP(engine));
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index bb9a10cc6904..e60856069971 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1330,7 +1330,6 @@ static void fw_domain_init(struct intel_uncore *uncore,
> i915_reg_t reg_ack)
> {
> struct intel_uncore_forcewake_domain *d;
> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
>
> if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
> return;
> @@ -1343,8 +1342,8 @@ static void fw_domain_init(struct intel_uncore *uncore,
> WARN_ON(!i915_mmio_reg_valid(reg_ack));
>
> d->wake_count = 0;
> - d->reg_set = i915->regs + i915_mmio_reg_offset(reg_set);
> - d->reg_ack = i915->regs + i915_mmio_reg_offset(reg_ack);
> + d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
> + d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
>
> d->id = domain_id;
>
> @@ -1539,9 +1538,53 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> -void intel_uncore_init(struct intel_uncore *uncore)
> +static int uncore_mmio_setup(struct intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore_to_i915(uncore);
> + struct pci_dev *pdev = i915->drm.pdev;
> + int mmio_bar;
> + int mmio_size;
> +
> + mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
> + /*
> + * Before gen4, the registers and the GTT are behind different BARs.
> + * However, from gen4 onwards, the registers and the GTT are shared
> + * in the same BAR, so we want to restrict this ioremap from
> + * clobbering the GTT which we want ioremap_wc instead. Fortunately,
> + * the register BAR remains the same size for all the earlier
> + * generations up to Ironlake.
> + */
> + if (INTEL_GEN(i915) < 5)
> + mmio_size = 512 * 1024;
> + else
> + mmio_size = 2 * 1024 * 1024;
> + uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> + if (uncore->regs == NULL) {
> + DRM_ERROR("failed to map registers\n");
> +
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static void uncore_mmio_cleanup(struct intel_uncore *uncore)
> +{
> + struct drm_i915_private *i915 = uncore_to_i915(uncore);
> + struct pci_dev *pdev = i915->drm.pdev;
> +
> + pci_iounmap(pdev, uncore->regs);
> +}
> +
> +
> +int intel_uncore_init(struct intel_uncore *uncore)
> +{
> + struct drm_i915_private *i915 = uncore_to_i915(uncore);
> + int ret;
> +
> + ret = uncore_mmio_setup(uncore);
> + if (ret)
> + return ret;
>
> i915_check_vgpu(i915);
>
> @@ -1589,6 +1632,8 @@ void intel_uncore_init(struct intel_uncore *uncore)
> }
>
> iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
> +
> + return 0;
> }
>
> /*
> @@ -1637,6 +1682,7 @@ void intel_uncore_fini(struct intel_uncore *uncore)
> &uncore->pmic_bus_access_nb);
> intel_uncore_forcewake_reset(uncore);
> iosf_mbi_punit_release();
> + uncore_mmio_cleanup(uncore);
> }
>
> static const struct reg_whitelist {
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index b1b596c81451..d345e5ab04a5 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -93,6 +93,8 @@ struct intel_forcewake_range {
> };
>
> struct intel_uncore {
> + void __iomem *regs;
> +
> spinlock_t lock; /** lock is also taken in irq contexts. */
>
> const struct intel_forcewake_range *fw_domains_table;
> @@ -142,7 +144,7 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
> }
>
> void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
> -void intel_uncore_init(struct intel_uncore *uncore);
> +int intel_uncore_init(struct intel_uncore *uncore);
> void intel_uncore_prune(struct intel_uncore *uncore);
> bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
> bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 09/10] drm/i915: add uncore flags
2019-03-19 18:35 ` [PATCH v2 09/10] drm/i915: add uncore flags Daniele Ceraolo Spurio
@ 2019-03-20 0:56 ` Paulo Zanoni
2019-03-20 1:28 ` Daniele Ceraolo Spurio
2019-03-21 0:26 ` Chris Wilson
1 sibling, 1 reply; 24+ messages in thread
From: Paulo Zanoni @ 2019-03-20 0:56 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> Save some uncore properties to avoid having to jump back to
> dev_priv every time
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 82 ++++++++++---------
> drivers/gpu/drm/i915/intel_uncore.h | 10 ++-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 ++--
> 6 files changed, 65 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ca41a3da1918..c609bcac8577 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2849,7 +2849,7 @@ static int intel_runtime_suspend(struct device *kdev)
> enable_rpm_wakeref_asserts(dev_priv);
> intel_runtime_pm_cleanup(dev_priv);
>
> - if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
> + if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
> DRM_ERROR("Unclaimed access detected prior to suspending\n");
>
> dev_priv->runtime_pm.suspended = true;
> @@ -2903,7 +2903,7 @@ static int intel_runtime_resume(struct device *kdev)
>
> intel_opregion_notify_adapter(dev_priv, PCI_D0);
> dev_priv->runtime_pm.suspended = false;
> - if (intel_uncore_unclaimed_mmio(dev_priv))
> + if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>
> if (INTEL_GEN(dev_priv) >= 11) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d4fcad136120..cfe379e938e6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13517,7 +13517,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
> * so enable debugging for the next modeset - and hope we catch
> * the culprit.
> */
> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
> intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index 57ed49dc19c4..125662c64934 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -270,7 +270,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> * periodically arm the mmio checker to see if we are triggering
> * any invalid access.
> */
> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>
> for_each_engine(engine, dev_priv, id) {
> struct hangcheck hc;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 1816eeae3ba9..26b28afb4500 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -509,18 +509,17 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
> }
>
> static bool
> -check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
> +check_for_unclaimed_mmio(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> bool ret = false;
>
> - if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
> + if (uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED)
> ret |= fpga_check_for_unclaimed_mmio(uncore);
>
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + if (uncore->flags & UNCORE_HAS_DBG_UNCLAIMED)
> ret |= vlv_check_for_unclaimed_mmio(uncore);
>
> - if (IS_GEN_RANGE(dev_priv, 6, 7))
> + if (uncore->flags & UNCORE_HAS_FIFO)
> ret |= gen6_check_for_fifo_debug(uncore);
>
> return ret;
> @@ -529,14 +528,12 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
> static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
> unsigned int restore_forcewake)
> {
> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
> -
> /* clear out unclaimed reg detection bit */
> - if (check_for_unclaimed_mmio(i915))
> + if (check_for_unclaimed_mmio(uncore))
> DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
>
> /* WaDisableShadowRegForCpd:chv */
> - if (IS_CHERRYVIEW(i915)) {
> + if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
> __raw_i915_write32(uncore, GTFIFOCTL,
> __raw_i915_read32(uncore, GTFIFOCTL) |
> GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> @@ -549,7 +546,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
> spin_lock_irq(&uncore->lock);
> uncore->funcs.force_wake_get(uncore, restore_forcewake);
>
> - if (IS_GEN_RANGE(i915, 6, 7))
> + if (uncore->flags & UNCORE_HAS_FIFO)
> uncore->fifo_count = fifo_free_entries(uncore);
> spin_unlock_irq(&uncore->lock);
> }
> @@ -668,12 +665,10 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
> */
> void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
> {
> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
> -
> spin_lock_irq(&uncore->lock);
> if (!--uncore->user_forcewake.count) {
> - if (intel_uncore_unclaimed_mmio(i915))
> - dev_info(i915->drm.dev,
> + if (intel_uncore_unclaimed_mmio(uncore))
> + dev_info(uncore_to_i915(uncore)->drm.dev,
> "Invalid mmio detected during user access\n");
>
> uncore->unclaimed_mmio_check =
> @@ -1072,12 +1067,12 @@ ilk_dummy_write(struct intel_uncore *uncore)
> }
>
> static void
> -__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> +__unclaimed_reg_debug(struct intel_uncore *uncore,
> const i915_reg_t reg,
> const bool read,
> const bool before)
> {
> - if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
> + if (WARN(check_for_unclaimed_mmio(uncore) && !before,
> "Unclaimed %s register 0x%x\n",
> read ? "read from" : "write to",
> i915_mmio_reg_offset(reg)))
> @@ -1086,7 +1081,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> }
>
> static inline void
> -unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> +unclaimed_reg_debug(struct intel_uncore *uncore,
> const i915_reg_t reg,
> const bool read,
> const bool before)
> @@ -1094,7 +1089,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> if (likely(!i915_modparams.mmio_debug))
> return;
>
> - __unclaimed_reg_debug(dev_priv, reg, read, before);
> + __unclaimed_reg_debug(uncore, reg, read, before);
> }
>
> #define GEN2_READ_HEADER(x) \
> @@ -1145,10 +1140,10 @@ __gen2_read(64)
> u##x val = 0; \
> assert_rpm_wakelock_held(dev_priv); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> - unclaimed_reg_debug(dev_priv, reg, true, true)
> + unclaimed_reg_debug(uncore, reg, true, true)
>
> #define GEN6_READ_FOOTER \
> - unclaimed_reg_debug(dev_priv, reg, true, false); \
> + unclaimed_reg_debug(uncore, reg, true, false); \
> spin_unlock_irqrestore(&uncore->lock, irqflags); \
> trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
> return val
> @@ -1259,10 +1254,10 @@ __gen2_write(32)
> trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> assert_rpm_wakelock_held(dev_priv); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> - unclaimed_reg_debug(dev_priv, reg, false, true)
> + unclaimed_reg_debug(uncore, reg, false, true)
>
> #define GEN6_WRITE_FOOTER \
> - unclaimed_reg_debug(dev_priv, reg, false, false); \
> + unclaimed_reg_debug(uncore, reg, false, false); \
> spin_unlock_irqrestore(&uncore->lock, irqflags)
>
> #define __gen6_write(x) \
> @@ -1391,7 +1386,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore_to_i915(uncore);
>
> - if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
> return;
>
> if (INTEL_GEN(i915) >= 11) {
> @@ -1590,6 +1585,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
>
> i915_check_vgpu(i915);
>
> + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
> + uncore->flags |= UNCORE_HAS_FORCEWAKE;
> +
> intel_uncore_edram_detect(i915);
> intel_uncore_fw_domains_init(uncore);
> __intel_uncore_early_sanitize(uncore, 0);
> @@ -1598,12 +1596,14 @@ int intel_uncore_init(struct intel_uncore *uncore)
> uncore->pmic_bus_access_nb.notifier_call =
> i915_pmic_bus_access_notifier;
>
> - if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> - } else if (IS_GEN(i915, 5)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
This changes the behavior when it's gen5 and vgpu is active. Is this
even possible? If not, will it ever be? Whether intentional or not,
perhaps it needs to be in a separate patch.
Since this is still the init function, maybe we don't even need this
change.
> + if (IS_GEN(i915, 5)) {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + } else {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> + }
> } else if (IS_GEN_RANGE(i915, 6, 7)) {
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
>
> @@ -1633,6 +1633,15 @@ int intel_uncore_init(struct intel_uncore *uncore)
> ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> }
>
> + if (HAS_FPGA_DBG_UNCLAIMED(i915))
> + uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> +
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
> +
> + if (IS_GEN_RANGE(i915, 6, 7))
> + uncore->flags |= UNCORE_HAS_FIFO;
> +
> iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>
> return 0;
> @@ -1864,15 +1873,14 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> {
> - return check_for_unclaimed_mmio(dev_priv);
> + return check_for_unclaimed_mmio(uncore);
> }
>
> bool
> -intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
> +intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> bool ret = false;
>
> spin_lock_irq(&uncore->lock);
> @@ -1880,7 +1888,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
> if (unlikely(uncore->unclaimed_mmio_check <= 0))
> goto out;
>
> - if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
> + if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
> if (!i915_modparams.mmio_debug) {
> DRM_DEBUG("Unclaimed register detected, "
> "enabling oneshot unclaimed register reporting. "
> @@ -1912,7 +1920,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> } else if (INTEL_GEN(dev_priv) >= 6) {
> fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
That doesn't look equivalent. Isn't it always gonna WARN now? Gen 2-5
never has the flag.
The whole function is about checking for gens, when we switch to
checking the flag we make it harder to read, especially since the
reader now has to think about whether vgpu_active() was true during
initialization. I'm not sure this is an improvement.
> fw_domains = 0;
> }
>
> @@ -1938,7 +1946,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> fw_domains = FORCEWAKE_RENDER;
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
Same here.
> fw_domains = 0;
> }
>
> @@ -1969,7 +1977,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>
> WARN_ON(!op);
>
> - if (intel_vgpu_active(dev_priv))
> + if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
This changes the vgpu_active() from something you call all the time to
a static check that is only ever checked during initialization. A quick
read at the vgpu code does not tell me whether this is something that
can change over time (i.e., the result intel_vgpu_active() is always
the same), but my first guess would be that it could change over time.
Still, this is the kind of change that should be in its own patch if
it's a behavior change and not just a rework in function arguments.
-
Overall, I'm not super sold in the current approach of the patch.
Perhaps it's fine to actually call uncore_to_i915() in the functions
that need to do gen or feature checks (e.g.,
check_for_unclaimed_mmio()). Maybe instead of adding the flags and
converting everything to intel_uncore we should keep the conversion of
everything to intel_uncore and then use uncore_to_i915() when needed.
I'm not against the patch, but we at least need to sort out the
possible behavior changes (or go the easier way to just convert all
these functions and then use uncore_to_i915() when needed).
Having more opinions on the design would probably help. Ping @everyone.
> return 0;
>
> if (op & FW_REG_READ)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index d345e5ab04a5..6df6586bb603 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -127,6 +127,12 @@ struct intel_uncore {
> } user_forcewake;
>
> int unclaimed_mmio_check;
> +
> + u32 flags;
> +#define UNCORE_HAS_FORCEWAKE BIT(0)
> +#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
> +#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
> +#define UNCORE_HAS_FIFO BIT(3)
> };
>
> /* Iterate over initialised fw domains */
> @@ -146,8 +152,8 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
> void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
> int intel_uncore_init(struct intel_uncore *uncore);
> void intel_uncore_prune(struct intel_uncore *uncore);
> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
> -bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
> +bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
> void intel_uncore_fini(struct intel_uncore *uncore);
> void intel_uncore_suspend(struct intel_uncore *uncore);
> void intel_uncore_resume_early(struct intel_uncore *uncore);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 69aa260b479d..d2c6a03fb29c 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -122,6 +122,7 @@ int intel_uncore_mock_selftests(void)
> static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_priv)
> {
> #define FW_RANGE 0x40000
> + struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long *valid;
> u32 offset;
> int err;
> @@ -142,31 +143,31 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
> if (!valid)
> return -ENOMEM;
>
> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>
> - check_for_unclaimed_mmio(dev_priv);
> + check_for_unclaimed_mmio(uncore);
> for (offset = 0; offset < FW_RANGE; offset += 4) {
> i915_reg_t reg = { offset };
>
> (void)I915_READ_FW(reg);
> - if (!check_for_unclaimed_mmio(dev_priv))
> + if (!check_for_unclaimed_mmio(uncore))
> set_bit(offset, valid);
> }
>
> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>
> err = 0;
> for_each_set_bit(offset, valid, FW_RANGE) {
> i915_reg_t reg = { offset };
>
> iosf_mbi_punit_acquire();
> - intel_uncore_forcewake_reset(&dev_priv->uncore);
> + intel_uncore_forcewake_reset(uncore);
> iosf_mbi_punit_release();
>
> - check_for_unclaimed_mmio(dev_priv);
> + check_for_unclaimed_mmio(uncore);
>
> (void)I915_READ(reg);
> - if (check_for_unclaimed_mmio(dev_priv)) {
> + if (check_for_unclaimed_mmio(uncore)) {
> pr_err("Unclaimed mmio read to register 0x%04x\n",
> offset);
> err = -EINVAL;
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 09/10] drm/i915: add uncore flags
2019-03-20 0:56 ` Paulo Zanoni
@ 2019-03-20 1:28 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 24+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-20 1:28 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx
On 3/19/19 5:56 PM, Paulo Zanoni wrote:
> Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
>> Save some uncore properties to avoid having to jump back to
>> dev_priv every time
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 4 +-
>> drivers/gpu/drm/i915/intel_display.c | 2 +-
>> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
>> drivers/gpu/drm/i915/intel_uncore.c | 82 ++++++++++---------
>> drivers/gpu/drm/i915/intel_uncore.h | 10 ++-
>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 ++--
>> 6 files changed, 65 insertions(+), 50 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index ca41a3da1918..c609bcac8577 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -2849,7 +2849,7 @@ static int intel_runtime_suspend(struct device *kdev)
>> enable_rpm_wakeref_asserts(dev_priv);
>> intel_runtime_pm_cleanup(dev_priv);
>>
>> - if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
>> + if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
>> DRM_ERROR("Unclaimed access detected prior to suspending\n");
>>
>> dev_priv->runtime_pm.suspended = true;
>> @@ -2903,7 +2903,7 @@ static int intel_runtime_resume(struct device *kdev)
>>
>> intel_opregion_notify_adapter(dev_priv, PCI_D0);
>> dev_priv->runtime_pm.suspended = false;
>> - if (intel_uncore_unclaimed_mmio(dev_priv))
>> + if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
>> DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>>
>> if (INTEL_GEN(dev_priv) >= 11) {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index d4fcad136120..cfe379e938e6 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -13517,7 +13517,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>> * so enable debugging for the next modeset - and hope we catch
>> * the culprit.
>> */
>> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
>> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>> intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
>> index 57ed49dc19c4..125662c64934 100644
>> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
>> @@ -270,7 +270,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
>> * periodically arm the mmio checker to see if we are triggering
>> * any invalid access.
>> */
>> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
>> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>>
>> for_each_engine(engine, dev_priv, id) {
>> struct hangcheck hc;
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 1816eeae3ba9..26b28afb4500 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -509,18 +509,17 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
>> }
>>
>> static bool
>> -check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
>> +check_for_unclaimed_mmio(struct intel_uncore *uncore)
>> {
>> - struct intel_uncore *uncore = &dev_priv->uncore;
>> bool ret = false;
>>
>> - if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
>> + if (uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED)
>> ret |= fpga_check_for_unclaimed_mmio(uncore);
>>
>> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> + if (uncore->flags & UNCORE_HAS_DBG_UNCLAIMED)
>> ret |= vlv_check_for_unclaimed_mmio(uncore);
>>
>> - if (IS_GEN_RANGE(dev_priv, 6, 7))
>> + if (uncore->flags & UNCORE_HAS_FIFO)
>> ret |= gen6_check_for_fifo_debug(uncore);
>>
>> return ret;
>> @@ -529,14 +528,12 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
>> static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
>> unsigned int restore_forcewake)
>> {
>> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
>> -
>> /* clear out unclaimed reg detection bit */
>> - if (check_for_unclaimed_mmio(i915))
>> + if (check_for_unclaimed_mmio(uncore))
>> DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
>>
>> /* WaDisableShadowRegForCpd:chv */
>> - if (IS_CHERRYVIEW(i915)) {
>> + if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
>> __raw_i915_write32(uncore, GTFIFOCTL,
>> __raw_i915_read32(uncore, GTFIFOCTL) |
>> GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
>> @@ -549,7 +546,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
>> spin_lock_irq(&uncore->lock);
>> uncore->funcs.force_wake_get(uncore, restore_forcewake);
>>
>> - if (IS_GEN_RANGE(i915, 6, 7))
>> + if (uncore->flags & UNCORE_HAS_FIFO)
>> uncore->fifo_count = fifo_free_entries(uncore);
>> spin_unlock_irq(&uncore->lock);
>> }
>> @@ -668,12 +665,10 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
>> */
>> void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
>> {
>> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
>> -
>> spin_lock_irq(&uncore->lock);
>> if (!--uncore->user_forcewake.count) {
>> - if (intel_uncore_unclaimed_mmio(i915))
>> - dev_info(i915->drm.dev,
>> + if (intel_uncore_unclaimed_mmio(uncore))
>> + dev_info(uncore_to_i915(uncore)->drm.dev,
>> "Invalid mmio detected during user access\n");
>>
>> uncore->unclaimed_mmio_check =
>> @@ -1072,12 +1067,12 @@ ilk_dummy_write(struct intel_uncore *uncore)
>> }
>>
>> static void
>> -__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>> +__unclaimed_reg_debug(struct intel_uncore *uncore,
>> const i915_reg_t reg,
>> const bool read,
>> const bool before)
>> {
>> - if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
>> + if (WARN(check_for_unclaimed_mmio(uncore) && !before,
>> "Unclaimed %s register 0x%x\n",
>> read ? "read from" : "write to",
>> i915_mmio_reg_offset(reg)))
>> @@ -1086,7 +1081,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>> }
>>
>> static inline void
>> -unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>> +unclaimed_reg_debug(struct intel_uncore *uncore,
>> const i915_reg_t reg,
>> const bool read,
>> const bool before)
>> @@ -1094,7 +1089,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>> if (likely(!i915_modparams.mmio_debug))
>> return;
>>
>> - __unclaimed_reg_debug(dev_priv, reg, read, before);
>> + __unclaimed_reg_debug(uncore, reg, read, before);
>> }
>>
>> #define GEN2_READ_HEADER(x) \
>> @@ -1145,10 +1140,10 @@ __gen2_read(64)
>> u##x val = 0; \
>> assert_rpm_wakelock_held(dev_priv); \
>> spin_lock_irqsave(&uncore->lock, irqflags); \
>> - unclaimed_reg_debug(dev_priv, reg, true, true)
>> + unclaimed_reg_debug(uncore, reg, true, true)
>>
>> #define GEN6_READ_FOOTER \
>> - unclaimed_reg_debug(dev_priv, reg, true, false); \
>> + unclaimed_reg_debug(uncore, reg, true, false); \
>> spin_unlock_irqrestore(&uncore->lock, irqflags); \
>> trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
>> return val
>> @@ -1259,10 +1254,10 @@ __gen2_write(32)
>> trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
>> assert_rpm_wakelock_held(dev_priv); \
>> spin_lock_irqsave(&uncore->lock, irqflags); \
>> - unclaimed_reg_debug(dev_priv, reg, false, true)
>> + unclaimed_reg_debug(uncore, reg, false, true)
>>
>> #define GEN6_WRITE_FOOTER \
>> - unclaimed_reg_debug(dev_priv, reg, false, false); \
>> + unclaimed_reg_debug(uncore, reg, false, false); \
>> spin_unlock_irqrestore(&uncore->lock, irqflags)
>>
>> #define __gen6_write(x) \
>> @@ -1391,7 +1386,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>> {
>> struct drm_i915_private *i915 = uncore_to_i915(uncore);
>>
>> - if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
>> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
>> return;
>>
>> if (INTEL_GEN(i915) >= 11) {
>> @@ -1590,6 +1585,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
>>
>> i915_check_vgpu(i915);
>>
>> + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
>> + uncore->flags |= UNCORE_HAS_FORCEWAKE;
>> +
>> intel_uncore_edram_detect(i915);
>> intel_uncore_fw_domains_init(uncore);
>> __intel_uncore_early_sanitize(uncore, 0);
>> @@ -1598,12 +1596,14 @@ int intel_uncore_init(struct intel_uncore *uncore)
>> uncore->pmic_bus_access_nb.notifier_call =
>> i915_pmic_bus_access_notifier;
>>
>> - if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
>> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
>> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
>> - } else if (IS_GEN(i915, 5)) {
>> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
>> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
>> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
>
> This changes the behavior when it's gen5 and vgpu is active. Is this
> even possible? If not, will it ever be? Whether intentional or not,
> perhaps it needs to be in a separate patch.
It shouldn't be possible, GVT is gen8+. Gen5 doesn't have PPGTT so it is
not something you can run virtualization on and that is why I didn't
care of that case.
>
> Since this is still the init function, maybe we don't even need this
> change.
True, I just thought that since I had the flag I could make use of it to
remove some redundant checks :P
>
>
>> + if (IS_GEN(i915, 5)) {
>> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
>> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
>> + } else {
>> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
>> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
>> + }
>> } else if (IS_GEN_RANGE(i915, 6, 7)) {
>> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
>>
>> @@ -1633,6 +1633,15 @@ int intel_uncore_init(struct intel_uncore *uncore)
>> ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>> }
>>
>> + if (HAS_FPGA_DBG_UNCLAIMED(i915))
>> + uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
>> +
>> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> + uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
>> +
>> + if (IS_GEN_RANGE(i915, 6, 7))
>> + uncore->flags |= UNCORE_HAS_FIFO;
>> +
>> iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>>
>> return 0;
>> @@ -1864,15 +1873,14 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
>> return ret;
>> }
>>
>> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
>> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
>> {
>> - return check_for_unclaimed_mmio(dev_priv);
>> + return check_for_unclaimed_mmio(uncore);
>> }
>>
>> bool
>> -intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
>> +intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
>> {
>> - struct intel_uncore *uncore = &dev_priv->uncore;
>> bool ret = false;
>>
>> spin_lock_irq(&uncore->lock);
>> @@ -1880,7 +1888,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
>> if (unlikely(uncore->unclaimed_mmio_check <= 0))
>> goto out;
>>
>> - if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
>> + if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
>> if (!i915_modparams.mmio_debug) {
>> DRM_DEBUG("Unclaimed register detected, "
>> "enabling oneshot unclaimed register reporting. "
>> @@ -1912,7 +1920,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
>> } else if (INTEL_GEN(dev_priv) >= 6) {
>> fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
>> } else {
>> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
>> + WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
>
> That doesn't look equivalent. Isn't it always gonna WARN now? Gen 2-5
> never has the flag.
ooops, you're right the check is the wrong way around
>
> The whole function is about checking for gens, when we switch to
> checking the flag we make it harder to read, especially since the
> reader now has to think about whether vgpu_active() was true during
> initialization. I'm not sure this is an improvement.
I've read this check as "if we didn't match any of the above cases on a
platform with forcewake then we're missing something, so warn", kind of
like a MISSING_CASE macro. What gen is the platform or whether we're on
a vgpu or not is not really something we care about here IMO.
>
>> fw_domains = 0;
>> }
>>
>> @@ -1938,7 +1946,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
>> } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
>> fw_domains = FORCEWAKE_RENDER;
>> } else {
>> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
>> + WARN_ON(!(uncore->flags & UNCORE_HAS_FORCEWAKE));
>
> Same here.
>
ooops x2 :P
>> fw_domains = 0;
>> }
>>
>> @@ -1969,7 +1977,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>>
>> WARN_ON(!op);
>>
>> - if (intel_vgpu_active(dev_priv))
>> + if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
>
> This changes the vgpu_active() from something you call all the time to
> a static check that is only ever checked during initialization. A quick
> read at the vgpu code does not tell me whether this is something that
> can change over time (i.e., the result intel_vgpu_active() is always
> the same), but my first guess would be that it could change over time.
AFAIU intel_vgpu_active() tells us whether we're running on a virtual
GPU so it can't change at runtime.
>
> Still, this is the kind of change that should be in its own patch if
> it's a behavior change and not just a rework in function arguments.
>
I'll split it out
> -
>
> Overall, I'm not super sold in the current approach of the patch.
> Perhaps it's fine to actually call uncore_to_i915() in the functions
> that need to do gen or feature checks (e.g.,
> check_for_unclaimed_mmio()). Maybe instead of adding the flags and
> converting everything to intel_uncore we should keep the conversion of
> everything to intel_uncore and then use uncore_to_i915() when needed.
>
> I'm not against the patch, but we at least need to sort out the
> possible behavior changes (or go the easier way to just convert all
> these functions and then use uncore_to_i915() when needed).
I just wanted to reduce the calls to uncore_to_i915 as much as possible
for extra encapsulation. My goal is to have no dev_priv involvment is
the full read/write flow at the end of the rework, but if the general
consensus is to use uncore_to_i915() instead I don't mind switching to that.
Thanks for the feedback!
Daniele
>
> Having more opinions on the design would probably help. Ping @everyone.
>
>> return 0;
>>
>> if (op & FW_REG_READ)
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
>> index d345e5ab04a5..6df6586bb603 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>> @@ -127,6 +127,12 @@ struct intel_uncore {
>> } user_forcewake;
>>
>> int unclaimed_mmio_check;
>> +
>> + u32 flags;
>> +#define UNCORE_HAS_FORCEWAKE BIT(0)
>> +#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
>> +#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
>> +#define UNCORE_HAS_FIFO BIT(3)
>> };
>>
>> /* Iterate over initialised fw domains */
>> @@ -146,8 +152,8 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
>> void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>> int intel_uncore_init(struct intel_uncore *uncore);
>> void intel_uncore_prune(struct intel_uncore *uncore);
>> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
>> -bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
>> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
>> +bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
>> void intel_uncore_fini(struct intel_uncore *uncore);
>> void intel_uncore_suspend(struct intel_uncore *uncore);
>> void intel_uncore_resume_early(struct intel_uncore *uncore);
>> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> index 69aa260b479d..d2c6a03fb29c 100644
>> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> @@ -122,6 +122,7 @@ int intel_uncore_mock_selftests(void)
>> static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_priv)
>> {
>> #define FW_RANGE 0x40000
>> + struct intel_uncore *uncore = &dev_priv->uncore;
>> unsigned long *valid;
>> u32 offset;
>> int err;
>> @@ -142,31 +143,31 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
>> if (!valid)
>> return -ENOMEM;
>>
>> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>
>> - check_for_unclaimed_mmio(dev_priv);
>> + check_for_unclaimed_mmio(uncore);
>> for (offset = 0; offset < FW_RANGE; offset += 4) {
>> i915_reg_t reg = { offset };
>>
>> (void)I915_READ_FW(reg);
>> - if (!check_for_unclaimed_mmio(dev_priv))
>> + if (!check_for_unclaimed_mmio(uncore))
>> set_bit(offset, valid);
>> }
>>
>> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>>
>> err = 0;
>> for_each_set_bit(offset, valid, FW_RANGE) {
>> i915_reg_t reg = { offset };
>>
>> iosf_mbi_punit_acquire();
>> - intel_uncore_forcewake_reset(&dev_priv->uncore);
>> + intel_uncore_forcewake_reset(uncore);
>> iosf_mbi_punit_release();
>>
>> - check_for_unclaimed_mmio(dev_priv);
>> + check_for_unclaimed_mmio(uncore);
>>
>> (void)I915_READ(reg);
>> - if (check_for_unclaimed_mmio(dev_priv)) {
>> + if (check_for_unclaimed_mmio(uncore)) {
>> pr_err("Unclaimed mmio read to register 0x%04x\n",
>> offset);
>> err = -EINVAL;
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.IGT: failure for Compartmentalize uncore code (rev2)
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
` (13 preceding siblings ...)
2019-03-19 19:39 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-20 5:53 ` Patchwork
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-03-20 5:53 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Compartmentalize uncore code (rev2)
URL : https://patchwork.freedesktop.org/series/57962/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5774_full -> Patchwork_12517_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12517_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12517_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12517_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-skl: PASS -> INCOMPLETE
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_mocs_settings@mocs-isolation-bsd2}:
- shard-skl: NOTRUN -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12517_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_exec_schedule@preempt-bsd2:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +1
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +6
* igt@gem_softpin@noreloc-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@basic-modeset-d:
- shard-iclb: NOTRUN -> SKIP [fdo#109278]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +1
* igt@kms_color@pipe-a-gamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_content_protection@atomic-dpms:
- shard-iclb: NOTRUN -> SKIP [fdo#109300]
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-kbl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-512x512-onscreen:
- shard-iclb: NOTRUN -> SKIP [fdo#109279]
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +1
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-xtiled:
- shard-skl: PASS -> FAIL [fdo#107791]
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
- shard-skl: NOTRUN -> FAIL [fdo#103184]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363] +1
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: PASS -> INCOMPLETE [fdo#109507]
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +10
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-iclb: PASS -> FAIL [fdo#109247] +11
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +61
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +131
* igt@kms_invalid_dotclock:
- shard-iclb: NOTRUN -> SKIP [fdo#109310]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_psr@psr2_basic:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: NOTRUN -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-glk: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: NOTRUN -> FAIL [fdo#104894] +1
* igt@kms_vrr@flip-basic:
- shard-iclb: NOTRUN -> SKIP [fdo#109502]
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-iclb: NOTRUN -> SKIP [fdo#109291]
#### Possible fixes ####
* igt@gem_mmap_gtt@big-copy-xy:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS
* igt@kms_atomic_transition@1x-modeset-transitions:
- shard-skl: FAIL [fdo#107815] / [fdo#108470] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-iclb: FAIL [fdo#107725] -> PASS
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: FAIL [fdo#103355] -> PASS
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +9
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: FAIL [fdo#109247] -> PASS +8
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: FAIL [fdo#108145] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-apl: FAIL [fdo#110037] -> PASS
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: INCOMPLETE [fdo#103665] -> DMESG-FAIL [fdo#105763]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108739]: https://bugs.freedesktop.org/show_bug.cgi?id=108739
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109310]: https://bugs.freedesktop.org/show_bug.cgi?id=109310
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5774 -> Patchwork_12517
CI_DRM_5774: eb58badf383e72d54ba48b8570ce7169c1419f6a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4890: 6d4d6949a099521003de252358601d22115e27ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12517: d3c15f3a0fd87cfeb9868ed308abe1e28bc969e1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12517/
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 00/10] Compartmentalize uncore code
2019-03-19 18:59 ` [PATCH v2 00/10] Compartmentalize uncore code Chris Wilson
@ 2019-03-20 11:34 ` Chris Wilson
0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-03-20 11:34 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Chris Wilson (2019-03-19 18:59:04)
> Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:33)
> > Compared to v1 [1], there is a new patch for further simplification of
> > low-level fw get/put by always using the bitmasks since the upper bits
> > of the fw reg are reserved on gen6 and I couldn't find any reason
> > writing them wouldn't work in the git history.
> > I put together a small selftest to trybot this on snb [2], if people
> > think it is worth adding it to the tree I can clean it up and send it
> > for review.
> >
> > Apart from the above, addresses the review comments, the only
> > non-trivial one being moving the mmio setup under uncore.
> >
> > [1] https://patchwork.freedesktop.org/series/57962/
> > [2] https://patchwork.freedesktop.org/patch/292852/?series=58159&rev=1
>
> I thought so. You just need to verify that the fw count is zero at the
> start of the loop and then flush the hrtimer instead of the imprecise
> usleep().
After beating around the bush to find the right mix of registers that
give us the inspection we need, I've pushed your selftest. Hopefully
that holds up to soak testing and provides a nice early warning canary.
Thanks,
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 09/10] drm/i915: add uncore flags
2019-03-19 18:35 ` [PATCH v2 09/10] drm/i915: add uncore flags Daniele Ceraolo Spurio
2019-03-20 0:56 ` Paulo Zanoni
@ 2019-03-21 0:26 ` Chris Wilson
1 sibling, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-03-21 0:26 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:42)
> Save some uncore properties to avoid having to jump back to
> dev_priv every time
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
I wanted to push "always use flags" separately just to have a better
look at whether we survived, since our rc6 counters on snb don't seem
broken, that looked ok.
Pushed up to the patch before this, as this one didn't apply cleanly.
However, the selftest needs a little tweak as a couple of machines are
flip-flopping -- we may need to be more careful in our wait_for_ack, or
something.
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2019-03-21 0:26 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-19 18:35 [PATCH v2 00/10] Compartmentalize uncore code Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 01/10] drm/i915: always use masks on FW regs Daniele Ceraolo Spurio
2019-03-19 23:14 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 02/10] drm/i915: use intel_uncore in fw get/put internal paths Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 03/10] drm/i915: use intel_uncore for all forcewake get/put Daniele Ceraolo Spurio
2019-03-19 23:48 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 04/10] drm/i915: make more uncore function work on intel_uncore Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 05/10] drm/i915: make find_fw_domain " Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 06/10] drm/i915: reduce the dev_priv->uncore dance in uncore.c Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 07/10] drm/i915: move regs pointer inside the uncore structure Daniele Ceraolo Spurio
2019-03-20 0:03 ` Paulo Zanoni
2019-03-19 18:35 ` [PATCH v2 08/10] drm/i915: make raw access function work on uncore Daniele Ceraolo Spurio
2019-03-19 18:35 ` [PATCH v2 09/10] drm/i915: add uncore flags Daniele Ceraolo Spurio
2019-03-20 0:56 ` Paulo Zanoni
2019-03-20 1:28 ` Daniele Ceraolo Spurio
2019-03-21 0:26 ` Chris Wilson
2019-03-19 18:35 ` [PATCH v2 10/10] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
2019-03-19 19:11 ` Chris Wilson
2019-03-19 18:55 ` ✗ Fi.CI.CHECKPATCH: warning for Compartmentalize uncore code (rev2) Patchwork
2019-03-19 18:59 ` [PATCH v2 00/10] Compartmentalize uncore code Chris Wilson
2019-03-20 11:34 ` Chris Wilson
2019-03-19 19:00 ` ✗ Fi.CI.SPARSE: warning for Compartmentalize uncore code (rev2) Patchwork
2019-03-19 19:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-20 5:53 ` ✗ Fi.CI.IGT: failure " Patchwork
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