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* [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support
@ 2019-03-21 14:23 Biju Das
  2019-03-21 14:23 ` [cip-dev] [PATCH 01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings Biju Das
                   ` (17 more replies)
  0 siblings, 18 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:23 UTC (permalink / raw)
  To: cip-dev

This patch series aims to add SoC identification/SYSC/RST support for
RZ/G2[ME] SoCs.

This patch series is based on linux-4.19.y-cip and all the patches
in this series are cherry-picked from linux rc tree.


Biju Das (8):
  dt-bindings: arm: Document RZ/G2M SoC DT bindings
  soc: renesas: Identify RZ/G2M
  arm64: Add Renesas R8A774A1 support
  arm64: defconfig: enable R8A774A1 SoC
  dt-bindings: power: Add r8a774a1 SYSC power domain definitions
  soc: renesas: rcar-sysc: Add r8a774a1 support
  soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A,B}
  soc: renesas: rcar-rst: Add support for RZ/G2M

Fabrizio Castro (10):
  dt-bindings: arm: Document RZ/G2E SoC DT bindings
  dt-bindings: arm: Fix RZ/G2E part number
  soc: renesas: Identify RZ/G2E
  arm64: Add Renesas R8A774C0 support
  arm64: defconfig: enable R8A774C0 SoC
  dt-bindings: power: Add r8a774c0 SYSC power domain definitions
  dt-bindings: power: rcar-sysc: Document r8a774c0 sysc
  soc: renesas: rcar-sysc: Add r8a774c0 support
  dt-bindings: reset: rcar-rst: Document r8a774c0 rst
  soc: renesas: rcar-rst: Add support for RZ/G2E

 Documentation/devicetree/bindings/arm/shmobile.txt |  4 ++
 .../bindings/power/renesas,rcar-sysc.txt           |  2 +
 .../devicetree/bindings/reset/renesas,rst.txt      |  2 +
 arch/arm64/Kconfig.platforms                       | 12 +++++
 arch/arm64/configs/defconfig                       |  2 +
 drivers/soc/renesas/Kconfig                        | 16 +++++--
 drivers/soc/renesas/Makefile                       |  2 +
 drivers/soc/renesas/r8a774a1-sysc.c                | 45 ++++++++++++++++++
 drivers/soc/renesas/r8a774c0-sysc.c                | 53 ++++++++++++++++++++++
 drivers/soc/renesas/rcar-rst.c                     |  5 +-
 drivers/soc/renesas/rcar-sysc.c                    |  6 +++
 drivers/soc/renesas/rcar-sysc.h                    |  2 +
 drivers/soc/renesas/renesas-soc.c                  | 35 +++++++++++---
 include/dt-bindings/power/r8a774a1-sysc.h          | 31 +++++++++++++
 include/dt-bindings/power/r8a774c0-sysc.h          | 25 ++++++++++
 15 files changed, 231 insertions(+), 11 deletions(-)
 create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c
 create mode 100644 drivers/soc/renesas/r8a774c0-sysc.c
 create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h
 create mode 100644 include/dt-bindings/power/r8a774c0-sysc.h

-- 
2.7.4

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
@ 2019-03-21 14:23 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 02/18] dt-bindings: arm: Document RZ/G2E " Biju Das
                   ` (16 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:23 UTC (permalink / raw)
  To: cip-dev

Add device tree bindings documentation for Renesas RZ/G2M (r8a774a1) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 01588646dbce3bf9a79a190f3949677067cc1e20)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 89b4a38..8acd3cd 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -23,6 +23,8 @@ SoCs:
     compatible = "renesas,r8a7745"
   - RZ/G1C (R8A77470)
     compatible = "renesas,r8a77470"
+  - RZ/G2M (R8A774A1)
+    compatible = "renesas,r8a774a1"
   - R-Car M1A (R8A77781)
     compatible = "renesas,r8a7778"
   - R-Car H1 (R8A77790)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 02/18] dt-bindings: arm: Document RZ/G2E SoC DT bindings
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
  2019-03-21 14:23 ` [cip-dev] [PATCH 01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 03/18] dt-bindings: arm: Fix RZ/G2E part number Biju Das
                   ` (15 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add device tree bindings documentation for Renesas RZ/G2E (r8a774c0)
SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 39c0e5a8746cfbfb87e86761337c807e7faea134)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 8acd3cd..9d74d81 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -25,6 +25,8 @@ SoCs:
     compatible = "renesas,r8a77470"
   - RZ/G2M (R8A774A1)
     compatible = "renesas,r8a774a1"
+  - RZ/G2E (RA8774C0)
+    compatible = "renesas,r8a774c0"
   - R-Car M1A (R8A77781)
     compatible = "renesas,r8a7778"
   - R-Car H1 (R8A77790)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 03/18] dt-bindings: arm: Fix RZ/G2E part number
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
  2019-03-21 14:23 ` [cip-dev] [PATCH 01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 02/18] dt-bindings: arm: Document RZ/G2E " Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 04/18] soc: renesas: Identify RZ/G2M Biju Das
                   ` (14 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Fix RZ/G2E part number from its description.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 058ad7b6aa5204d3af878415c7b946748ab34f7a)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 9d74d81..7b1e257 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -25,7 +25,7 @@ SoCs:
     compatible = "renesas,r8a77470"
   - RZ/G2M (R8A774A1)
     compatible = "renesas,r8a774a1"
-  - RZ/G2E (RA8774C0)
+  - RZ/G2E (R8A774C0)
     compatible = "renesas,r8a774c0"
   - R-Car M1A (R8A77781)
     compatible = "renesas,r8a7778"
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 04/18] soc: renesas: Identify RZ/G2M
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (2 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 03/18] dt-bindings: arm: Fix RZ/G2E part number Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 05/18] soc: renesas: Identify RZ/G2E Biju Das
                   ` (13 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

This patch adds support for identifying the RZ/G2M (r8a774a1) SoC.
It corrects the original RZ/G SoC family name to RZ/G1 and also
adds support for the new RZ/G2 SoC family.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 2a4056a759e26745f3a19431f5428c581fd8f347)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/soc/renesas/renesas-soc.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index d44d0e6..5691618 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -50,11 +50,16 @@ static const struct renesas_family fam_rza __initconst __maybe_unused = {
 	.name	= "RZ/A",
 };
 
-static const struct renesas_family fam_rzg __initconst __maybe_unused = {
-	.name	= "RZ/G",
+static const struct renesas_family fam_rzg1 __initconst __maybe_unused = {
+	.name	= "RZ/G1",
 	.reg	= 0xff000044,		/* PRR (Product Register) */
 };
 
+static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
+	.name	= "RZ/G2",
+	.reg	= 0xfff00044,		/* PRR (Product Register) */
+};
+
 static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
 	.name	= "SH-Mobile",
 	.reg	= 0xe600101c,		/* CCCR (Common Chip Code Register) */
@@ -81,30 +86,35 @@ static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = {
 };
 
 static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = {
-	.family	= &fam_rzg,
+	.family	= &fam_rzg1,
 	.id	= 0x45,
 };
 
 static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
-	.family	= &fam_rzg,
+	.family	= &fam_rzg1,
 	.id	= 0x47,
 };
 
 static const struct renesas_soc soc_rz_g1n __initconst __maybe_unused = {
-	.family	= &fam_rzg,
+	.family	= &fam_rzg1,
 	.id	= 0x4b,
 };
 
 static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
-	.family	= &fam_rzg,
+	.family	= &fam_rzg1,
 	.id	= 0x4c,
 };
 
 static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
-	.family	= &fam_rzg,
+	.family	= &fam_rzg1,
 	.id	= 0x53,
 };
 
+static const struct renesas_soc soc_rz_g2m __initconst __maybe_unused = {
+	.family	= &fam_rzg2,
+	.id	= 0x52,
+};
+
 static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
 	.family	= &fam_rcar_gen1,
 };
@@ -205,6 +215,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
 #ifdef CONFIG_ARCH_R8A77470
 	{ .compatible = "renesas,r8a77470",	.data = &soc_rz_g1c },
 #endif
+#ifdef CONFIG_ARCH_R8A774A1
+	{ .compatible = "renesas,r8a774a1",	.data = &soc_rz_g2m },
+#endif
 #ifdef CONFIG_ARCH_R8A7778
 	{ .compatible = "renesas,r8a7778",	.data = &soc_rcar_m1a },
 #endif
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 05/18] soc: renesas: Identify RZ/G2E
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (3 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 04/18] soc: renesas: Identify RZ/G2M Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 06/18] arm64: Add Renesas R8A774A1 support Biju Das
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add support for identifying the RZ/G2E (r8a774c0) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 2bab3d8012ebc463b899ee2c9292bd9282d75257)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/soc/renesas/renesas-soc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 5691618..d9b8485 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -115,6 +115,11 @@ static const struct renesas_soc soc_rz_g2m __initconst __maybe_unused = {
 	.id	= 0x52,
 };
 
+static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = {
+	.family	= &fam_rzg2,
+	.id	= 0x57,
+};
+
 static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
 	.family	= &fam_rcar_gen1,
 };
@@ -218,6 +223,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
 #ifdef CONFIG_ARCH_R8A774A1
 	{ .compatible = "renesas,r8a774a1",	.data = &soc_rz_g2m },
 #endif
+#ifdef CONFIG_ARCH_R8A774C0
+	{ .compatible = "renesas,r8a774c0",	.data = &soc_rz_g2e },
+#endif
 #ifdef CONFIG_ARCH_R8A7778
 	{ .compatible = "renesas,r8a7778",	.data = &soc_rcar_m1a },
 #endif
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 06/18] arm64: Add Renesas R8A774A1 support
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (4 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 05/18] soc: renesas: Identify RZ/G2E Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 07/18] arm64: Add Renesas R8A774C0 support Biju Das
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

Add configuration option for the RZ/G2M (R8A774A1) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 5afa67792d0a25d5642cd6929ed0f92b5e7f5076)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/Kconfig.platforms | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 393d2b5..531ea50 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -186,6 +186,12 @@ config ARCH_RENESAS
 	help
 	  This enables support for the ARMv8 based Renesas SoCs.
 
+config ARCH_R8A774A1
+	bool "Renesas RZ/G2M SoC Platform"
+	depends on ARCH_RENESAS
+	help
+	  This enables support for the Renesas RZ/G2M SoC.
+
 config ARCH_R8A7795
 	bool "Renesas R-Car H3 SoC Platform"
 	depends on ARCH_RENESAS
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 07/18] arm64: Add Renesas R8A774C0 support
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (5 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 06/18] arm64: Add Renesas R8A774A1 support Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 08/18] arm64: defconfig: enable R8A774A1 SoC Biju Das
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add configuration option for the RZ/G2E (R8A774C0) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 692dce77dfb71b5eaf896d3cdc7ef72f70631b14)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/Kconfig.platforms | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 531ea50..71ae51d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -192,6 +192,12 @@ config ARCH_R8A774A1
 	help
 	  This enables support for the Renesas RZ/G2M SoC.
 
+config ARCH_R8A774C0
+	bool "Renesas RZ/G2E SoC Platform"
+	depends on ARCH_RENESAS
+	help
+	  This enables support for the Renesas RZ/G2E SoC.
+
 config ARCH_R8A7795
 	bool "Renesas R-Car H3 SoC Platform"
 	depends on ARCH_RENESAS
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 08/18] arm64: defconfig: enable R8A774A1 SoC
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (6 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 07/18] arm64: Add Renesas R8A774C0 support Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC Biju Das
                   ` (9 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 defconfig.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 48acc8440a78596384881ba773e47d55c4de2ebc)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index db8d364..3f1868c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,6 +50,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SEATTLE=y
 CONFIG_ARCH_SYNQUACER=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A774A1=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77965=y
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (7 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 08/18] arm64: defconfig: enable R8A774A1 SoC Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Enable the Renesas RZ/G2E (R8A774C0) SoC in the ARM64 defconfig.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 76506880eac66cb1f189a993c39ad0fcba723b99)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3f1868c..e6ec985 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y
 CONFIG_ARCH_SYNQUACER=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774C0=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77965=y
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (8 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 11/18] dt-bindings: power: Add r8a774c0 " Biju Das
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

This patch adds power domain indices for RZ/G2M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 066f7e63b9ed0badffc32bcf135e59658b423999)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 include/dt-bindings/power/r8a774a1-sysc.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h

diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
new file mode 100644
index 0000000..580f431
--- /dev/null
+++ b/include/dt-bindings/power/r8a774a1-sysc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A1_PD_CA57_CPU0		 0
+#define R8A774A1_PD_CA57_CPU1		 1
+#define R8A774A1_PD_CA53_CPU0		 5
+#define R8A774A1_PD_CA53_CPU1		 6
+#define R8A774A1_PD_CA53_CPU2		 7
+#define R8A774A1_PD_CA53_CPU3		 8
+#define R8A774A1_PD_CA57_SCU		12
+#define R8A774A1_PD_A3VC		14
+#define R8A774A1_PD_3DG_A		17
+#define R8A774A1_PD_3DG_B		18
+#define R8A774A1_PD_CA53_SCU		21
+#define R8A774A1_PD_A2VC0		25
+#define R8A774A1_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774A1_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 11/18] dt-bindings: power: Add r8a774c0 SYSC power domain definitions
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (9 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 12/18] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

This patch adds power domain indices for RZ/G2E.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit cb391265bca42f17c59d90e842a6bc582e3e2211)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 include/dt-bindings/power/r8a774c0-sysc.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a774c0-sysc.h

diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h
new file mode 100644
index 0000000..9922d4c
--- /dev/null
+++ b/include/dt-bindings/power/r8a774c0-sysc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774C0_PD_CA53_CPU0		5
+#define R8A774C0_PD_CA53_CPU1		6
+#define R8A774C0_PD_A3VC		14
+#define R8A774C0_PD_3DG_A		17
+#define R8A774C0_PD_3DG_B		18
+#define R8A774C0_PD_CA53_SCU		21
+#define R8A774C0_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774C0_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 12/18] soc: renesas: rcar-sysc: Add r8a774a1 support
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (10 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 11/18] dt-bindings: power: Add r8a774c0 " Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc Biju Das
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 7f0e99cc916933ecd7fd407e2eb42448198e0404)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 .../bindings/power/renesas,rcar-sysc.txt           |  1 +
 drivers/soc/renesas/Kconfig                        |  5 +++
 drivers/soc/renesas/Makefile                       |  1 +
 drivers/soc/renesas/r8a774a1-sysc.c                | 45 ++++++++++++++++++++++
 drivers/soc/renesas/rcar-sysc.c                    |  3 ++
 drivers/soc/renesas/rcar-sysc.h                    |  1 +
 6 files changed, 56 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 180ae65..4e3ec6a 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -10,6 +10,7 @@ Required properties:
       - "renesas,r8a7743-sysc" (RZ/G1M)
       - "renesas,r8a7745-sysc" (RZ/G1E)
       - "renesas,r8a77470-sysc" (RZ/G1C)
+      - "renesas,r8a774a1-sysc" (RZ/G2M)
       - "renesas,r8a7779-sysc" (R-Car H1)
       - "renesas,r8a7790-sysc" (R-Car H2)
       - "renesas,r8a7791-sysc" (R-Car M2-W)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1d824cb..d769330 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -9,6 +9,7 @@ config SOC_RENESAS
 	select SYSC_R8A7743 if ARCH_R8A7743
 	select SYSC_R8A7745 if ARCH_R8A7745
 	select SYSC_R8A77470 if ARCH_R8A77470
+	select SYSC_R8A774A1 if ARCH_R8A774A1
 	select SYSC_R8A7779 if ARCH_R8A7779
 	select SYSC_R8A7790 if ARCH_R8A7790
 	select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -37,6 +38,10 @@ config SYSC_R8A77470
 	bool "RZ/G1C System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
 
+config SYSC_R8A774A1
+	bool "RZ/G2M System Controller support" if COMPILE_TEST
+	select SYSC_RCAR
+
 config SYSC_R8A7779
 	bool "R-Car H1 System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index c37b080..6adb9d6 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS)	+= renesas-soc.o
 obj-$(CONFIG_SYSC_R8A7743)	+= r8a7743-sysc.o
 obj-$(CONFIG_SYSC_R8A7745)	+= r8a7745-sysc.o
 obj-$(CONFIG_SYSC_R8A77470)	+= r8a77470-sysc.o
+obj-$(CONFIG_SYSC_R8A774A1)	+= r8a774a1-sysc.o
 obj-$(CONFIG_SYSC_R8A7779)	+= r8a7779-sysc.o
 obj-$(CONFIG_SYSC_R8A7790)	+= r8a7790-sysc.o
 obj-$(CONFIG_SYSC_R8A7791)	+= r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a774a1-sysc.c b/drivers/soc/renesas/r8a774a1-sysc.c
new file mode 100644
index 0000000..9db51ff
--- /dev/null
+++ b/drivers/soc/renesas/r8a774a1-sysc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2M System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car M3-W System Controller
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a774a1-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
+	{ "always-on",	    0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+	{ "ca57-scu",	0x1c0, 0, R8A774A1_PD_CA57_SCU,	R8A774A1_PD_ALWAYS_ON,
+	  PD_SCU },
+	{ "ca57-cpu0",	 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
+	  PD_CPU_NOCR },
+	{ "ca57-cpu1",	 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
+	  PD_CPU_NOCR },
+	{ "ca53-scu",	0x140, 0, R8A774A1_PD_CA53_SCU,	R8A774A1_PD_ALWAYS_ON,
+	  PD_SCU },
+	{ "ca53-cpu0",	0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "ca53-cpu1",	0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "ca53-cpu2",	0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "ca53-cpu3",	0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "a3vc",	0x380, 0, R8A774A1_PD_A3VC,	R8A774A1_PD_ALWAYS_ON },
+	{ "a2vc0",	0x3c0, 0, R8A774A1_PD_A2VC0,	R8A774A1_PD_A3VC },
+	{ "a2vc1",	0x3c0, 1, R8A774A1_PD_A2VC1,	R8A774A1_PD_A3VC },
+	{ "3dg-a",	0x100, 0, R8A774A1_PD_3DG_A,	R8A774A1_PD_ALWAYS_ON },
+	{ "3dg-b",	0x100, 1, R8A774A1_PD_3DG_B,	R8A774A1_PD_3DG_A },
+};
+
+const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
+	.areas = r8a774a1_areas,
+	.num_areas = ARRAY_SIZE(r8a774a1_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 029188e..fe32f7a 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -275,6 +275,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
 #ifdef CONFIG_SYSC_R8A77470
 	{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
 #endif
+#ifdef CONFIG_SYSC_R8A774A1
+	{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
+#endif
 #ifdef CONFIG_SYSC_R8A7779
 	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
 #endif
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index a22e7cf..33defe6 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -52,6 +52,7 @@ struct rcar_sysc_info {
 extern const struct rcar_sysc_info r8a7743_sysc_info;
 extern const struct rcar_sysc_info r8a7745_sysc_info;
 extern const struct rcar_sysc_info r8a77470_sysc_info;
+extern const struct rcar_sysc_info r8a774a1_sysc_info;
 extern const struct rcar_sysc_info r8a7779_sysc_info;
 extern const struct rcar_sysc_info r8a7790_sysc_info;
 extern const struct rcar_sysc_info r8a7791_sysc_info;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (11 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 12/18] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 14/18] soc: renesas: rcar-sysc: Add r8a774c0 support Biju Das
                   ` (4 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Document bindings for the RZ/G2E (a.k.a. R8A774C0) system
controller.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 39dc9a103bc587d32a0416c5a47483a6e9ef88e2)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 4e3ec6a..4cb97d4 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -11,6 +11,7 @@ Required properties:
       - "renesas,r8a7745-sysc" (RZ/G1E)
       - "renesas,r8a77470-sysc" (RZ/G1C)
       - "renesas,r8a774a1-sysc" (RZ/G2M)
+      - "renesas,r8a774c0-sysc" (RZ/G2E)
       - "renesas,r8a7779-sysc" (R-Car H1)
       - "renesas,r8a7790-sysc" (R-Car H2)
       - "renesas,r8a7791-sysc" (R-Car M2-W)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 14/18] soc: renesas: rcar-sysc: Add r8a774c0 support
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (12 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B} Biju Das
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add support for the RZ/G2E (R8A774C0) SoC power areas to the
R-Car SYSC driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit f37d211c687588328c083f4523c4a26620dc5bb6)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig         |  5 +++
 drivers/soc/renesas/Makefile        |  1 +
 drivers/soc/renesas/r8a774c0-sysc.c | 68 +++++++++++++++++++++++++++++++++++++
 drivers/soc/renesas/rcar-sysc.c     |  3 ++
 drivers/soc/renesas/rcar-sysc.h     |  1 +
 5 files changed, 78 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a774c0-sysc.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index d769330..e50e77c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -10,6 +10,7 @@ config SOC_RENESAS
 	select SYSC_R8A7745 if ARCH_R8A7745
 	select SYSC_R8A77470 if ARCH_R8A77470
 	select SYSC_R8A774A1 if ARCH_R8A774A1
+	select SYSC_R8A774C0 if ARCH_R8A774C0
 	select SYSC_R8A7779 if ARCH_R8A7779
 	select SYSC_R8A7790 if ARCH_R8A7790
 	select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -42,6 +43,10 @@ config SYSC_R8A774A1
 	bool "RZ/G2M System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
 
+config SYSC_R8A774C0
+	bool "RZ/G2E System Controller support" if COMPILE_TEST
+	select SYSC_RCAR
+
 config SYSC_R8A7779
 	bool "R-Car H1 System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 6adb9d6..3bdd7db 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SYSC_R8A7743)	+= r8a7743-sysc.o
 obj-$(CONFIG_SYSC_R8A7745)	+= r8a7745-sysc.o
 obj-$(CONFIG_SYSC_R8A77470)	+= r8a77470-sysc.o
 obj-$(CONFIG_SYSC_R8A774A1)	+= r8a774a1-sysc.o
+obj-$(CONFIG_SYSC_R8A774C0)	+= r8a774c0-sysc.o
 obj-$(CONFIG_SYSC_R8A7779)	+= r8a7779-sysc.o
 obj-$(CONFIG_SYSC_R8A7790)	+= r8a7790-sysc.o
 obj-$(CONFIG_SYSC_R8A7791)	+= r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a774c0-sysc.c b/drivers/soc/renesas/r8a774c0-sysc.c
new file mode 100644
index 0000000..e1ac4c0
--- /dev/null
+++ b/drivers/soc/renesas/r8a774c0-sysc.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2E System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car E3 System Controller
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/power/r8a774c0-sysc.h>
+
+#include "rcar-sysc.h"
+
+static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
+	{ "always-on",	    0, 0, R8A774C0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+	{ "ca53-scu",	0x140, 0, R8A774C0_PD_CA53_SCU,  R8A774C0_PD_ALWAYS_ON,
+	  PD_SCU },
+	{ "ca53-cpu0",	0x200, 0, R8A774C0_PD_CA53_CPU0, R8A774C0_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "ca53-cpu1",	0x200, 1, R8A774C0_PD_CA53_CPU1, R8A774C0_PD_CA53_SCU,
+	  PD_CPU_NOCR },
+	{ "a3vc",	0x380, 0, R8A774C0_PD_A3VC,	R8A774C0_PD_ALWAYS_ON },
+	{ "a2vc1",	0x3c0, 1, R8A774C0_PD_A2VC1,	R8A774C0_PD_A3VC },
+	{ "3dg-a",	0x100, 0, R8A774C0_PD_3DG_A,	R8A774C0_PD_ALWAYS_ON },
+	{ "3dg-b",	0x100, 1, R8A774C0_PD_3DG_B,	R8A774C0_PD_3DG_A },
+};
+
+static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
+					unsigned int num_areas, u8 id,
+					int new_parent)
+{
+	unsigned int i;
+
+	for (i = 0; i < num_areas; i++)
+		if (areas[i].isr_bit == id) {
+			areas[i].parent = new_parent;
+			return;
+		}
+}
+
+/* Fixups for RZ/G2E ES1.0 revision */
+static const struct soc_device_attribute r8a774c0[] __initconst = {
+	{ .soc_id = "r8a774c0", .revision = "ES1.0" },
+	{ /* sentinel */ }
+};
+
+static int __init r8a774c0_sysc_init(void)
+{
+	if (soc_device_match(r8a774c0)) {
+		rcar_sysc_fix_parent(r8a774c0_areas,
+				     ARRAY_SIZE(r8a774c0_areas),
+				     R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
+		rcar_sysc_fix_parent(r8a774c0_areas,
+				     ARRAY_SIZE(r8a774c0_areas),
+				     R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
+	}
+
+	return 0;
+}
+
+const struct rcar_sysc_info r8a774c0_sysc_info __initconst = {
+	.init = r8a774c0_sysc_init,
+	.areas = r8a774c0_areas,
+	.num_areas = ARRAY_SIZE(r8a774c0_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index fe32f7a..e63d7a2 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -278,6 +278,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
 #ifdef CONFIG_SYSC_R8A774A1
 	{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
 #endif
+#ifdef CONFIG_SYSC_R8A774C0
+	{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
+#endif
 #ifdef CONFIG_SYSC_R8A7779
 	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
 #endif
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 33defe6..dc71f49 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -53,6 +53,7 @@ extern const struct rcar_sysc_info r8a7743_sysc_info;
 extern const struct rcar_sysc_info r8a7745_sysc_info;
 extern const struct rcar_sysc_info r8a77470_sysc_info;
 extern const struct rcar_sysc_info r8a774a1_sysc_info;
+extern const struct rcar_sysc_info r8a774c0_sysc_info;
 extern const struct rcar_sysc_info r8a7779_sysc_info;
 extern const struct rcar_sysc_info r8a7790_sysc_info;
 extern const struct rcar_sysc_info r8a7791_sysc_info;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B}
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (13 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 14/18] soc: renesas: rcar-sysc: Add r8a774c0 support Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-04-09 19:49   ` Pavel Machek
  2019-03-21 14:24 ` [cip-dev] [PATCH 16/18] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das
                   ` (2 subsequent siblings)
  17 siblings, 1 reply; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

The workaround for the wrong hierarchy of the 3DG-{A,B} power domains on
RZ/G2E ES1.0 corrected the parent domains. However, the 3DG-{A,B} power
domains were still initialized and powered in the wrong order, causing
3DG operation to fail.

Fix this by changing the order in the table at runtime, when running on
an affected SoC.

This work is based on the work done by Geert for R-Car E3.

Fixes: f37d211c687588328 ("soc: renesas: rcar-sysc: Add r8a774c0 support")

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a64597227d0de5610407fcc95dc835745a53f5d0)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/soc/renesas/r8a774c0-sysc.c | 23 ++++-------------------
 1 file changed, 4 insertions(+), 19 deletions(-)

diff --git a/drivers/soc/renesas/r8a774c0-sysc.c b/drivers/soc/renesas/r8a774c0-sysc.c
index e1ac4c0..11050e1 100644
--- a/drivers/soc/renesas/r8a774c0-sysc.c
+++ b/drivers/soc/renesas/r8a774c0-sysc.c
@@ -28,19 +28,6 @@ static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
 	{ "3dg-b",	0x100, 1, R8A774C0_PD_3DG_B,	R8A774C0_PD_3DG_A },
 };
 
-static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
-					unsigned int num_areas, u8 id,
-					int new_parent)
-{
-	unsigned int i;
-
-	for (i = 0; i < num_areas; i++)
-		if (areas[i].isr_bit == id) {
-			areas[i].parent = new_parent;
-			return;
-		}
-}
-
 /* Fixups for RZ/G2E ES1.0 revision */
 static const struct soc_device_attribute r8a774c0[] __initconst = {
 	{ .soc_id = "r8a774c0", .revision = "ES1.0" },
@@ -50,12 +37,10 @@ static const struct soc_device_attribute r8a774c0[] __initconst = {
 static int __init r8a774c0_sysc_init(void)
 {
 	if (soc_device_match(r8a774c0)) {
-		rcar_sysc_fix_parent(r8a774c0_areas,
-				     ARRAY_SIZE(r8a774c0_areas),
-				     R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
-		rcar_sysc_fix_parent(r8a774c0_areas,
-				     ARRAY_SIZE(r8a774c0_areas),
-				     R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
+		/* Fix incorrect 3DG hierarchy */
+		swap(r8a774c0_areas[6], r8a774c0_areas[7]);
+		r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
+		r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
 	}
 
 	return 0;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 16/18] soc: renesas: rcar-rst: Add support for RZ/G2M
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (14 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B} Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 18/18] soc: renesas: rcar-rst: Add support for RZ/G2E Biju Das
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 3116d859e7b15d3740afd44c975cdb34a4c1246e)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
 drivers/soc/renesas/Kconfig                             | 6 +++---
 drivers/soc/renesas/rcar-rst.c                          | 4 +++-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index 67e83b0..e4fe0ab 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -18,6 +18,7 @@ Required properties:
 		  - "renesas,r8a7743-rst" (RZ/G1M)
 		  - "renesas,r8a7745-rst" (RZ/G1E)
 		  - "renesas,r8a77470-rst" (RZ/G1C)
+		  - "renesas,r8a774a1-rst" (RZ/G2M)
 		  - "renesas,r8a7778-reset-wdt" (R-Car M1A)
 		  - "renesas,r8a7779-reset-wdt" (R-Car H1)
 		  - "renesas,r8a7790-rst" (R-Car H2)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index e50e77c..163e666 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,9 +3,9 @@ config SOC_RENESAS
 	default y if ARCH_RENESAS
 	select SOC_BUS
 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
-			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
-			   ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \
-			   ARCH_R8A77995
+			   ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \
+			   ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \
+			   ARCH_R8A77990 || ARCH_R8A77995
 	select SYSC_R8A7743 if ARCH_R8A7743
 	select SYSC_R8A7745 if ARCH_R8A7745
 	select SYSC_R8A77470 if ARCH_R8A77470
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index d9c1034..a447873 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -41,10 +41,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
 };
 
 static const struct of_device_id rcar_rst_matches[] __initconst = {
-	/* RZ/G is handled like R-Car Gen2 */
+	/* RZ/G1 is handled like R-Car Gen2 */
 	{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
 	{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
 	{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
+	/* RZ/G2 is handled like R-Car Gen3 */
+	{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
 	/* R-Car Gen1 */
 	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
 	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (15 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 16/18] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das
@ 2019-03-21 14:24 ` Biju Das
  2019-03-21 14:24 ` [cip-dev] [PATCH 18/18] soc: renesas: rcar-rst: Add support for RZ/G2E Biju Das
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Document bindings for the RZ/G2E (a.k.a. R8A774C0) reset
module.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit fe46b8229f287e912b8c8d28bf8dde4cd704c17e)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index e4fe0ab..25e6db5 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -19,6 +19,7 @@ Required properties:
 		  - "renesas,r8a7745-rst" (RZ/G1E)
 		  - "renesas,r8a77470-rst" (RZ/G1C)
 		  - "renesas,r8a774a1-rst" (RZ/G2M)
+		  - "renesas,r8a774c0-rst" (RZ/G2E)
 		  - "renesas,r8a7778-reset-wdt" (R-Car M1A)
 		  - "renesas,r8a7779-reset-wdt" (R-Car H1)
 		  - "renesas,r8a7790-rst" (R-Car H2)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 18/18] soc: renesas: rcar-rst: Add support for RZ/G2E
  2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
                   ` (16 preceding siblings ...)
  2019-03-21 14:24 ` [cip-dev] [PATCH 17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst Biju Das
@ 2019-03-21 14:24 ` Biju Das
  17 siblings, 0 replies; 20+ messages in thread
From: Biju Das @ 2019-03-21 14:24 UTC (permalink / raw)
  To: cip-dev

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 91e95ecd4b4ff35624ac48bdf6dcf2d855f0b63e)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig    | 6 +++---
 drivers/soc/renesas/rcar-rst.c | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 163e666..614d767 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,9 +3,9 @@ config SOC_RENESAS
 	default y if ARCH_RENESAS
 	select SOC_BUS
 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
-			   ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \
-			   ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \
-			   ARCH_R8A77990 || ARCH_R8A77995
+			   ARCH_R8A774A1 || ARCH_R8A774C0 || ARCH_R8A7795 || \
+			   ARCH_R8A7796 || ARCH_R8A77965 || ARCH_R8A77970 || \
+			   ARCH_R8A77980 || ARCH_R8A77990 || ARCH_R8A77995
 	select SYSC_R8A7743 if ARCH_R8A7743
 	select SYSC_R8A7745 if ARCH_R8A7745
 	select SYSC_R8A77470 if ARCH_R8A77470
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index a447873..d5e31f4 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -47,6 +47,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
 	{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
 	/* RZ/G2 is handled like R-Car Gen3 */
 	{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
+	{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
 	/* R-Car Gen1 */
 	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
 	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B}
  2019-03-21 14:24 ` [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B} Biju Das
@ 2019-04-09 19:49   ` Pavel Machek
  0 siblings, 0 replies; 20+ messages in thread
From: Pavel Machek @ 2019-04-09 19:49 UTC (permalink / raw)
  To: cip-dev

On Thu 2019-03-21 14:24:13, Biju Das wrote:
> The workaround for the wrong hierarchy of the 3DG-{A,B} power domains on
> RZ/G2E ES1.0 corrected the parent domains. However, the 3DG-{A,B} power
> domains were still initialized and powered in the wrong order, causing
> 3DG operation to fail.
> 
> Fix this by changing the order in the table at runtime, when running on
> an affected SoC.
> 
> This work is based on the work done by Geert for R-Car E3.
> 
> Fixes: f37d211c687588328 ("soc: renesas: rcar-sysc: Add r8a774c0 support")

I prefer directly including good commit (rather than including bad commit and
then fixing it up). Let me try to fix it up.

Anyway, I merged this and the rest of the series.

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2019-04-09 19:49 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-21 14:23 [cip-dev] [PATCH 00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support Biju Das
2019-03-21 14:23 ` [cip-dev] [PATCH 01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 02/18] dt-bindings: arm: Document RZ/G2E " Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 03/18] dt-bindings: arm: Fix RZ/G2E part number Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 04/18] soc: renesas: Identify RZ/G2M Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 05/18] soc: renesas: Identify RZ/G2E Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 06/18] arm64: Add Renesas R8A774A1 support Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 07/18] arm64: Add Renesas R8A774C0 support Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 08/18] arm64: defconfig: enable R8A774A1 SoC Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 11/18] dt-bindings: power: Add r8a774c0 " Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 12/18] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 14/18] soc: renesas: rcar-sysc: Add r8a774c0 support Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B} Biju Das
2019-04-09 19:49   ` Pavel Machek
2019-03-21 14:24 ` [cip-dev] [PATCH 16/18] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst Biju Das
2019-03-21 14:24 ` [cip-dev] [PATCH 18/18] soc: renesas: rcar-rst: Add support for RZ/G2E Biju Das

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