[U-Boot] [PATCH v2 0/6] Update Stratix 10 SDRAM driver

[U-Boot] [PATCH v2 0/6] Update Stratix 10 SDRAM driver

[Marek Vasut]

On 3/21/19 6:23 PM, Ley Foon Tan wrote:
> This patchset update Stratix 10 SDRAM driver to support:
> - Multi-banks memory
>   - Stratix 10 support up to 2 memory banks:
> 	Bank 0: Address 0, size 2GB
> 	Bank 1: Address 0x100000000, size 124GB
> - Add warm reset boot checking function (Patch[5])
> - Add ECC memory scrubbing support (Patch [6])
>   - Use cache enabled + "DC ZVA" instruction to clear memory to zeros
> 
> v1 -> v2:
> ---------
> - Decode memory bank configuration from device tree
> - Use asm volatile() and "memory" clobber
> 
> History:
> --------
> v1: https://patchwork.ozlabs.org/cover/1055134/
> 
> Ley Foon Tan (6):
>   ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
>   ddr: altera: Stratix10: Add multi-banks DRAM size check
>   configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2
>   arm: dts: Stratix10: Modify stratix10 socdk memory node
>   arm: socfpga: stratix10: Add cpu_has_been_warmreset()
>   ddr: altera: Stratix10: Add ECC memory scrubbing
> 
>  arch/arm/dts/socfpga_stratix10_socdk.dts      |   4 +-
>  .../include/mach/reset_manager_s10.h          |   3 +
>  .../arm/mach-socfpga/include/mach/sdram_s10.h |   9 ++
>  arch/arm/mach-socfpga/reset_manager_s10.c     |   9 ++
>  arch/arm/mach-socfpga/spl_s10.c               |  11 --
>  configs/socfpga_stratix10_defconfig           |   2 +-
>  drivers/ddr/altera/sdram_s10.c                | 136 +++++++++++++++++-
>  7 files changed, 159 insertions(+), 15 deletions(-)
> 
Applied all to socfpga/next, thanks

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 0/6] Update Stratix 10 SDRAM driver

[Ley Foon Tan]

This patchset update Stratix 10 SDRAM driver to support:
- Multi-banks memory
  - Stratix 10 support up to 2 memory banks:
	Bank 0: Address 0, size 2GB
	Bank 1: Address 0x100000000, size 124GB
- Add warm reset boot checking function (Patch[5])
- Add ECC memory scrubbing support (Patch [6])
  - Use cache enabled + "DC ZVA" instruction to clear memory to zeros

v1 -> v2:
---------
- Decode memory bank configuration from device tree
- Use asm volatile() and "memory" clobber

History:
--------
v1: https://patchwork.ozlabs.org/cover/1055134/

Ley Foon Tan (6):
  ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
  ddr: altera: Stratix10: Add multi-banks DRAM size check
  configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2
  arm: dts: Stratix10: Modify stratix10 socdk memory node
  arm: socfpga: stratix10: Add cpu_has_been_warmreset()
  ddr: altera: Stratix10: Add ECC memory scrubbing

 arch/arm/dts/socfpga_stratix10_socdk.dts      |   4 +-
 .../include/mach/reset_manager_s10.h          |   3 +
 .../arm/mach-socfpga/include/mach/sdram_s10.h |   9 ++
 arch/arm/mach-socfpga/reset_manager_s10.c     |   9 ++
 arch/arm/mach-socfpga/spl_s10.c               |  11 --
 configs/socfpga_stratix10_defconfig           |   2 +-
 drivers/ddr/altera/sdram_s10.c                | 136 +++++++++++++++++-
 7 files changed, 159 insertions(+), 15 deletions(-)

-- 
2.19.0

[U-Boot] [PATCH v2 1/6] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

[Ley Foon Tan]

Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/spl_s10.c | 11 -----------
 drivers/ddr/altera/sdram_s10.c  | 15 +++++++++++++++
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a3db20a819..a141ffe82a 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	gd->ram_size = sdram_calculate_size();
-	printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
-
-	/* Sanity check ensure correct SDRAM size specified */
-	debug("DDR: Running SDRAM size sanity check\n");
-	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
-		puts("DDR: SDRAM size check failed!\n");
-		hang();
-	}
-	debug("DDR: SDRAM size check passed!\n");
-
 	mbox_init();
 
 #ifdef CONFIG_CADENCE_QSPI
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index a48567c109..033ccca437 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
 				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 }
 
+static void sdram_size_check(void)
+{
+	/* Sanity check ensure correct SDRAM size specified */
+	debug("DDR: Running SDRAM size sanity check\n");
+	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+	debug("DDR: SDRAM size check passed!\n");
+}
+
 /**
  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  *
@@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
 	else
 		gd->ram_size = size;
 
+	printf("DDR: %lld MiB\n", gd->ram_size >> 20);
+
 	/* Enable or disable the SDRAM ECC */
 	if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 		setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
@@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 	}
 
+	sdram_size_check();
+
 	debug("DDR: HMC init success\n");
 	return 0;
 }
-- 
2.19.0

[U-Boot] [PATCH v2 2/6] ddr: altera: Stratix10: Add multi-banks DRAM size check

[Ley Foon Tan]

Stratix 10 maps dram from 0 to 128GB.  There is a 2GB hole
in the memory for peripherals and other IO from 2GB to 4GB.
However the dram controller ignores upper address bits for
smaller dram configurations.  Example: a 4GB dram
maps to multiple locations, every 4GB on the address.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 drivers/ddr/altera/sdram_s10.c | 46 ++++++++++++++++++++++++++++++----
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 033ccca437..462c8feaef 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -7,12 +7,14 @@
 #include <common.h>
 #include <errno.h>
 #include <div64.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <wait_bit.h>
 #include <asm/arch/firewall_s10.h>
 #include <asm/arch/sdram_s10.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/reset_manager.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -134,14 +136,35 @@ static int poll_hmc_clock_status(void)
 				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 }
 
-static void sdram_size_check(void)
+static void sdram_size_check(bd_t *bd)
 {
+	phys_size_t total_ram_check = 0;
+	phys_size_t ram_check = 0;
+	phys_addr_t start = 0;
+	int bank;
+
 	/* Sanity check ensure correct SDRAM size specified */
 	debug("DDR: Running SDRAM size sanity check\n");
-	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start = bd->bi_dram[bank].start;
+		while (ram_check < bd->bi_dram[bank].size) {
+			ram_check += get_ram_size((void *)(start + ram_check),
+						 (phys_size_t)SZ_1G);
+		}
+		total_ram_check += ram_check;
+		ram_check = 0;
+	}
+
+	/* If the ram_size is 2GB smaller, we can assume the IO space is
+	 * not mapped in.  gd->ram_size is the actual size of the dram
+	 * not the accessible size.
+	 */
+	if (total_ram_check != gd->ram_size) {
 		puts("DDR: SDRAM size check failed!\n");
 		hang();
 	}
+
 	debug("DDR: SDRAM size check passed!\n");
 }
 
@@ -155,6 +178,8 @@ int sdram_mmr_init_full(unsigned int unused)
 	u32 update_value, io48_value, ddrioctl;
 	u32 i;
 	int ret;
+	phys_size_t hw_size;
+	bd_t bd = {0};
 
 	/* Enable access to DDR from CPU master */
 	clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
@@ -346,9 +371,20 @@ int sdram_mmr_init_full(unsigned int unused)
 	unsigned long long size = sdram_calculate_size();
 	/* If the size is invalid, use default Config size */
 	if (size <= 0)
-		gd->ram_size = PHYS_SDRAM_1_SIZE;
+		hw_size = PHYS_SDRAM_1_SIZE;
 	else
-		gd->ram_size = size;
+		hw_size = size;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, &bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		return -1;
+	}
+
+	if (gd->ram_size != hw_size)
+		printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 
 	printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 
@@ -374,7 +410,7 @@ int sdram_mmr_init_full(unsigned int unused)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 	}
 
-	sdram_size_check();
+	sdram_size_check(&bd);
 
 	debug("DDR: HMC init success\n");
 	return 0;
-- 
2.19.0

[U-Boot] [PATCH v2 3/6] configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2

[Ley Foon Tan]

Stratix10 maps dram in 2 address spans, from 0-2GB and from
2GB up to 128GB.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 configs/socfpga_stratix10_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 9e6d582ee3..4a14ea039e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -6,7 +6,7 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
 CONFIG_SPL=y
 CONFIG_IDENT_STRING="socfpga_stratix10"
 CONFIG_SPL_FS_FAT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
-- 
2.19.0

[U-Boot] [PATCH v2 4/6] arm: dts: Stratix10: Modify stratix10 socdk memory node

[Ley Foon Tan]

The stratix10 socdk ships with 4GB of memory.  Modify the
device tree to represent this.  Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size.  This means that
, the 4GB DRAM is mapped to memory every 4GB.

For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:

Loose 2GB of memory:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* last 4GB */
                      <1 0x00000000 1 0x00000000>;
                u-boot,dm-pre-reloc;
        };


or to map it all:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* next 6GB */
                      <2 0x80000000 1 0x80000000>;
                u-boot,dm-pre-reloc;
        };

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/dts/socfpga_stratix10_socdk.dts | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index 6e8ddcd9f4..c59b77d829 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -36,7 +36,9 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0 0 0 0x80000000>; /* 2GB */
+		/* 4GB */
+		reg = <0 0x00000000 0 0x80000000>,
+		      <1 0x80000000 0 0x80000000>;
 		u-boot,dm-pre-reloc;
 	};
 };
-- 
2.19.0

[U-Boot] [PATCH v2 5/6] arm: socfpga: stratix10: Add cpu_has_been_warmreset()

[Ley Foon Tan]

Add helper function cpu_has_been_warmreset() to check
if CPU is from warm reset boot.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 3 +++
 arch/arm/mach-socfpga/reset_manager_s10.c              | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 31b73edabe..e186296791 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -9,6 +9,7 @@
 
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
 
 void socfpga_bridges_reset(int enable);
 
@@ -47,6 +48,8 @@ struct socfpga_reset_manager {
 #define RSTMGR_MPUMODRST_CORE0		0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
 #define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	0x000F0F00
 
 /*
  * Define a reset identifier, from which a permodrst bank ID
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index f176c38495..f8dd787cc6 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -103,3 +103,12 @@ void reset_deassert_peripherals_handoff(void)
 	writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
 	writel(0, &reset_manager_base->per0modrst);
 }
+
+/*
+ * Return non-zero if the CPU has been warm reset
+ */
+int cpu_has_been_warmreset(void)
+{
+	return readl(&reset_manager_base->status) &
+		RSTMGR_L4WD_MPU_WARMRESET_MASK;
+}
-- 
2.19.0

[U-Boot] [PATCH v2 6/6] ddr: altera: Stratix10: Add ECC memory scrubbing

[Ley Foon Tan]

Scrub memory content if ECC is enabled and it is not
from warm reset boot.

Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 .../arm/mach-socfpga/include/mach/sdram_s10.h |  9 +++
 drivers/ddr/altera/sdram_s10.c                | 81 +++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index ca68594445..f39206ca1e 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -22,6 +22,7 @@ int sdram_calibration_full(void);
 #define ECCCTRL1			0x100
 #define ECCCTRL2			0x104
 #define ERRINTEN			0x110
+#define ERRINTENS			0x114
 #define INTMODE				0x11c
 #define INTSTAT				0x120
 #define AUTOWB_CORRADDR			0x138
@@ -52,6 +53,10 @@ int sdram_calibration_full(void);
 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
 
+#define	DDR_HMC_ERRINTEN_INTMASK				\
+		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
+		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
 /* NOC DDR scheduler */
 #define DDR_SCH_ID_COREID		0
 #define DDR_SCH_ID_REVID		0x4
@@ -180,4 +185,8 @@ int sdram_calibration_full(void);
 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
 	(((x) >> 0) & 0xFF)
 
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+
 #endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 462c8feaef..e4d4a02ca2 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -23,6 +23,8 @@ static const struct socfpga_system_manager *sysmgr_regs =
 
 #define DDR_CONFIG(A, B, C, R)	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
+#define PGTABLE_OFF	0x4000
+
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
 	/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -136,6 +138,76 @@ static int poll_hmc_clock_status(void)
 				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 }
 
+static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+	phys_size_t i;
+
+	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
+		       addr);
+		hang();
+	}
+
+	if (size % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
+		       size);
+		hang();
+	}
+
+	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
+	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("dc zva, %0"
+		     :
+		     : "r"(addr)
+		     : "memory");
+		addr += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+static void sdram_init_ecc_bits(bd_t *bd)
+{
+	phys_size_t size, size_init;
+	phys_addr_t start_addr;
+	int bank = 0;
+	unsigned int start = get_timer(0);
+
+	icache_enable();
+
+	start_addr = bd->bi_dram[0].start;
+	size = bd->bi_dram[0].size;
+
+	/* Initialize small block for page table */
+	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
+	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+	size -= (PGTABLE_OFF + PGTABLE_SIZE);
+	dcache_enable();
+
+	while (1) {
+		while (size) {
+			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+			sdram_clear_mem(start_addr, size_init);
+			size -= size_init;
+			start_addr += size_init;
+			WATCHDOG_RESET();
+		}
+
+		bank++;
+		if (bank >= CONFIG_NR_DRAM_BANKS)
+			break;
+
+		start_addr = bd->bi_dram[bank].start;
+		size = bd->bi_dram[bank].size;
+	}
+
+	dcache_disable();
+	icache_disable();
+
+	printf("SDRAM-ECC: Initialized success with %d ms\n",
+	       (unsigned int)get_timer(start));
+}
+
 static void sdram_size_check(bd_t *bd)
 {
 	phys_size_t total_ram_check = 0;
@@ -400,6 +472,15 @@ int sdram_mmr_init_full(unsigned int unused)
 		setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+		writel(DDR_HMC_ERRINTEN_INTMASK,
+		       SOCFPGA_SDR_ADDRESS + ERRINTENS);
+
+		/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
+		writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
+		/* Initialize memory content if not from warm reset */
+		if (!cpu_has_been_warmreset())
+			sdram_init_ecc_bits(&bd);
 	} else {
 		clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
-- 
2.19.0