* [RFC PATCH] x86/xen/pmu: Use MSRs C001_020X instead of the legacy MSRs for Hygon
@ 2019-03-22 10:43 ` Pu Wen
0 siblings, 0 replies; 2+ messages in thread
From: Pu Wen @ 2019-03-22 10:43 UTC (permalink / raw)
To: boris.ostrovsky, jgross, bp, tglx, mingo, hpa, x86
Cc: linux-kernel, xen-devel, Pu Wen
The Hygon Dhyana processor supports MSRs C001_020X for the performance
monitor counter(PMC). There are six core performance events counters for
Dhyana but there are only four legacy PMC MSRs. So switching to use MSRs
C001_020X(compatible with the F15H ones) for Xen vPMU infrastructure on
Hygon platform.
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
arch/x86/xen/pmu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index e13b0b4..6480eed 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -92,11 +92,11 @@ static void xen_pmu_arch_init(void)
break;
}
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
- amd_num_counters = F10H_NUM_COUNTERS;
- amd_counters_base = MSR_K7_PERFCTR0;
- amd_ctrls_base = MSR_K7_EVNTSEL0;
- amd_msr_step = 1;
- k7_counters_mirrored = 0;
+ amd_num_counters = F15H_NUM_COUNTERS;
+ amd_counters_base = MSR_F15H_PERF_CTR;
+ amd_ctrls_base = MSR_F15H_PERF_CTL;
+ amd_msr_step = 2;
+ k7_counters_mirrored = 1;
} else {
uint32_t eax, ebx, ecx, edx;
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [RFC PATCH] x86/xen/pmu: Use MSRs C001_020X instead of the legacy MSRs for Hygon
@ 2019-03-22 10:43 ` Pu Wen
0 siblings, 0 replies; 2+ messages in thread
From: Pu Wen @ 2019-03-22 10:43 UTC (permalink / raw)
To: boris.ostrovsky, jgross, bp, tglx, mingo, hpa, x86
Cc: xen-devel, linux-kernel, Pu Wen
The Hygon Dhyana processor supports MSRs C001_020X for the performance
monitor counter(PMC). There are six core performance events counters for
Dhyana but there are only four legacy PMC MSRs. So switching to use MSRs
C001_020X(compatible with the F15H ones) for Xen vPMU infrastructure on
Hygon platform.
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
arch/x86/xen/pmu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index e13b0b4..6480eed 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -92,11 +92,11 @@ static void xen_pmu_arch_init(void)
break;
}
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
- amd_num_counters = F10H_NUM_COUNTERS;
- amd_counters_base = MSR_K7_PERFCTR0;
- amd_ctrls_base = MSR_K7_EVNTSEL0;
- amd_msr_step = 1;
- k7_counters_mirrored = 0;
+ amd_num_counters = F15H_NUM_COUNTERS;
+ amd_counters_base = MSR_F15H_PERF_CTR;
+ amd_ctrls_base = MSR_F15H_PERF_CTL;
+ amd_msr_step = 2;
+ k7_counters_mirrored = 1;
} else {
uint32_t eax, ebx, ecx, edx;
--
2.7.4
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^ permalink raw reply related [flat|nested] 2+ messages in thread
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2019-03-22 10:43 [RFC PATCH] x86/xen/pmu: Use MSRs C001_020X instead of the legacy MSRs for Hygon Pu Wen
2019-03-22 10:43 ` Pu Wen
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