[PATCH 0/6] clk: ti: a few OMAP clock fixes

[PATCH 0/6] clk: ti: a few OMAP clock fixes

[Tero Kristo]

Hi,

These patches fix a few issues with OMAP clock driver suite. They could
be merged as fixes, or just be postponed until next merge window. Depends
on the preference from Stephen / Tony really.

Fixes done:
- dropped CLK_IS_BASIC from mach-omap2 (Tony, can you ack patch #2? Depends
  on patch #1 so can't be merged standalone.)
- prevent non-existent clocks registering on both the cutdown SoCs (dra71)
  and HS devices

-Tero

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 1/6] clk: ti: export the omap2_clk_is_hw_omap call

[Tero Kristo]

There is one instance outside the TI clock driver that needs the info
whether a clock is an OMAP HW clock or not. Thus, move the function
declaration into the public header.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/clock.h | 1 -
 include/linux/clk/ti.h | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 1c0fac5..4223a39 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -303,7 +303,6 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
 				       struct clk_rate_request *req);
 int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
-bool omap2_clk_is_hw_omap(struct clk_hw *hw);
 
 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
 
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 78872ef..2821f7c 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -243,6 +243,7 @@ struct ti_clk_ll_ops {
 
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
+bool omap2_clk_is_hw_omap(struct clk_hw *hw);
 int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 2/6] ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage

[Tero Kristo]

CLK_IS_BASIC flag is about to get deprecated, and as such, can't be used.
Instead, the API call for checking whether a clock is of type hw_omap shall
be used, so convert the code to use this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3a04c73..baadddf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -648,10 +648,10 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
 	if (oh->clkdm) {
 		return oh->clkdm;
 	} else if (oh->_clk) {
-		if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+		if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk)))
 			return NULL;
 		clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
-		return  clk->clkdm;
+		return clk->clkdm;
 	}
 	return NULL;
 }
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 3/6] clk: ti: dra7x: prevent non-existing clkctrl clocks from registering

[Tero Kristo]

Certain clkctrl clocks (like the USB_OTG_SS4) do not exist on some
variants of the dra7x SoC. Append a flag for these clocks and skip
the registration in cases where the clocks do not exist.

Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/clk-7xx-compat.c |  2 +-
 drivers/clk/ti/clk-7xx.c        |  2 +-
 drivers/clk/ti/clkctrl.c        | 14 ++++++++++++++
 drivers/clk/ti/clock.h          |  6 ++++++
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
index e3cb7f0..0d53bd0 100644
--- a/drivers/clk/ti/clk-7xx-compat.c
+++ b/drivers/clk/ti/clk-7xx-compat.c
@@ -362,7 +362,7 @@
 	{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
 	{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 	{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
-	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
 	{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 	{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
 	{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 597fb4a..098c342 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -348,7 +348,7 @@
 	{ DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
 	{ DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 	{ DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
-	{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+	{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
 	{ DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 	{ DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 	{ DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 639f515..4cdeb8d 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -446,6 +446,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 	u32 addr;
 	int ret;
 	char *c;
+	u16 soc_mask = 0;
 
 	if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
 	    of_node_name_eq(node, "clk"))
@@ -469,6 +470,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 		else
 			data = dra7_clkctrl_data;
 	}
+
+	if (of_machine_is_compatible("ti,dra72"))
+		soc_mask = CLKF_SOC_DRA72;
+	if (of_machine_is_compatible("ti,dra74"))
+		soc_mask = CLKF_SOC_DRA74;
+	if (of_machine_is_compatible("ti,dra76"))
+		soc_mask = CLKF_SOC_DRA76;
 #endif
 #ifdef CONFIG_SOC_AM33XX
 	if (of_machine_is_compatible("ti,am33xx")) {
@@ -562,6 +570,12 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 	reg_data = data->regs;
 
 	while (reg_data->parent) {
+		if ((reg_data->flags & CLKF_SOC_MASK) &&
+		    (reg_data->flags & soc_mask) == 0) {
+			reg_data++;
+			continue;
+		}
+
 		hw = kzalloc(sizeof(*hw), GFP_KERNEL);
 		if (!hw)
 			return;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 4223a39..773e2c4 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -83,6 +83,12 @@ enum {
 #define CLKF_HW_SUP			BIT(6)
 #define CLKF_NO_IDLEST			BIT(7)
 
+#define CLKF_SOC_MASK			GENMASK(10, 8)
+
+#define CLKF_SOC_DRA72			BIT(8)
+#define CLKF_SOC_DRA74			BIT(9)
+#define CLKF_SOC_DRA76			BIT(10)
+
 #define CLK(dev, con, ck)		\
 	{				\
 		.lk = {			\
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 4/6] clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devices

[Tero Kristo]

RNG and TIMER12 are reserved for secure side usage only on HS devices,
so disable their clkctrl clocks on HS SoCs also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Andrew F. Davis <afd@ti.com>
---
 arch/arm/mach-omap2/clock.c     | 3 +++
 drivers/clk/ti/clk-7xx-compat.c | 4 ++--
 drivers/clk/ti/clk-7xx.c        | 4 ++--
 drivers/clk/ti/clkctrl.c        | 3 +++
 drivers/clk/ti/clock.h          | 9 +++++----
 include/linux/clk/ti.h          | 1 +
 6 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 42881f2..3e0f09c 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -119,6 +119,9 @@ void __init ti_clk_init_features(void)
 	if (cpu_is_omap343x())
 		features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
 
+	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+		features.flags |= TI_CLK_DEVICE_TYPE_GP;
+
 	/* Idlest value for interface clocks.
 	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
 	 * 34xx reverses this, just to keep us on our toes
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
index 0d53bd0..b3cd229 100644
--- a/drivers/clk/ti/clk-7xx-compat.c
+++ b/drivers/clk/ti/clk-7xx-compat.c
@@ -662,7 +662,7 @@
 	{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 	{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 	{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
-	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
 	{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 	{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
 	{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
@@ -704,7 +704,7 @@
 	{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 	{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
-	{ DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
+	{ DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
 	{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 	{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
 	{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 098c342..79186b9 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -590,7 +590,7 @@
 	{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 	{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 	{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
-	{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },
+	{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
 	{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 	{ 0 },
 };
@@ -757,7 +757,7 @@
 	{ DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 	{ DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
-	{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
+	{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
 	{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 	{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
 	{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 4cdeb8d..96d65a1 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -509,6 +509,9 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 		data = dm816_clkctrl_data;
 #endif
 
+	if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
+		soc_mask |= CLKF_SOC_NONSEC;
+
 	while (data->addr) {
 		if (addr == data->addr)
 			break;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 773e2c4..e4b8392 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -83,11 +83,12 @@ enum {
 #define CLKF_HW_SUP			BIT(6)
 #define CLKF_NO_IDLEST			BIT(7)
 
-#define CLKF_SOC_MASK			GENMASK(10, 8)
+#define CLKF_SOC_MASK			GENMASK(11, 8)
 
-#define CLKF_SOC_DRA72			BIT(8)
-#define CLKF_SOC_DRA74			BIT(9)
-#define CLKF_SOC_DRA76			BIT(10)
+#define CLKF_SOC_NONSEC			BIT(8)
+#define CLKF_SOC_DRA72			BIT(9)
+#define CLKF_SOC_DRA74			BIT(10)
+#define CLKF_SOC_DRA76			BIT(11)
 
 #define CLK(dev, con, ck)		\
 	{				\
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 2821f7c..1e8ef96 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -294,6 +294,7 @@ struct ti_clk_features {
 #define TI_CLK_DISABLE_CLKDM_CONTROL		BIT(2)
 #define TI_CLK_ERRATA_I810			BIT(3)
 #define TI_CLK_CLKCTRL_COMPAT			BIT(4)
+#define TI_CLK_DEVICE_TYPE_GP			BIT(5)
 
 void ti_clk_setup_features(struct ti_clk_features *features);
 const struct ti_clk_features *ti_clk_get_features(void);
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 5/6] clk: ti: am33xx: drop idlest polling from gfx clkctrl clock

[Tero Kristo]

From: Eric Ruei <e-ruei1@ti.com>

The GFX modules on AM33xx SoCs have a hardreset line and are controlled
by a GFX reset line. Any clkctrl enable/disable operations cannot be
checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for the GFX clocks. These details should be handled
by the driver integration code itself.

Signed-off-by: Eric Ruei <e-ruei1@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/clk-33xx-compat.c | 2 +-
 drivers/clk/ti/clk-33xx.c        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c
index 3e07f12..d11fb42 100644
--- a/drivers/clk/ti/clk-33xx-compat.c
+++ b/drivers/clk/ti/clk-33xx-compat.c
@@ -181,7 +181,7 @@
 };
 
 static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
-	{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+	{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
 	{ 0 },
 };
 
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index a360d31..7436e0f 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -217,7 +217,7 @@
 };
 
 static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
-	{ AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+	{ AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
 	{ 0 },
 };
 
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 6/6] clk: ti: am43xx: drop idlest polling from gfx clkctrl clock

[Tero Kristo]

From: Eric Ruei <e-ruei1@ti.com>

The GFX modules on AM43xx SoCs have a hardreset line and are controlled
by a GFX reset line. Any clkctrl enable/disable operations cannot be
checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for the GFX clocks. These details should be handled
by the driver integration code itself.

Add the CLKF_NO_IDLEST flag to the GFX clkctrl clock so that these
module status checks are skipped.

Signed-off-by: Eric Ruei <e-ruei1@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/clk-43xx-compat.c | 2 +-
 drivers/clk/ti/clk-43xx.c        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c
index 5130398..ac8117d 100644
--- a/drivers/clk/ti/clk-43xx-compat.c
+++ b/drivers/clk/ti/clk-43xx-compat.c
@@ -65,7 +65,7 @@
 };
 
 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
-	{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+	{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
 	{ 0 },
 };
 
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 2782d91..9882a9b 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -73,7 +73,7 @@
 };
 
 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
-	{ AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+	{ AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
 	{ 0 },
 };
 
-- 
1.9.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH 5/6] clk: ti: am33xx: drop idlest polling from gfx clkctrl clock

[Tony Lindgren]

Hi,

* Tero Kristo <t-kristo@ti.com> [190404 08:12]:
> From: Eric Ruei <e-ruei1@ti.com>
> 
> The GFX modules on AM33xx SoCs have a hardreset line and are controlled
> by a GFX reset line. Any clkctrl enable/disable operations cannot be
> checked for module enabled/disabled status independent of the reset
> operation, and this causes some unwanted timeouts in the kernel and
> unbalanced states for the GFX clocks. These details should be handled
> by the driver integration code itself.

These last two patches should no longer be needed with ti-sysc.
Well, at least based on testing with the earlier reset-simple driver
patch and a test for sgx register access on am335x.

On init we deassert rstctrl if configured and in reset, then enable
clocks, and read the module revision. And the module is ready for child
device driver(s) to probe, and do what they want with the rstctrl via a
reset driver. If no child device driver(s) are configured, ti-sysc will
just put the module rstctrl back to reset using reset driver.

Regards,

Tony

Re: [PATCH 2/6] ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [190404 08:12]:
> CLK_IS_BASIC flag is about to get deprecated, and as such, can't be used.
> Instead, the API call for checking whether a clock is of type hw_omap shall
> be used, so convert the code to use this.

Acked-by: Tony Lindgren <tony@atomide.com>

Re: [PATCH 5/6] clk: ti: am33xx: drop idlest polling from gfx clkctrl clock

[Tero Kristo]

On 04/04/2019 17:06, Tony Lindgren wrote:
> Hi,
> 
> * Tero Kristo <t-kristo@ti.com> [190404 08:12]:
>> From: Eric Ruei <e-ruei1@ti.com>
>>
>> The GFX modules on AM33xx SoCs have a hardreset line and are controlled
>> by a GFX reset line. Any clkctrl enable/disable operations cannot be
>> checked for module enabled/disabled status independent of the reset
>> operation, and this causes some unwanted timeouts in the kernel and
>> unbalanced states for the GFX clocks. These details should be handled
>> by the driver integration code itself.
> 
> These last two patches should no longer be needed with ti-sysc.
> Well, at least based on testing with the earlier reset-simple driver
> patch and a test for sgx register access on am335x.
> 
> On init we deassert rstctrl if configured and in reset, then enable
> clocks, and read the module revision. And the module is ready for child
> device driver(s) to probe, and do what they want with the rstctrl via a
> reset driver. If no child device driver(s) are configured, ti-sysc will
> just put the module rstctrl back to reset using reset driver.

Ok good to know, lets drop these patches for now and re-consider once we 
can try out graphics with latest kernel... unfortunately it is not 
available upstream.

-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH 5/6] clk: ti: am33xx: drop idlest polling from gfx clkctrl clock

[Stephen Boyd]

Quoting Tero Kristo (2019-04-07 22:45:08)
> On 04/04/2019 17:06, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [190404 08:12]:
> >> From: Eric Ruei <e-ruei1@ti.com>
> >>
> >> The GFX modules on AM33xx SoCs have a hardreset line and are controlled
> >> by a GFX reset line. Any clkctrl enable/disable operations cannot be
> >> checked for module enabled/disabled status independent of the reset
> >> operation, and this causes some unwanted timeouts in the kernel and
> >> unbalanced states for the GFX clocks. These details should be handled
> >> by the driver integration code itself.
> > 
> > These last two patches should no longer be needed with ti-sysc.
> > Well, at least based on testing with the earlier reset-simple driver
> > patch and a test for sgx register access on am335x.
> > 
> > On init we deassert rstctrl if configured and in reset, then enable
> > clocks, and read the module revision. And the module is ready for child
> > device driver(s) to probe, and do what they want with the rstctrl via a
> > reset driver. If no child device driver(s) are configured, ti-sysc will
> > just put the module rstctrl back to reset using reset driver.
> 
> Ok good to know, lets drop these patches for now and re-consider once we 
> can try out graphics with latest kernel... unfortunately it is not 
> available upstream.

Sooooo drop the last two patches and I should pick up the first four?

Re: [PATCH 5/6] clk: ti: am33xx: drop idlest polling from gfx clkctrl clock

[Tony Lindgren]

* Stephen Boyd <sboyd@kernel.org> [190425 17:51]:
> Quoting Tero Kristo (2019-04-07 22:45:08)
> > On 04/04/2019 17:06, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [190404 08:12]:
> > >> From: Eric Ruei <e-ruei1@ti.com>
> > >>
> > >> The GFX modules on AM33xx SoCs have a hardreset line and are controlled
> > >> by a GFX reset line. Any clkctrl enable/disable operations cannot be
> > >> checked for module enabled/disabled status independent of the reset
> > >> operation, and this causes some unwanted timeouts in the kernel and
> > >> unbalanced states for the GFX clocks. These details should be handled
> > >> by the driver integration code itself.
> > > 
> > > These last two patches should no longer be needed with ti-sysc.
> > > Well, at least based on testing with the earlier reset-simple driver
> > > patch and a test for sgx register access on am335x.
> > > 
> > > On init we deassert rstctrl if configured and in reset, then enable
> > > clocks, and read the module revision. And the module is ready for child
> > > device driver(s) to probe, and do what they want with the rstctrl via a
> > > reset driver. If no child device driver(s) are configured, ti-sysc will
> > > just put the module rstctrl back to reset using reset driver.
> > 
> > Ok good to know, lets drop these patches for now and re-consider once we 
> > can try out graphics with latest kernel... unfortunately it is not 
> > available upstream.
> 
> Sooooo drop the last two patches and I should pick up the first four?

Yes please.

Regards,

Tony

Re: [PATCH 1/6] clk: ti: export the omap2_clk_is_hw_omap call

[Stephen Boyd]

Quoting Tero Kristo (2019-04-04 01:11:02)
> There is one instance outside the TI clock driver that needs the info
> whether a clock is an OMAP HW clock or not. Thus, move the function
> declaration into the public header.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---

Applied to clk-next

Re: [PATCH 2/6] ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage

[Stephen Boyd]

Quoting Tero Kristo (2019-04-04 01:11:03)
> CLK_IS_BASIC flag is about to get deprecated, and as such, can't be used.
> Instead, the API call for checking whether a clock is of type hw_omap shall
> be used, so convert the code to use this.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---

Applied to clk-next

Re: [PATCH 3/6] clk: ti: dra7x: prevent non-existing clkctrl clocks from registering

[Stephen Boyd]

Quoting Tero Kristo (2019-04-04 01:11:04)
> Certain clkctrl clocks (like the USB_OTG_SS4) do not exist on some
> variants of the dra7x SoC. Append a flag for these clocks and skip
> the registration in cases where the clocks do not exist.
> 
> Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---

Applied to clk-next

Re: [PATCH 4/6] clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devices

[Stephen Boyd]

Quoting Tero Kristo (2019-04-04 01:11:05)
> RNG and TIMER12 are reserved for secure side usage only on HS devices,
> so disable their clkctrl clocks on HS SoCs also.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Tested-by: Andrew F. Davis <afd@ti.com>
> ---

Applied to clk-next