* [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
@ 2019-04-09 16:13 Mika Kuoppala
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
` (10 more replies)
0 siblings, 11 replies; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
In order not to inflate gen9 rc6 enabling sequence with
gen11 specifics, use a separate function for it.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 72 +++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bba477e62a12..43ec0fb4c197 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7120,6 +7120,76 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
+static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /* 1a: Software RC state - RC0 */
+ I915_WRITE(GEN6_RC_STATE, 0);
+
+ /* 1b: Get forcewake during program sequence. Although the driver
+ * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+
+ /* 2a: Disable RC states. */
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ /* 2b: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+ I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+ for_each_engine(engine, dev_priv, id)
+ I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
+
+ if (HAS_GUC(dev_priv))
+ I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
+
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ /*
+ * 2c: Program Coarse Power Gating Policies.
+ *
+ * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
+ * use instead is a more conservative estimate for the maximum time
+ * it takes us to service a CS interrupt and submit a new ELSP - that
+ * is the time which the GPU is idle waiting for the CPU to select the
+ * next request to execute. If the idle hysteresis is less than that
+ * interrupt service latency, the hardware will automatically gate
+ * the power well and we will then incur the wake up cost on top of
+ * the service latency. A similar guide from intel_pstate is that we
+ * do not want the enable hysteresis to less than the wakeup latency.
+ *
+ * igt/gem_exec_nop/sequential provides a rough estimate for the
+ * service latency, and puts it around 10us for Broadwell (and other
+ * big core) and around 40us for Broxton (and other low power cores).
+ * [Note that for legacy ringbuffer submission, this is less than 1us!]
+ * However, the wakeup latency on Broxton is closer to 100us. To be
+ * conservative, we have to factor in a context switch on top (due
+ * to ksoftirqd).
+ */
+ I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
+ I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
+
+ /* 3a: Enable RC6 */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+
+ I915_WRITE(GEN6_RC_CONTROL,
+ GEN6_RC_CTL_HW_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE |
+ GEN6_RC_CTL_EI_MODE(1));
+
+ /*
+ * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+ */
+ I915_WRITE(GEN9_PG_ENABLE,
+ GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
+
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+}
+
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
@@ -8596,6 +8666,8 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
cherryview_enable_rc6(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
valleyview_enable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 11)
+ gen11_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 9)
gen9_enable_rc6(dev_priv);
else if (IS_BROADWELL(dev_priv))
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:51 ` Michal Wajdeczko
2019-04-09 16:13 ` [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis Mika Kuoppala
` (9 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
On gen11 the recommended rc6 threshold differs from previous
gens, apply it.
References: bspec#52070
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 43ec0fb4c197..30ef507b88a4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7174,7 +7174,7 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
/* 3a: Enable RC6 */
- I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
I915_WRITE(GEN6_RC_CONTROL,
GEN6_RC_CTL_HW_ENABLE |
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:16 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 4/7] drm/i915/icl: Enable media sampler powergate Mika Kuoppala
` (8 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
Use a recommended idle hysteresis for media and render powergates.
References: bspec#52070
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30ef507b88a4..b9be9ea5fc18 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7170,8 +7170,8 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
* conservative, we have to factor in a context switch on top (due
* to ksoftirqd).
*/
- I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
- I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
+ I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
+ I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
/* 3a: Enable RC6 */
I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/7] drm/i915/icl: Enable media sampler powergate
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
2019-04-09 16:13 ` [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:34 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control Mika Kuoppala
` (7 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
Enable media sampler powergate as recommended.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c206e803ab3..20f5850c52f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8687,8 +8687,9 @@ enum {
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
#define GEN9_PG_ENABLE _MMIO(0xA210)
-#define GEN9_RENDER_PG_ENABLE (1 << 0)
-#define GEN9_MEDIA_PG_ENABLE (1 << 1)
+#define GEN9_RENDER_PG_ENABLE BIT(0)
+#define GEN9_MEDIA_PG_ENABLE BIT(1)
+#define GEN11_MEDIA_SAMPLER_PG_ENABLE BIT(2)
#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9be9ea5fc18..47f98e064de5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7185,7 +7185,9 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
*/
I915_WRITE(GEN9_PG_ENABLE,
- GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
+ GEN9_RENDER_PG_ENABLE |
+ GEN9_MEDIA_PG_ENABLE |
+ GEN11_MEDIA_SAMPLER_PG_ENABLE);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (2 preceding siblings ...)
2019-04-09 16:13 ` [PATCH 4/7] drm/i915/icl: Enable media sampler powergate Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:32 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock Mika Kuoppala
` (6 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
There is no video turbo mode for gen11, so don't set it.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 47f98e064de5..d6abba5c0b32 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6548,6 +6548,7 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
u32 threshold_up = 0, threshold_down = 0; /* in % */
u32 ei_up = 0, ei_down = 0;
+ u32 media_turbo;
lockdep_assert_held(&rps->power.mutex);
@@ -6605,8 +6606,10 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
GT_INTERVAL_FROM_US(dev_priv,
ei_down * threshold_down / 100));
+ media_turbo = INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO;
+
I915_WRITE(GEN6_RP_CONTROL,
- GEN6_RP_MEDIA_TURBO |
+ media_turbo |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (3 preceding siblings ...)
2019-04-09 16:13 ` [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:21 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts Mika Kuoppala
` (5 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
Unlike previous gens, we already hold the irq_lock on
entering the rps handler so we can't use it as it is.
Make a gen11 specific rps interrupt handler without
locking.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6454ddc37f8b..619e6ab273e7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1796,6 +1796,22 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
/* The RPS events need forcewake, so we add them to a work queue and mask their
* IMR bits until the work is done. Other interrupts can be processed without
* the work queue. */
+static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
+{
+ struct intel_rps *rps = &i915->gt_pm.rps;
+ const u32 events = i915->pm_rps_events & pm_iir;
+
+ lockdep_assert_held(&i915->irq_lock);
+
+ if (events) {
+ gen6_mask_pm_irq(i915, events);
+ if (rps->interrupts_enabled) {
+ rps->pm_iir |= events;
+ schedule_work(&rps->work);
+ }
+ }
+}
+
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -2949,7 +2965,7 @@ gen11_other_irq_handler(struct drm_i915_private * const i915,
const u8 instance, const u16 iir)
{
if (instance == OTHER_GTPM_INSTANCE)
- return gen6_rps_irq_handler(i915, iir);
+ return gen11_rps_irq_handler(i915, iir);
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (4 preceding siblings ...)
2019-04-09 16:13 ` [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock Mika Kuoppala
@ 2019-04-09 16:13 ` Mika Kuoppala
2019-04-09 16:26 ` Chris Wilson
2019-04-09 16:28 ` [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Chris Wilson
` (4 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-09 16:13 UTC (permalink / raw)
To: intel-gfx
With gen11 the interrupt registers are shared between 2 engines,
with Engine1 instance being upper word and Engine0 instance being
lower. Annoyingly gen11 selected the pm interrupts to be in the
Engine1 instance.
Rectify the situation by shifting the access accordingly,
based on gen.
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=108059
Testcase: igt/i915_pm_rps@min-max-config-loaded
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++++++++------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 619e6ab273e7..be501e069b60 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -369,24 +369,39 @@ static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}
-static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
+static void write_pm_imr(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 11)
- return GEN11_GPM_WGBOXPERF_INTR_MASK;
- else if (INTEL_GEN(dev_priv) >= 8)
- return GEN8_GT_IMR(2);
- else
- return GEN6_PMIMR;
+ i915_reg_t reg;
+ u32 mask = dev_priv->pm_imr;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
+ mask = mask << 16;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ reg = GEN8_GT_IMR(2);
+ } else {
+ reg = GEN6_PMIMR;
+ }
+
+ I915_WRITE(reg, mask);
+ POSTING_READ(reg);
}
-static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
+static void write_pm_ier(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 11)
- return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
- else if (INTEL_GEN(dev_priv) >= 8)
- return GEN8_GT_IER(2);
- else
- return GEN6_PMIER;
+ i915_reg_t reg;
+ u32 mask = dev_priv->pm_ier;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
+ mask = mask << 16;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ reg = GEN8_GT_IER(2);
+ } else {
+ reg = GEN6_PMIER;
+ }
+
+ I915_WRITE(reg, mask);
}
/**
@@ -411,8 +426,7 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
if (new_val != dev_priv->pm_imr) {
dev_priv->pm_imr = new_val;
- I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
- POSTING_READ(gen6_pm_imr(dev_priv));
+ write_pm_imr(dev_priv);
}
}
@@ -453,7 +467,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
lockdep_assert_held(&dev_priv->irq_lock);
dev_priv->pm_ier |= enable_mask;
- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ write_pm_ier(dev_priv);
gen6_unmask_pm_irq(dev_priv, enable_mask);
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
}
@@ -464,7 +478,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
dev_priv->pm_ier &= ~disable_mask;
__gen6_mask_pm_irq(dev_priv, disable_mask);
- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ write_pm_ier(dev_priv);
/* though a barrier is missing here, but don't really need a one */
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis
2019-04-09 16:13 ` [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis Mika Kuoppala
@ 2019-04-09 16:16 ` Chris Wilson
2019-04-10 8:04 ` Mika Kuoppala
0 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:16 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:06)
> Use a recommended idle hysteresis for media and render powergates.
>
> References: bspec#52070
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 30ef507b88a4..b9be9ea5fc18 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7170,8 +7170,8 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
> * conservative, we have to factor in a context switch on top (due
> * to ksoftirqd).
> */
> - I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> - I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
> + I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> + I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
We were using higher than recommended for the simple reason of not
allowing it to powergate while signaling between engines. We are much
faster now (though be sure to disable semaphores to put us in worse
case) and since we use one value, we need to measure on the slow
platform.
Anyway, just pointing out there was a reason for a relatively large
hysteresis.
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock
2019-04-09 16:13 ` [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock Mika Kuoppala
@ 2019-04-09 16:21 ` Chris Wilson
2019-04-10 8:09 ` Mika Kuoppala
0 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:21 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:09)
> Unlike previous gens, we already hold the irq_lock on
> entering the rps handler so we can't use it as it is.
>
> Make a gen11 specific rps interrupt handler without
> locking.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6454ddc37f8b..619e6ab273e7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1796,6 +1796,22 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> /* The RPS events need forcewake, so we add them to a work queue and mask their
> * IMR bits until the work is done. Other interrupts can be processed without
> * the work queue. */
> +static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
> +{
> + struct intel_rps *rps = &i915->gt_pm.rps;
> + const u32 events = i915->pm_rps_events & pm_iir;
> +
> + lockdep_assert_held(&i915->irq_lock);
> +
> + if (events) {
if (!events)
return;
?
Maybe you have reason for the indent later.
> + gen6_mask_pm_irq(i915, events);
> + if (rps->interrupts_enabled) {
> + rps->pm_iir |= events;
> + schedule_work(&rps->work);
> + }
> + }
All I can say is that this is evidence that we've never had an rps
interrupt!
I guess this patch needs to be first just in case an interrupt is sent.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts
2019-04-09 16:13 ` [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts Mika Kuoppala
@ 2019-04-09 16:26 ` Chris Wilson
2019-04-10 8:20 ` Mika Kuoppala
0 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:26 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:10)
> With gen11 the interrupt registers are shared between 2 engines,
> with Engine1 instance being upper word and Engine0 instance being
> lower. Annoyingly gen11 selected the pm interrupts to be in the
> Engine1 instance.
Sounds weird, but I can't fault the solution. The choice would either to
have been shift pm_rps_events andadd gen11_pm_imr/_ier, so this patch
looks to be the smaller delta.
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (5 preceding siblings ...)
2019-04-09 16:13 ` [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts Mika Kuoppala
@ 2019-04-09 16:28 ` Chris Wilson
2019-04-09 16:57 ` Michal Wajdeczko
` (3 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:28 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:04)
> In order not to inflate gen9 rc6 enabling sequence with
> gen11 specifics, use a separate function for it.
And disable_rc6 remains as simple as before.
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control
2019-04-09 16:13 ` [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control Mika Kuoppala
@ 2019-04-09 16:32 ` Chris Wilson
2019-04-10 8:05 ` Mika Kuoppala
0 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:32 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:08)
> There is no video turbo mode for gen11, so don't set it.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 47f98e064de5..d6abba5c0b32 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6548,6 +6548,7 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
> u32 threshold_up = 0, threshold_down = 0; /* in % */
> u32 ei_up = 0, ei_down = 0;
> + u32 media_turbo;
>
> lockdep_assert_held(&rps->power.mutex);
>
> @@ -6605,8 +6606,10 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
> GT_INTERVAL_FROM_US(dev_priv,
> ei_down * threshold_down / 100));
>
> + media_turbo = INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO;
> +
> I915_WRITE(GEN6_RP_CONTROL,
> - GEN6_RP_MEDIA_TURBO |
> + media_turbo |
Looks short enough to fit inline?
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] drm/i915/icl: Enable media sampler powergate
2019-04-09 16:13 ` [PATCH 4/7] drm/i915/icl: Enable media sampler powergate Mika Kuoppala
@ 2019-04-09 16:34 ` Chris Wilson
0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 16:34 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-09 17:13:07)
> Enable media sampler powergate as recommended.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c206e803ab3..20f5850c52f8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8687,8 +8687,9 @@ enum {
> #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
> #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
> #define GEN9_PG_ENABLE _MMIO(0xA210)
> -#define GEN9_RENDER_PG_ENABLE (1 << 0)
> -#define GEN9_MEDIA_PG_ENABLE (1 << 1)
> +#define GEN9_RENDER_PG_ENABLE BIT(0)
> +#define GEN9_MEDIA_PG_ENABLE BIT(1)
> +#define GEN11_MEDIA_SAMPLER_PG_ENABLE BIT(2)
REG_BIT(foo)
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
@ 2019-04-09 16:51 ` Michal Wajdeczko
0 siblings, 0 replies; 24+ messages in thread
From: Michal Wajdeczko @ 2019-04-09 16:51 UTC (permalink / raw)
To: intel-gfx, Mika Kuoppala
On Tue, 09 Apr 2019 18:13:05 +0200, Mika Kuoppala
<mika.kuoppala@linux.intel.com> wrote:
> On gen11 the recommended rc6 threshold differs from previous
> gens, apply it.
>
> References: bspec#52070
Is this correct number? I found it at 33149
And note that we are using different tag:
Bspec: 33149
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 43ec0fb4c197..30ef507b88a4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7174,7 +7174,7 @@ static void gen11_enable_rc6(struct
> drm_i915_private *dev_priv)
> I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
> /* 3a: Enable RC6 */
> - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> + I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
Btw, in bspec this is done at the end of step 2b.
Shall we reorder whole function to match the spec?
~Michal
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (6 preceding siblings ...)
2019-04-09 16:28 ` [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Chris Wilson
@ 2019-04-09 16:57 ` Michal Wajdeczko
2019-04-09 17:04 ` Chris Wilson
2019-04-09 17:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
` (2 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Michal Wajdeczko @ 2019-04-09 16:57 UTC (permalink / raw)
To: intel-gfx, Mika Kuoppala
On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
<mika.kuoppala@linux.intel.com> wrote:
[snip]
> +
> + /*
> + * 2c: Program Coarse Power Gating Policies.
> + *
> + * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
> + * use instead is a more conservative estimate for the maximum time
> + * it takes us to service a CS interrupt and submit a new ELSP - that
> + * is the time which the GPU is idle waiting for the CPU to select the
> + * next request to execute. If the idle hysteresis is less than that
> + * interrupt service latency, the hardware will automatically gate
> + * the power well and we will then incur the wake up cost on top of
> + * the service latency. A similar guide from intel_pstate is that we
> + * do not want the enable hysteresis to less than the wakeup latency.
> + *
> + * igt/gem_exec_nop/sequential provides a rough estimate for the
> + * service latency, and puts it around 10us for Broadwell (and other
> + * big core) and around 40us for Broxton (and other low power cores).
> + * [Note that for legacy ringbuffer submission, this is less than 1us!]
> + * However, the wakeup latency on Broxton is closer to 100us. To be
> + * conservative, we have to factor in a context switch on top (due
> + * to ksoftirqd).
> + */
Do we want to copy legacy comments to Gen11 specific function ?
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:57 ` Michal Wajdeczko
@ 2019-04-09 17:04 ` Chris Wilson
0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-04-09 17:04 UTC (permalink / raw)
To: Michal Wajdeczko, Mika Kuoppala, intel-gfx
Quoting Michal Wajdeczko (2019-04-09 17:57:58)
> On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
> <mika.kuoppala@linux.intel.com> wrote:
>
> [snip]
>
> > +
> > + /*
> > + * 2c: Program Coarse Power Gating Policies.
> > + *
> > + * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
> > + * use instead is a more conservative estimate for the maximum time
> > + * it takes us to service a CS interrupt and submit a new ELSP - that
> > + * is the time which the GPU is idle waiting for the CPU to select the
> > + * next request to execute. If the idle hysteresis is less than that
> > + * interrupt service latency, the hardware will automatically gate
> > + * the power well and we will then incur the wake up cost on top of
> > + * the service latency. A similar guide from intel_pstate is that we
> > + * do not want the enable hysteresis to less than the wakeup latency.
> > + *
> > + * igt/gem_exec_nop/sequential provides a rough estimate for the
> > + * service latency, and puts it around 10us for Broadwell (and other
> > + * big core) and around 40us for Broxton (and other low power cores).
> > + * [Note that for legacy ringbuffer submission, this is less than 1us!]
> > + * However, the wakeup latency on Broxton is closer to 100us. To be
> > + * conservative, we have to factor in a context switch on top (due
> > + * to ksoftirqd).
> > + */
>
> Do we want to copy legacy comments to Gen11 specific function ?
The comment isn't legacy until you crunch through the measurements to
work out the minimum tolerances that are sensible for us.
-Chris
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^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (7 preceding siblings ...)
2019-04-09 16:57 ` Michal Wajdeczko
@ 2019-04-09 17:16 ` Patchwork
2019-04-09 17:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-10 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-04-09 17:16 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
URL : https://patchwork.freedesktop.org/series/59237/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
18e95bd1432c drm/i915: Use dedicated rc6 enabling sequence for gen11
-:29: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#29: FILE: drivers/gpu/drm/i915/intel_pm.c:7132:
+ * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
total: 0 errors, 1 warnings, 0 checks, 84 lines checked
c8793cae22c1 drm/i915/icl: Apply a recommended rc6 threshold
aa62d29fe1ae drm/i915/icl: Apply recommended rc6 idle hysteresis
1b904b5fd577 drm/i915/icl: Enable media sampler powergate
265eaf609bc8 drm/i915/icl: Disable video turbo mode for rp control
b8d222eef36b drm/i915/icl: Handle rps interrupts without irq lock
92c211e3d49d drm/i915: Use Engine1 instance for gen11 pm interrupts
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (8 preceding siblings ...)
2019-04-09 17:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
@ 2019-04-09 17:42 ` Patchwork
2019-04-10 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-04-09 17:42 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
URL : https://patchwork.freedesktop.org/series/59237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5897 -> Patchwork_12742
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59237/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12742 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_store@basic-bsd1:
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-y: PASS -> DMESG-WARN [fdo#109638]
* igt@i915_selftest@live_contexts:
- fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@i915_selftest@live_hangcheck:
- fi-bxt-dsi: PASS -> INCOMPLETE [fdo#103927]
- fi-icl-y: PASS -> INCOMPLETE [fdo#108569]
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48
* igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> FAIL [k.org#202321]
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: INCOMPLETE [fdo#107713] -> PASS
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> DMESG-WARN [fdo#105538] / [fdo#107732] / [fdo#109513]
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105538]: https://bugs.freedesktop.org/show_bug.cgi?id=105538
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109513]: https://bugs.freedesktop.org/show_bug.cgi?id=109513
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (44 -> 43)
------------------------------
Additional (3): fi-byt-j1900 fi-kbl-r fi-bsw-n3050
Missing (4): fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5897 -> Patchwork_12742
CI_DRM_5897: 7d07e025e78603d6270bc115fdb6c1efea6e66a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4934: dc4f45eb6874331daec870dc1e4cfc3ac5c49311 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12742: 92c211e3d49dcaed6a8394855321a33a5007f930 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
92c211e3d49d drm/i915: Use Engine1 instance for gen11 pm interrupts
b8d222eef36b drm/i915/icl: Handle rps interrupts without irq lock
265eaf609bc8 drm/i915/icl: Disable video turbo mode for rp control
1b904b5fd577 drm/i915/icl: Enable media sampler powergate
aa62d29fe1ae drm/i915/icl: Apply recommended rc6 idle hysteresis
c8793cae22c1 drm/i915/icl: Apply a recommended rc6 threshold
18e95bd1432c drm/i915: Use dedicated rc6 enabling sequence for gen11
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12742/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
` (9 preceding siblings ...)
2019-04-09 17:42 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-10 5:59 ` Patchwork
2019-04-10 9:04 ` Chris Wilson
10 siblings, 1 reply; 24+ messages in thread
From: Patchwork @ 2019-04-10 5:59 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
URL : https://patchwork.freedesktop.org/series/59237/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5897_full -> Patchwork_12742_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12742_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12742_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12742_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_caching@writes:
- shard-iclb: PASS -> DMESG-WARN +1
Known issues
------------
Here are the changes found in Patchwork_12742_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-iclb: PASS -> DMESG-WARN [fdo#109960]
* igt@gem_pread@pagefault-pread:
- shard-iclb: NOTRUN -> SKIP [fdo#109277]
* igt@i915_pm_rpm@dpms-lpsp:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] +1
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> SKIP [fdo#109506]
* igt@i915_pm_rpm@sysfs-read:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_suspend@sysfs-reader:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +1
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +21
* igt@kms_content_protection@atomic:
- shard-iclb: NOTRUN -> SKIP [fdo#109300]
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> FAIL [fdo#110321] / [fdo#110336]
* igt@kms_crtc_background_color:
- shard-iclb: NOTRUN -> SKIP [fdo#109305]
* igt@kms_draw_crc@fill-fb:
- shard-iclb: PASS -> FAIL [fdo#103184] / [fdo#109960]
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +126
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-skl: PASS -> FAIL [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#109247] +23
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +1
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> FAIL [fdo#108145] +5
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_psr@primary_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +4
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: PASS -> FAIL [fdo#104894] +1
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: PASS -> FAIL [fdo#104894]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +2
* igt@perf_pmu@rc6:
- shard-kbl: PASS -> SKIP [fdo#109271]
* igt@prime_vgem@sync-bsd1:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +276
#### Possible fixes ####
* igt@gem_mmap_gtt@forked-big-copy-xy:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: INCOMPLETE [fdo#109801] -> PASS
* igt@i915_pm_rps@reset:
- shard-iclb: FAIL [fdo#108059] -> PASS +2
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: FAIL [fdo#103355] -> PASS +2
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#102887] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
- shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-rmfb:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-iclb: FAIL [fdo#103375] -> PASS
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +21
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@cursor_plane_onoff:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-iclb: FAIL [fdo#105010] -> PASS
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109305]: https://bugs.freedesktop.org/show_bug.cgi?id=109305
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#109960]: https://bugs.freedesktop.org/show_bug.cgi?id=109960
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5897 -> Patchwork_12742
CI_DRM_5897: 7d07e025e78603d6270bc115fdb6c1efea6e66a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4934: dc4f45eb6874331daec870dc1e4cfc3ac5c49311 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12742: 92c211e3d49dcaed6a8394855321a33a5007f930 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12742/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis
2019-04-09 16:16 ` Chris Wilson
@ 2019-04-10 8:04 ` Mika Kuoppala
0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-10 8:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:06)
>> Use a recommended idle hysteresis for media and render powergates.
>>
>> References: bspec#52070
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 30ef507b88a4..b9be9ea5fc18 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7170,8 +7170,8 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
>> * conservative, we have to factor in a context switch on top (due
>> * to ksoftirqd).
>> */
>> - I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
>> - I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
>> + I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
>> + I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
>
> We were using higher than recommended for the simple reason of not
> allowing it to powergate while signaling between engines. We are much
> faster now (though be sure to disable semaphores to put us in worse
> case) and since we use one value, we need to measure on the slow
> platform.
>
> Anyway, just pointing out there was a reason for a relatively large
> hysteresis.
Then we should just drop this patch. Ta for pointing out the
reasoning.
-Mika
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control
2019-04-09 16:32 ` Chris Wilson
@ 2019-04-10 8:05 ` Mika Kuoppala
0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-10 8:05 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:08)
>> There is no video turbo mode for gen11, so don't set it.
>>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 47f98e064de5..d6abba5c0b32 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6548,6 +6548,7 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
>> struct intel_rps *rps = &dev_priv->gt_pm.rps;
>> u32 threshold_up = 0, threshold_down = 0; /* in % */
>> u32 ei_up = 0, ei_down = 0;
>> + u32 media_turbo;
>>
>> lockdep_assert_held(&rps->power.mutex);
>>
>> @@ -6605,8 +6606,10 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
>> GT_INTERVAL_FROM_US(dev_priv,
>> ei_down * threshold_down / 100));
>>
>> + media_turbo = INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO;
>> +
>> I915_WRITE(GEN6_RP_CONTROL,
>> - GEN6_RP_MEDIA_TURBO |
>> + media_turbo |
>
> Looks short enough to fit inline?
It was inline at first. Then I thought that it was ugly and
gets pointed out in review and changed it. My heuristics
failed.
Well, inline coming up!
-mika
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock
2019-04-09 16:21 ` Chris Wilson
@ 2019-04-10 8:09 ` Mika Kuoppala
0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-10 8:09 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:09)
>> Unlike previous gens, we already hold the irq_lock on
>> entering the rps handler so we can't use it as it is.
>>
>> Make a gen11 specific rps interrupt handler without
>> locking.
>>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 6454ddc37f8b..619e6ab273e7 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1796,6 +1796,22 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>> /* The RPS events need forcewake, so we add them to a work queue and mask their
>> * IMR bits until the work is done. Other interrupts can be processed without
>> * the work queue. */
>> +static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
>> +{
>> + struct intel_rps *rps = &i915->gt_pm.rps;
>> + const u32 events = i915->pm_rps_events & pm_iir;
>> +
>> + lockdep_assert_held(&i915->irq_lock);
>> +
>> + if (events) {
>
> if (!events)
> return;
> ?
> Maybe you have reason for the indent later.
No reasons. I am avid fan of early return. This was explained by
copypasta from gen6 variant and then some interrupt event masked
between my ears. will send v2
>
>> + gen6_mask_pm_irq(i915, events);
>> + if (rps->interrupts_enabled) {
>> + rps->pm_iir |= events;
>> + schedule_work(&rps->work);
>> + }
>> + }
>
> All I can say is that this is evidence that we've never had an rps
> interrupt!
>
> I guess this patch needs to be first just in case an interrupt is
> sent.
Yeah, when got first ever sent, I witnessed spectacular fireworks.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Ta,
-Mika
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts
2019-04-09 16:26 ` Chris Wilson
@ 2019-04-10 8:20 ` Mika Kuoppala
0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2019-04-10 8:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:10)
>> With gen11 the interrupt registers are shared between 2 engines,
>> with Engine1 instance being upper word and Engine0 instance being
>> lower. Annoyingly gen11 selected the pm interrupts to be in the
>> Engine1 instance.
>
> Sounds weird, but I can't fault the solution. The choice would either to
> have been shift pm_rps_events andadd gen11_pm_imr/_ier, so this patch
> looks to be the smaller delta.
Small wart added is one extra posting read on disabling.
I didn't like the under the hood shifting but the much
smaller delta was too tempting.
Perhaps a comment to the register definitions
would be warranted at minimum.
-Mika
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
2019-04-10 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-04-10 9:04 ` Chris Wilson
0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2019-04-10 9:04 UTC (permalink / raw)
To: Mika Kuoppala, Patchwork; +Cc: intel-gfx
Quoting Patchwork (2019-04-10 06:59:20)
> #### Possible fixes ####
>
> * igt@i915_pm_rps@reset:
> - shard-iclb: FAIL [fdo#108059] -> PASS +2
\o/
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2019-04-10 9:04 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-09 16:13 [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Mika Kuoppala
2019-04-09 16:13 ` [PATCH 2/7] drm/i915/icl: Apply a recommended rc6 threshold Mika Kuoppala
2019-04-09 16:51 ` Michal Wajdeczko
2019-04-09 16:13 ` [PATCH 3/7] drm/i915/icl: Apply recommended rc6 idle hysteresis Mika Kuoppala
2019-04-09 16:16 ` Chris Wilson
2019-04-10 8:04 ` Mika Kuoppala
2019-04-09 16:13 ` [PATCH 4/7] drm/i915/icl: Enable media sampler powergate Mika Kuoppala
2019-04-09 16:34 ` Chris Wilson
2019-04-09 16:13 ` [PATCH 5/7] drm/i915/icl: Disable video turbo mode for rp control Mika Kuoppala
2019-04-09 16:32 ` Chris Wilson
2019-04-10 8:05 ` Mika Kuoppala
2019-04-09 16:13 ` [PATCH 6/7] drm/i915/icl: Handle rps interrupts without irq lock Mika Kuoppala
2019-04-09 16:21 ` Chris Wilson
2019-04-10 8:09 ` Mika Kuoppala
2019-04-09 16:13 ` [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts Mika Kuoppala
2019-04-09 16:26 ` Chris Wilson
2019-04-10 8:20 ` Mika Kuoppala
2019-04-09 16:28 ` [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 Chris Wilson
2019-04-09 16:57 ` Michal Wajdeczko
2019-04-09 17:04 ` Chris Wilson
2019-04-09 17:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2019-04-09 17:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-10 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-10 9:04 ` Chris Wilson
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