From: Stephen Boyd <sboyd@kernel.org> To: Nicolas Boichat <drinkcat@chromium.org>, Weiyi Lu <weiyi.lu@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com>, Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh@kernel.org>, James Liao <jamesjj.liao@mediatek.com>, Fan Chen <fan.chen@mediatek.com>, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, lkml <linux-kernel@vger.kernel.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>, linux-clk@vger.kernel.org, srv_heupstream <srv_heupstream@mediatek.com>, stable@vger.kernel.org, Owen Chen <owen.chen@mediatek.com>, Guenter Roeck <groeck@chromium.org> Subject: Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Date: Thu, 11 Apr 2019 13:12:55 -0700 [thread overview] Message-ID: <155501357547.20095.14128079106803580356@swboyd.mtv.corp.google.com> (raw) In-Reply-To: <CANMq1KCBnvscDcwvV-dqFbn+TTxZ97WXMdGZdmPOOter-0HxnQ@mail.gmail.com> (Please trim replies to save me time) Quoting Nicolas Boichat (2019-03-14 16:21:26) > On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > > +{ > > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > > + u32 val; > > + > > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > > + val = (val >> mux->data->mux_shift) & mask; > > + > > + return val; > > +} > > + > > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) > > +{ > > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > > + unsigned long flags; > > Guenter reported the following issue > (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1524422): > "" > The construct conditionally acquiring a spinlock is too complex for > gcc to understand. This results in the following build warning. > > drivers/clk/mediatek/clk-mux.c: In function > 'mtk_clk_mux_set_parent_lock': ./include/linux/spinlock.h:279:3: > warning: 'flags' may be used uninitialized in this function > > Other clock drivers avoid the problem by initializing flags with 0. > Lets do that here as well. > """ Ok. I'll squash in this fix. diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 877a883fa616..76f9cd039195 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -76,7 +76,7 @@ static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) { struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); u32 mask = GENMASK(mux->data->mux_width - 1, 0); - unsigned long flags; + unsigned long flags = 0; if (mux->lock) spin_lock_irqsave(mux->lock, flags); @@ -99,7 +99,7 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); u32 mask = GENMASK(mux->data->mux_width - 1, 0); u32 val, orig; - unsigned long flags; + unsigned long flags = 0; if (mux->lock) spin_lock_irqsave(mux->lock, flags);
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org> To: Nicolas Boichat <drinkcat@chromium.org>, Weiyi Lu <weiyi.lu@mediatek.com> Cc: Rob Herring <robh@kernel.org>, Guenter Roeck <groeck@chromium.org>, srv_heupstream <srv_heupstream@mediatek.com>, James Liao <jamesjj.liao@mediatek.com>, Stephen Boyd <sboyd@codeaurora.org>, lkml <linux-kernel@vger.kernel.org>, stable@vger.kernel.org, Fan Chen <fan.chen@mediatek.com>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>, Matthias Brugger <matthias.bgg@gmail.com>, Owen Chen <owen.chen@mediatek.com>, linux-clk@vger.kernel.org, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Date: Thu, 11 Apr 2019 13:12:55 -0700 [thread overview] Message-ID: <155501357547.20095.14128079106803580356@swboyd.mtv.corp.google.com> (raw) In-Reply-To: <CANMq1KCBnvscDcwvV-dqFbn+TTxZ97WXMdGZdmPOOter-0HxnQ@mail.gmail.com> (Please trim replies to save me time) Quoting Nicolas Boichat (2019-03-14 16:21:26) > On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > > +{ > > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > > + u32 val; > > + > > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > > + val = (val >> mux->data->mux_shift) & mask; > > + > > + return val; > > +} > > + > > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) > > +{ > > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > > + unsigned long flags; > > Guenter reported the following issue > (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1524422): > "" > The construct conditionally acquiring a spinlock is too complex for > gcc to understand. This results in the following build warning. > > drivers/clk/mediatek/clk-mux.c: In function > 'mtk_clk_mux_set_parent_lock': ./include/linux/spinlock.h:279:3: > warning: 'flags' may be used uninitialized in this function > > Other clock drivers avoid the problem by initializing flags with 0. > Lets do that here as well. > """ Ok. I'll squash in this fix. diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 877a883fa616..76f9cd039195 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -76,7 +76,7 @@ static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) { struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); u32 mask = GENMASK(mux->data->mux_width - 1, 0); - unsigned long flags; + unsigned long flags = 0; if (mux->lock) spin_lock_irqsave(mux->lock, flags); @@ -99,7 +99,7 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); u32 mask = GENMASK(mux->data->mux_width - 1, 0); u32 val, orig; - unsigned long flags; + unsigned long flags = 0; if (mux->lock) spin_lock_irqsave(mux->lock, flags); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-04-11 20:12 UTC|newest] Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-05 5:05 [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:42 ` James Liao 2019-03-05 6:42 ` James Liao 2019-03-05 6:42 ` James Liao 2019-03-07 16:09 ` Matthias Brugger 2019-03-07 16:09 ` Matthias Brugger 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:43 ` James Liao 2019-03-05 6:43 ` James Liao 2019-03-05 6:43 ` James Liao 2019-03-08 6:17 ` Nicolas Boichat 2019-03-08 6:17 ` Nicolas Boichat 2019-03-08 6:17 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-04-11 20:12 ` Stephen Boyd [this message] 2019-04-11 20:12 ` Stephen Boyd 2019-04-11 20:12 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:46 ` James Liao 2019-03-05 6:46 ` James Liao 2019-03-05 6:46 ` James Liao 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 4/9] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` [PATCH v5 5/9] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-04-11 20:19 ` Stephen Boyd 2019-04-11 20:19 ` Stephen Boyd 2019-04-11 20:19 ` Stephen Boyd 2019-04-12 2:42 ` Weiyi Lu 2019-04-12 2:42 ` Weiyi Lu 2019-04-12 2:42 ` Weiyi Lu 2019-03-05 5:05 ` [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-08 6:23 ` Nicolas Boichat 2019-03-08 6:23 ` Nicolas Boichat 2019-03-08 6:23 ` Nicolas Boichat 2019-04-11 20:21 ` Stephen Boyd 2019-04-11 20:21 ` Stephen Boyd 2019-04-11 20:21 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 8/9] clk: mediatek: Add MT8183 clock support Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:48 ` James Liao 2019-03-05 6:48 ` James Liao 2019-03-05 6:48 ` James Liao 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-03-28 5:18 ` [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu 2019-03-28 5:18 ` Weiyi Lu 2019-03-28 5:18 ` Weiyi Lu
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