* [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize and refactor MSA instructions ILVEV.<B|H|W|D>,
ILVOD.<B|H|W|D>, ILVL.<B|H|W|D> and ILVR.<B|H|W|D>.
v9:
- Tests were changed, instead of iterating through the
loop 10 million times and calling the instruction
once, iterate through the loop 1 million times, and
call the instruction ten times.
- Eliminate the hybrid approach in ILVL.<B|H|W|D> and
ILVR.<B|H|W|D>, because the performance of directly
using TCG registers is much better than the
performance of the handler.
- Change the tables in the commit messages, due to
modified performance testing program.
v8:
- Rebased onto current master branch.
- Inserted Reviewed-by in the applicable commit message.
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV.<B|H> and ILVOD.<B|H> instructions.
- Refactor gen_ilvod_b and gen_ilvod_h functions. Use
the shared function gen_ilvod_bh, which has two extra
arguments mask and shift, because mask and shift are
the only differences in the implementation of those
two functions.
Same applies for gen_ilvev_b and gen_ilvev_h.
- Use assigning uint64_t constant values to the bit mask,
instead of shifting the bit mask, in ILVR.<H|W> and
ILVL.<H|W> instructions.
- Use only one helper for ILVEV.D and ILVR.D instructions,
because they are equivalent.
Same applies for ILVOD.D and ILVL.D.
- Minor changes in the commit messages.
v6:
- Add ILVL.<B|H|W|D> and ILVR.<B|H|W|D> MSA instructions
with mixed approaches (with helpers and with tcg
registers).
- Test the performance for ILVL.<B|H|W|D> and
ILVR.<B|H|W|D> MSA instructions, with helpers,
with tcg and with the mixed approach.
- Use a tcg register instead of an int variable for
storing a constant value of the mask (for logic
operations).
- Eliminate some unnecessary tcg_gen calls.
- Changes in commit messages and the cover letter.
v5:
- Use tcg_gen_deposit function.
- Added performance number for no-deposit and
with-deposit cases of ILVEV.W.
- Minor changes in commit messages and the cover letter.
v4:
- Clean up typing errors.
- Change the commit message and the cover letter.
- Fix bug for ILVEV.D, in case where the destination
and one of the sources are the same register.
v3:
- Reduce the number of logic operations to a
minimum.
- Add comments.
v2:
- Minor changes in commit messages and the cover letter.
Mateja Marjanovic (6):
target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions
target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions
target/mips: Optimize ILVL.<B|H|W|D> MSA instructions
target/mips: Optimize ILVR.<B|H|W|D> MSA instructions
target/mips: Merge implementation of ILVEV.D and ILVR.D
target/mips: Merge implementation of ILVOD.D and ILVL.D
target/mips/helper.h | 4 -
target/mips/msa_helper.c | 32 ---
target/mips/translate.c | 532 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 528 insertions(+), 40 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize and refactor MSA instructions ILVEV.<B|H|W|D>,
ILVOD.<B|H|W|D>, ILVL.<B|H|W|D> and ILVR.<B|H|W|D>.
v9:
- Tests were changed, instead of iterating through the
loop 10 million times and calling the instruction
once, iterate through the loop 1 million times, and
call the instruction ten times.
- Eliminate the hybrid approach in ILVL.<B|H|W|D> and
ILVR.<B|H|W|D>, because the performance of directly
using TCG registers is much better than the
performance of the handler.
- Change the tables in the commit messages, due to
modified performance testing program.
v8:
- Rebased onto current master branch.
- Inserted Reviewed-by in the applicable commit message.
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV.<B|H> and ILVOD.<B|H> instructions.
- Refactor gen_ilvod_b and gen_ilvod_h functions. Use
the shared function gen_ilvod_bh, which has two extra
arguments mask and shift, because mask and shift are
the only differences in the implementation of those
two functions.
Same applies for gen_ilvev_b and gen_ilvev_h.
- Use assigning uint64_t constant values to the bit mask,
instead of shifting the bit mask, in ILVR.<H|W> and
ILVL.<H|W> instructions.
- Use only one helper for ILVEV.D and ILVR.D instructions,
because they are equivalent.
Same applies for ILVOD.D and ILVL.D.
- Minor changes in the commit messages.
v6:
- Add ILVL.<B|H|W|D> and ILVR.<B|H|W|D> MSA instructions
with mixed approaches (with helpers and with tcg
registers).
- Test the performance for ILVL.<B|H|W|D> and
ILVR.<B|H|W|D> MSA instructions, with helpers,
with tcg and with the mixed approach.
- Use a tcg register instead of an int variable for
storing a constant value of the mask (for logic
operations).
- Eliminate some unnecessary tcg_gen calls.
- Changes in commit messages and the cover letter.
v5:
- Use tcg_gen_deposit function.
- Added performance number for no-deposit and
with-deposit cases of ILVEV.W.
- Minor changes in commit messages and the cover letter.
v4:
- Clean up typing errors.
- Change the commit message and the cover letter.
- Fix bug for ILVEV.D, in case where the destination
and one of the sources are the same register.
v3:
- Reduce the number of logic operations to a
minimum.
- Add comments.
v2:
- Minor changes in commit messages and the cover letter.
Mateja Marjanovic (6):
target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions
target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions
target/mips: Optimize ILVL.<B|H|W|D> MSA instructions
target/mips: Optimize ILVR.<B|H|W|D> MSA instructions
target/mips: Merge implementation of ILVEV.D and ILVR.D
target/mips: Merge implementation of ILVOD.D and ILVL.D
target/mips/helper.h | 4 -
target/mips/msa_helper.c | 32 ---
target/mips/translate.c | 532 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 528 insertions(+), 40 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize set of MSA instructions ILVOD.<B|H|W|D>, using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers to tcg, but without using
tcg_gen_deposit function. The third one is with the deposit
function and with using a uint64_t constant bit mask, and
the fourth is with the deposit function and with a mask
which is a tcg constant. The fourth is implemented in this
patch.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===================================================================
|| instruction || 1 || 2 || 3 || 4 ||
===================================================================
|| ilvod.b || 107.585 ms || 2.717 ms || 2.572 ms || 2.373 ms ||
|| ilvod.h || 82.871 ms || 2.420 ms || 2.414 ms || 2.320 ms ||
|| ilvod.w || 109.722 ms || 2.702 ms || 2.348 ms || 2.303 ms ||
|| ilvod.d || 30.813 ms || 2.083 ms || 2.036 ms || 2.036 ms ||
===================================================================
1 - before
2 - no-deposit-no-mask-as-tcg-constant
3 - with-deposit-no-mask-as-tcg-constant
4 - with-deposit-with-mask-as-tcg-constant (final)
The deposit function is used only in ILVOD.W.
No-deposit version of the ILVOD.W implementation:
static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
uint32_t ws, uint32_t wt)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_const_i64(0xffffffff00000000ULL);
tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask);
tcg_gen_shri_i64(t1, t1, 32);
tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask);
tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask);
tcg_gen_shri_i64(t1, t1, 32);
tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask);
tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
tcg_temp_free_i64(mask);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 7 ----
target/mips/translate.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 90 insertions(+), 9 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index a6d687e..d162836 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -865,7 +865,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c74e3cd..9e52a31 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1206,13 +1206,6 @@ MSA_FN_DF(ilvr_df)
MSA_FN_DF(ilvev_df)
#undef MSA_DO
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = pwt->DF[2*i+1]; \
- pwx->DF[2*i+1] = pws->DF[2*i+1]; \
- } while (0)
-MSA_FN_DF(ilvod_df)
-#undef MSA_DO
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 364bd6d..99bd441 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28001,6 +28001,80 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tws);
}
+/*
+ * [MSA] ILVOD.<B|H> wd, ws, wt
+ *
+ * Vector Interleave Odd (<byte|halfword> data elements)
+ *
+ */
+static inline void gen_ilvod_bh(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt,
+ uint64_t mask, uint32_t shift)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 mask_tcg = tcg_const_i64(mask);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask_tcg);
+ tcg_gen_shri_i64(t1, t1, shift);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask_tcg);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask_tcg);
+ tcg_gen_shri_i64(t1, t1, shift);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask_tcg);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
+
+ tcg_temp_free_i64(mask_tcg);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static inline void gen_ilvod_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvod_bh(env, wd, ws, wt, 0xff00ff00ff00ff00ULL, 8);
+}
+
+static inline void gen_ilvod_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvod_bh(env, wd, ws, wt, 0xffff0000ffff0000ULL, 16);
+}
+
+/*
+ * [MSA] ILVOD.W wd, ws, wt
+ *
+ * Vector Interleave Odd (word data elements)
+ *
+ */
+static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t1, msa_wr_d[wt * 2], 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2], msa_wr_d[ws * 2], t1, 0, 32);
+
+ tcg_gen_shri_i64(t1, msa_wr_d[wt * 2 + 1], 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1], t1, 0, 32);
+
+ tcg_temp_free_i64(t1);
+}
+
+/*
+ * [MSA] ILVOD.D wd, ws, wt
+ *
+ * Vector Interleave Odd (doubleword data elements)
+ *
+ */
+static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
+}
+
static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -28172,7 +28246,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVOD_df:
- gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvod_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvod_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvod_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvod_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_DOTP_S_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize set of MSA instructions ILVOD.<B|H|W|D>, using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers to tcg, but without using
tcg_gen_deposit function. The third one is with the deposit
function and with using a uint64_t constant bit mask, and
the fourth is with the deposit function and with a mask
which is a tcg constant. The fourth is implemented in this
patch.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===================================================================
|| instruction || 1 || 2 || 3 || 4 ||
===================================================================
|| ilvod.b || 107.585 ms || 2.717 ms || 2.572 ms || 2.373 ms ||
|| ilvod.h || 82.871 ms || 2.420 ms || 2.414 ms || 2.320 ms ||
|| ilvod.w || 109.722 ms || 2.702 ms || 2.348 ms || 2.303 ms ||
|| ilvod.d || 30.813 ms || 2.083 ms || 2.036 ms || 2.036 ms ||
===================================================================
1 - before
2 - no-deposit-no-mask-as-tcg-constant
3 - with-deposit-no-mask-as-tcg-constant
4 - with-deposit-with-mask-as-tcg-constant (final)
The deposit function is used only in ILVOD.W.
No-deposit version of the ILVOD.W implementation:
static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
uint32_t ws, uint32_t wt)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_const_i64(0xffffffff00000000ULL);
tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask);
tcg_gen_shri_i64(t1, t1, 32);
tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask);
tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask);
tcg_gen_shri_i64(t1, t1, 32);
tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask);
tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
tcg_temp_free_i64(mask);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 7 ----
target/mips/translate.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 90 insertions(+), 9 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index a6d687e..d162836 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -865,7 +865,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c74e3cd..9e52a31 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1206,13 +1206,6 @@ MSA_FN_DF(ilvr_df)
MSA_FN_DF(ilvev_df)
#undef MSA_DO
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = pwt->DF[2*i+1]; \
- pwx->DF[2*i+1] = pws->DF[2*i+1]; \
- } while (0)
-MSA_FN_DF(ilvod_df)
-#undef MSA_DO
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 364bd6d..99bd441 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28001,6 +28001,80 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tws);
}
+/*
+ * [MSA] ILVOD.<B|H> wd, ws, wt
+ *
+ * Vector Interleave Odd (<byte|halfword> data elements)
+ *
+ */
+static inline void gen_ilvod_bh(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt,
+ uint64_t mask, uint32_t shift)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 mask_tcg = tcg_const_i64(mask);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask_tcg);
+ tcg_gen_shri_i64(t1, t1, shift);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask_tcg);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask_tcg);
+ tcg_gen_shri_i64(t1, t1, shift);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask_tcg);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
+
+ tcg_temp_free_i64(mask_tcg);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static inline void gen_ilvod_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvod_bh(env, wd, ws, wt, 0xff00ff00ff00ff00ULL, 8);
+}
+
+static inline void gen_ilvod_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvod_bh(env, wd, ws, wt, 0xffff0000ffff0000ULL, 16);
+}
+
+/*
+ * [MSA] ILVOD.W wd, ws, wt
+ *
+ * Vector Interleave Odd (word data elements)
+ *
+ */
+static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t1, msa_wr_d[wt * 2], 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2], msa_wr_d[ws * 2], t1, 0, 32);
+
+ tcg_gen_shri_i64(t1, msa_wr_d[wt * 2 + 1], 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1], t1, 0, 32);
+
+ tcg_temp_free_i64(t1);
+}
+
+/*
+ * [MSA] ILVOD.D wd, ws, wt
+ *
+ * Vector Interleave Odd (doubleword data elements)
+ *
+ */
+static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
+}
+
static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -28172,7 +28246,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVOD_df:
- gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvod_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvod_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvod_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvod_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_DOTP_S_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 2/6] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize set of MSA instructions ILVEV.<B|H|W|D>, using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers to tcg, but without using
tcg_gen_deposit function. The third one is with using the
tcg_gen_deposit function and with using a uint64_t constant
bit mask, and the fourth is with using the tcg_gen_deposit
function and with a mask which is a tcg constant. The fourth
is implemented in this patch.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===================================================================
|| instruction || 1 || 2 || 3 || 4 ||
===================================================================
|| ilvev.b || 107.592 ms || 2.432 ms || 2.381 ms || 2.599 ms ||
|| ilvev.h || 83.422 ms || 2.352 ms || 2.623 ms || 2.532 ms ||
|| ilvev.w || 109.300 ms || 2.342 ms || 2.329 ms || 2.266 ms ||
|| ilvev.d || 30.915 ms || 1.926 ms || 2.002 ms || 1.976 ms ||
===================================================================
1 - before
2 - no-deposit-no-mask-as-tcg-constant
3 - with-deposit-no-mask-as-tcg-constant
4 - with-deposit-with-mask-as-tcg-constant (final)
The deposit function is used only in ILVEV.W.
No-deposit version of the ILVEV.W implementation:
static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
uint32_t ws, uint32_t wt)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
uint64_t mask = 0x00000000ffffffffULL;
tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
tcg_gen_andi_i64(t2, msa_wr_d[ws * 2], mask);
tcg_gen_shli_i64(t2, t2, 32);
tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
tcg_gen_andi_i64(t2, msa_wr_d[ws * 2 + 1], mask);
tcg_gen_shli_i64(t2, t2, 32);
tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 9 -----
target/mips/translate.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 86 insertions(+), 11 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d162836..2f23b0d 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -864,7 +864,6 @@ DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 9e52a31..a500c59 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1197,15 +1197,6 @@ MSA_FN_DF(ilvl_df)
} while (0)
MSA_FN_DF(ilvr_df)
#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = pwt->DF[2*i]; \
- pwx->DF[2*i+1] = pws->DF[2*i]; \
- } while (0)
-MSA_FN_DF(ilvev_df)
-#undef MSA_DO
-
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 99bd441..930ef3a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28075,6 +28075,76 @@ static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
}
+
+/*
+ * [MSA] ILVEV.<B|H> wd, ws, wt
+ *
+ * Vector Interleave Even (<byte|halfword> data elements)
+ *
+ */
+static inline void gen_ilvev_bh(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt,
+ uint64_t mask, uint32_t shift)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 mask_tcg = tcg_const_i64(mask);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask_tcg);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask_tcg);
+ tcg_gen_shli_i64(t2, t2, shift);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask_tcg);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask_tcg);
+ tcg_gen_shli_i64(t2, t2, shift);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
+
+ tcg_temp_free_i64(mask_tcg);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static inline void gen_ilvev_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvev_bh(env, wd, ws, wt, 0x00ff00ff00ff00ffULL, 8);
+}
+
+static inline void gen_ilvev_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvev_bh(env, wd, ws, wt, 0x0000ffff0000ffffULL, 16);
+}
+
+/*
+ * [MSA] ILVEV.W wd, ws, wt
+ *
+ * Vector Interleave Even (word data elements)
+ *
+ */
+static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2],
+ msa_wr_d[ws * 2], 32, 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[wt * 2 + 1],
+ msa_wr_d[ws * 2 + 1], 32, 32);
+}
+
+/*
+ * [MSA] ILVEV.D wd, ws, wt
+ *
+ * Vector Interleave Even (Doubleword data elements)
+ *
+ */
+static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
+}
+
static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -28231,7 +28301,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVEV_df:
- gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvev_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvev_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvev_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvev_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BINSR_df:
gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 2/6] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize set of MSA instructions ILVEV.<B|H|W|D>, using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers to tcg, but without using
tcg_gen_deposit function. The third one is with using the
tcg_gen_deposit function and with using a uint64_t constant
bit mask, and the fourth is with using the tcg_gen_deposit
function and with a mask which is a tcg constant. The fourth
is implemented in this patch.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===================================================================
|| instruction || 1 || 2 || 3 || 4 ||
===================================================================
|| ilvev.b || 107.592 ms || 2.432 ms || 2.381 ms || 2.599 ms ||
|| ilvev.h || 83.422 ms || 2.352 ms || 2.623 ms || 2.532 ms ||
|| ilvev.w || 109.300 ms || 2.342 ms || 2.329 ms || 2.266 ms ||
|| ilvev.d || 30.915 ms || 1.926 ms || 2.002 ms || 1.976 ms ||
===================================================================
1 - before
2 - no-deposit-no-mask-as-tcg-constant
3 - with-deposit-no-mask-as-tcg-constant
4 - with-deposit-with-mask-as-tcg-constant (final)
The deposit function is used only in ILVEV.W.
No-deposit version of the ILVEV.W implementation:
static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
uint32_t ws, uint32_t wt)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
uint64_t mask = 0x00000000ffffffffULL;
tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
tcg_gen_andi_i64(t2, msa_wr_d[ws * 2], mask);
tcg_gen_shli_i64(t2, t2, 32);
tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
tcg_gen_andi_i64(t2, msa_wr_d[ws * 2 + 1], mask);
tcg_gen_shli_i64(t2, t2, 32);
tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 9 -----
target/mips/translate.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 86 insertions(+), 11 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d162836..2f23b0d 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -864,7 +864,6 @@ DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 9e52a31..a500c59 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1197,15 +1197,6 @@ MSA_FN_DF(ilvl_df)
} while (0)
MSA_FN_DF(ilvr_df)
#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = pwt->DF[2*i]; \
- pwx->DF[2*i+1] = pws->DF[2*i]; \
- } while (0)
-MSA_FN_DF(ilvev_df)
-#undef MSA_DO
-
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 99bd441..930ef3a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28075,6 +28075,76 @@ static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
}
+
+/*
+ * [MSA] ILVEV.<B|H> wd, ws, wt
+ *
+ * Vector Interleave Even (<byte|halfword> data elements)
+ *
+ */
+static inline void gen_ilvev_bh(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt,
+ uint64_t mask, uint32_t shift)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 mask_tcg = tcg_const_i64(mask);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask_tcg);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask_tcg);
+ tcg_gen_shli_i64(t2, t2, shift);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
+
+ tcg_gen_and_i64(t1, msa_wr_d[wt * 2 + 1], mask_tcg);
+ tcg_gen_and_i64(t2, msa_wr_d[ws * 2 + 1], mask_tcg);
+ tcg_gen_shli_i64(t2, t2, shift);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t1, t2);
+
+ tcg_temp_free_i64(mask_tcg);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static inline void gen_ilvev_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvev_bh(env, wd, ws, wt, 0x00ff00ff00ff00ffULL, 8);
+}
+
+static inline void gen_ilvev_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ gen_ilvev_bh(env, wd, ws, wt, 0x0000ffff0000ffffULL, 16);
+}
+
+/*
+ * [MSA] ILVEV.W wd, ws, wt
+ *
+ * Vector Interleave Even (word data elements)
+ *
+ */
+static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2],
+ msa_wr_d[ws * 2], 32, 32);
+ tcg_gen_deposit_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[wt * 2 + 1],
+ msa_wr_d[ws * 2 + 1], 32, 32);
+}
+
+/*
+ * [MSA] ILVEV.D wd, ws, wt
+ *
+ * Vector Interleave Even (Doubleword data elements)
+ *
+ */
+static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
+}
+
static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -28231,7 +28301,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVEV_df:
- gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvev_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvev_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvev_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvev_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BINSR_df:
gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 3/6] target/mips: Optimize ILVL.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize ILVL.<B|H|W|D> instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===========================================================
|| instruction || BEFORE || LOOP UNROLL || TCG ||
===========================================================
|| ilvl.b || 107.069 ms || 55.619 ms || 7.735 ms ||
|| ilvl.h || 83.340 ms || 31.320 ms || 3.797 ms ||
|| ilvl.w || 109.448 ms || 31.714 ms || 2.381 ms ||
|| ilvl.d || 31.557 ms || 28.716 ms || 2.029 ms ||
===========================================================
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 8 ---
target/mips/translate.c | 184 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 183 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 2f23b0d..85c8b17 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -862,7 +862,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index a500c59..f9b85fc 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1184,14 +1184,6 @@ MSA_FN_DF(pckod_df)
#define MSA_DO(DF) \
do { \
- pwx->DF[2*i] = L##DF(pwt, i); \
- pwx->DF[2*i+1] = L##DF(pws, i); \
- } while (0)
-MSA_FN_DF(ilvl_df)
-#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
pwx->DF[2*i] = R##DF(pwt, i); \
pwx->DF[2*i+1] = R##DF(pws, i); \
} while (0)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 930ef3a..d9aef77 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28002,6 +28002,173 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
}
/*
+ * [MSA] ILVL.B wd, ws, wt
+ *
+ * Vector Interleave Left (byte data elements)
+ *
+ */
+static inline void gen_ilvl_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000000000ffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x000000000000ff00ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000000000ff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ff000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x000000ff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000ff0000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00ff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xff00000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.H wd, ws, wt
+ *
+ * Vector Interleave Left (halfword data elements)
+ *
+ */
+static inline void gen_ilvl_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x000000000000ffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ffff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x0000ffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xffff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.W wd, ws, wt
+ *
+ * Vector Interleave Left (word data elements)
+ *
+ */
+static inline void gen_ilvl_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000ffffffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0xffffffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.D wd, ws, wt
+ *
+ * Vector Interleave Left (doubleword data elements)
+ *
+ */
+static inline void gen_ilvl_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
+}
+
+/*
* [MSA] ILVOD.<B|H> wd, ws, wt
*
* Vector Interleave Odd (<byte|halfword> data elements)
@@ -28265,7 +28432,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVL_df:
- gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvl_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvl_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvl_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvl_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BNEG_df:
gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 3/6] target/mips: Optimize ILVL.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize ILVL.<B|H|W|D> instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===========================================================
|| instruction || BEFORE || LOOP UNROLL || TCG ||
===========================================================
|| ilvl.b || 107.069 ms || 55.619 ms || 7.735 ms ||
|| ilvl.h || 83.340 ms || 31.320 ms || 3.797 ms ||
|| ilvl.w || 109.448 ms || 31.714 ms || 2.381 ms ||
|| ilvl.d || 31.557 ms || 28.716 ms || 2.029 ms ||
===========================================================
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 8 ---
target/mips/translate.c | 184 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 183 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 2f23b0d..85c8b17 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -862,7 +862,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index a500c59..f9b85fc 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1184,14 +1184,6 @@ MSA_FN_DF(pckod_df)
#define MSA_DO(DF) \
do { \
- pwx->DF[2*i] = L##DF(pwt, i); \
- pwx->DF[2*i+1] = L##DF(pws, i); \
- } while (0)
-MSA_FN_DF(ilvl_df)
-#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
pwx->DF[2*i] = R##DF(pwt, i); \
pwx->DF[2*i+1] = R##DF(pws, i); \
} while (0)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 930ef3a..d9aef77 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28002,6 +28002,173 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
}
/*
+ * [MSA] ILVL.B wd, ws, wt
+ *
+ * Vector Interleave Left (byte data elements)
+ *
+ */
+static inline void gen_ilvl_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000000000ffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x000000000000ff00ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000000000ff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ff000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x000000ff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000ff0000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00ff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xff00000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.H wd, ws, wt
+ *
+ * Vector Interleave Left (halfword data elements)
+ *
+ */
+static inline void gen_ilvl_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x000000000000ffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ffff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x0000ffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xffff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.W wd, ws, wt
+ *
+ * Vector Interleave Left (word data elements)
+ *
+ */
+static inline void gen_ilvl_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000ffffffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0xffffffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2 + 1], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2 + 1], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVL.D wd, ws, wt
+ *
+ * Vector Interleave Left (doubleword data elements)
+ *
+ */
+static inline void gen_ilvl_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
+}
+
+/*
* [MSA] ILVOD.<B|H> wd, ws, wt
*
* Vector Interleave Odd (<byte|halfword> data elements)
@@ -28265,7 +28432,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVL_df:
- gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvl_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvl_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvl_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvl_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BNEG_df:
gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize ILVR.<B|H|W|D> instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===========================================================
|| instruction || BEFORE || LOOP UNROLL || TCG ||
===========================================================
|| ilvr.b || 106.461 ms || 52.131 ms || 7.813 ms ||
|| ilvr.h || 82.962 ms || 36.222 ms || 3.622 ms ||
|| ilvr.w || 109.451 ms || 33.042 ms || 2.331 ms ||
|| ilvr.d || 32.270 ms || 27.328 ms || 2.025 ms ||
===========================================================
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 8 ---
target/mips/translate.c | 184 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 183 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 85c8b17..c1681da 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -862,7 +862,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f9b85fc..4cb0929 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1181,14 +1181,6 @@ MSA_FN_DF(pckev_df)
} while (0)
MSA_FN_DF(pckod_df)
#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = R##DF(pwt, i); \
- pwx->DF[2*i+1] = R##DF(pws, i); \
- } while (0)
-MSA_FN_DF(ilvr_df)
-#undef MSA_DO
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d9aef77..214736c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28002,6 +28002,173 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
}
/*
+ * [MSA] ILVR.B wd, ws, wt
+ *
+ * Vector Interleave Right (byte data elements)
+ *
+ */
+static inline void gen_ilvr_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000000000ffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x000000000000ff00ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000000000ff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ff000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x000000ff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000ff0000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00ff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xff00000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.H wd, ws, wt
+ *
+ * Vector Interleave Right (halfword data elements)
+ *
+ */
+static inline void gen_ilvr_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x000000000000ffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ffff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x0000ffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xffff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.W wd, ws, wt
+ *
+ * Vector Interleave Right (word data elements)
+ *
+ */
+static inline void gen_ilvr_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000ffffffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0xffffffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.D wd, ws, wt
+ *
+ * Vector Interleave Right (doubleword data elements)
+ *
+ */
+static inline void gen_ilvr_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
+}
+
+/*
* [MSA] ILVL.B wd, ws, wt
*
* Vector Interleave Left (byte data elements)
@@ -28468,7 +28635,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVR_df:
- gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvr_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvr_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvr_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvr_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BINSL_df:
gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Optimize ILVR.<B|H|W|D> instructions, using
directly tcg registers and logic performed on
them, and instead of shifting the bit mask or
assigning a new tcg constant to the bit mask,
assign a new (shifted) uint64_t value to the
bit mask.
Performance measurement is done by executing the
instructions 10 million times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8.
===========================================================
|| instruction || BEFORE || LOOP UNROLL || TCG ||
===========================================================
|| ilvr.b || 106.461 ms || 52.131 ms || 7.813 ms ||
|| ilvr.h || 82.962 ms || 36.222 ms || 3.622 ms ||
|| ilvr.w || 109.451 ms || 33.042 ms || 2.331 ms ||
|| ilvr.d || 32.270 ms || 27.328 ms || 2.025 ms ||
===========================================================
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 1 -
target/mips/msa_helper.c | 8 ---
target/mips/translate.c | 184 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 183 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 85c8b17..c1681da 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -862,7 +862,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f9b85fc..4cb0929 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1181,14 +1181,6 @@ MSA_FN_DF(pckev_df)
} while (0)
MSA_FN_DF(pckod_df)
#undef MSA_DO
-
-#define MSA_DO(DF) \
- do { \
- pwx->DF[2*i] = R##DF(pwt, i); \
- pwx->DF[2*i+1] = R##DF(pws, i); \
- } while (0)
-MSA_FN_DF(ilvr_df)
-#undef MSA_DO
#undef MSA_LOOP_COND
#define MSA_LOOP_COND(DF) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d9aef77..214736c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28002,6 +28002,173 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
}
/*
+ * [MSA] ILVR.B wd, ws, wt
+ *
+ * Vector Interleave Right (byte data elements)
+ *
+ */
+static inline void gen_ilvr_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000000000ffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x000000000000ff00ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000000000ff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ff000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x000000ff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x0000ff0000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 24);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00ff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xff00000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 8);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.H wd, ws, wt
+ *
+ * Vector Interleave Right (halfword data elements)
+ *
+ */
+static inline void gen_ilvr_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x000000000000ffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0x00000000ffff0000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0x0000ffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+
+ mask = 0xffff000000000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t2, t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.W wd, ws, wt
+ *
+ * Vector Interleave Right (word data elements)
+ *
+ */
+static inline void gen_ilvr_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint64_t mask = 0x00000000ffffffffULL;
+
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_shli_i64(t1, t1, 32);
+ tcg_gen_or_i64(msa_wr_d[wd * 2], t2, t1);
+
+ mask = 0xffffffff00000000ULL;
+ tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_mov_i64(t2, t1);
+ tcg_gen_andi_i64(t1, msa_wr_d[ws * 2], mask);
+ tcg_gen_or_i64(msa_wr_d[wd * 2 + 1], t2, t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * [MSA] ILVR.D wd, ws, wt
+ *
+ * Vector Interleave Right (doubleword data elements)
+ *
+ */
+static inline void gen_ilvr_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+ tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
+ tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
+}
+
+/*
* [MSA] ILVL.B wd, ws, wt
*
* Vector Interleave Left (byte data elements)
@@ -28468,7 +28635,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVR_df:
- gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_ilvr_b(env, wd, ws, wt);
+ break;
+ case DF_HALF:
+ gen_ilvr_h(env, wd, ws, wt);
+ break;
+ case DF_WORD:
+ gen_ilvr_w(env, wd, ws, wt);
+ break;
+ case DF_DOUBLE:
+ gen_ilvr_d(env, wd, ws, wt);
+ break;
+ default:
+ assert(0);
+ }
break;
case OPC_BINSL_df:
gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 214736c..019a2c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28156,19 +28156,6 @@ static inline void gen_ilvr_w(CPUMIPSState *env, uint32_t wd,
}
/*
- * [MSA] ILVR.D wd, ws, wt
- *
- * Vector Interleave Right (doubleword data elements)
- *
- */
-static inline void gen_ilvr_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
-}
-
-/*
* [MSA] ILVL.B wd, ws, wt
*
* Vector Interleave Left (byte data elements)
@@ -28469,11 +28456,17 @@ static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
/*
* [MSA] ILVEV.D wd, ws, wt
*
- * Vector Interleave Even (Doubleword data elements)
+ * Vector Interleave Even (doubleword data elements)
+ *
+ * [MSA] ILVR.D wd, ws, wt
+ *
+ * Vector Interleave Right (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
*
*/
-static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
+static inline void gen_ilvev_ilvr_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
@@ -28646,7 +28639,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvr_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvr_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -28676,7 +28669,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvev_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvev_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 214736c..019a2c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28156,19 +28156,6 @@ static inline void gen_ilvr_w(CPUMIPSState *env, uint32_t wd,
}
/*
- * [MSA] ILVR.D wd, ws, wt
- *
- * Vector Interleave Right (doubleword data elements)
- *
- */
-static inline void gen_ilvr_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
-}
-
-/*
* [MSA] ILVL.B wd, ws, wt
*
* Vector Interleave Left (byte data elements)
@@ -28469,11 +28456,17 @@ static inline void gen_ilvev_w(CPUMIPSState *env, uint32_t wd,
/*
* [MSA] ILVEV.D wd, ws, wt
*
- * Vector Interleave Even (Doubleword data elements)
+ * Vector Interleave Even (doubleword data elements)
+ *
+ * [MSA] ILVR.D wd, ws, wt
+ *
+ * Vector Interleave Right (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
*
*/
-static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
+static inline void gen_ilvev_ilvr_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
@@ -28646,7 +28639,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvr_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvr_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -28676,7 +28669,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvev_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvev_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, philmd, richard.henderson, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 019a2c0..020a659 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28310,19 +28310,6 @@ static inline void gen_ilvl_w(CPUMIPSState *env, uint32_t wd,
}
/*
- * [MSA] ILVL.D wd, ws, wt
- *
- * Vector Interleave Left (doubleword data elements)
- *
- */
-static inline void gen_ilvl_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
-}
-
-/*
* [MSA] ILVOD.<B|H> wd, ws, wt
*
* Vector Interleave Odd (<byte|halfword> data elements)
@@ -28388,9 +28375,15 @@ static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
*
* Vector Interleave Odd (doubleword data elements)
*
+ * [MSA] ILVL.D wd, ws, wt
+ *
+ * Vector Interleave Left (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
+ *
*/
-static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
+static inline void gen_ilvod_ilvl_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
@@ -28603,7 +28596,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvl_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvl_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -28699,7 +28692,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvod_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvod_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D
@ 2019-04-18 15:29 ` Mateja Marjanovic
0 siblings, 0 replies; 18+ messages in thread
From: Mateja Marjanovic @ 2019-04-18 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, richard.henderson, philmd, amarkovic, aurelien
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 019a2c0..020a659 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28310,19 +28310,6 @@ static inline void gen_ilvl_w(CPUMIPSState *env, uint32_t wd,
}
/*
- * [MSA] ILVL.D wd, ws, wt
- *
- * Vector Interleave Left (doubleword data elements)
- *
- */
-static inline void gen_ilvl_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
-}
-
-/*
* [MSA] ILVOD.<B|H> wd, ws, wt
*
* Vector Interleave Odd (<byte|halfword> data elements)
@@ -28388,9 +28375,15 @@ static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
*
* Vector Interleave Odd (doubleword data elements)
*
+ * [MSA] ILVL.D wd, ws, wt
+ *
+ * Vector Interleave Left (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
+ *
*/
-static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
+static inline void gen_ilvod_ilvl_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
@@ -28603,7 +28596,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvl_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvl_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -28699,7 +28692,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_ilvod_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvod_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:48 ` no-reply
0 siblings, 0 replies; 18+ messages in thread
From: no-reply @ 2019-04-18 15:48 UTC (permalink / raw)
To: mateja.marjanovic
Cc: fam, qemu-devel, arikalo, richard.henderson, philmd, amarkovic, aurelien
Patchew URL: https://patchew.org/QEMU/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
The full log is available at
http://patchew.org/logs/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:48 ` no-reply
0 siblings, 0 replies; 18+ messages in thread
From: no-reply @ 2019-04-18 15:48 UTC (permalink / raw)
To: mateja.marjanovic
Cc: fam, arikalo, richard.henderson, qemu-devel, amarkovic, philmd, aurelien
Patchew URL: https://patchew.org/QEMU/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
The full log is available at
http://patchew.org/logs/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:57 ` no-reply
0 siblings, 0 replies; 18+ messages in thread
From: no-reply @ 2019-04-18 15:57 UTC (permalink / raw)
To: mateja.marjanovic
Cc: fam, qemu-devel, arikalo, richard.henderson, philmd, amarkovic, aurelien
Patchew URL: https://patchew.org/QEMU/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
remote: Counting objects: 4930, done.
error: RPC failed; result=18, HTTP code = 200
fatal: The remote end hung up unexpectedly
fatal: protocol error: bad pack header
Clone of 'https://git.qemu.org/git/dtc.git' into submodule path 'dtc' failed
failed to init submodule dtc
COPY RUNNER
The full log is available at
http://patchew.org/logs/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions
@ 2019-04-18 15:57 ` no-reply
0 siblings, 0 replies; 18+ messages in thread
From: no-reply @ 2019-04-18 15:57 UTC (permalink / raw)
To: mateja.marjanovic
Cc: fam, arikalo, richard.henderson, qemu-devel, amarkovic, philmd, aurelien
Patchew URL: https://patchew.org/QEMU/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
remote: Counting objects: 4930, done.
error: RPC failed; result=18, HTTP code = 200
fatal: The remote end hung up unexpectedly
fatal: protocol error: bad pack header
Clone of 'https://git.qemu.org/git/dtc.git' into submodule path 'dtc' failed
failed to init submodule dtc
COPY RUNNER
The full log is available at
http://patchew.org/logs/1555601350-4176-1-git-send-email-mateja.marjanovic@rt-rk.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-04-18 15:59 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-18 15:29 [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 2/6] target/mips: Optimize ILVEV.<B|H|W|D> " Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 3/6] target/mips: Optimize ILVL.<B|H|W|D> " Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 4/6] target/mips: Optimize ILVR.<B|H|W|D> " Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:29 ` [Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D Mateja Marjanovic
2019-04-18 15:29 ` Mateja Marjanovic
2019-04-18 15:48 ` [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions no-reply
2019-04-18 15:48 ` no-reply
2019-04-18 15:57 ` no-reply
2019-04-18 15:57 ` no-reply
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