* [Qemu-devel] [PATCH V1 0/3] Leon3 patches
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd, chouteau,
frederic.konrad
Hi all,
Those are some little fixes for the leon3 machine:
* The first part has already been submitted before and has been reworked
to follow Philippe's advice see:
<1519898536-19027-1-git-send-email-frederic.konrad@adacore.com>
"grlib_apbuart: always enable tx and rx"
* The second part adds AHB and APB plug and play devices to allow to boot
linux.
* The third part adds myself to the MAINTAINERS for this board.
The test images are available here: https://www.gaisler.com/anonftp/linux/lin
ux-2.6/images/leon-linux-4.9/leon-linux-4.9-1.0/up/
Tested with:
qemu-system-sparc -M leon3_generic --nographic --kernel image.ram
Regards,
Fred
KONRAD Frederic (3):
leon3: add a little bootloader
leon3: introduce the plug and play mecanism
MAINTAINERS: add myself for leon3
MAINTAINERS | 1 +
hw/misc/Makefile.objs | 2 +
hw/misc/grlib_ahb_apb_pnp.c | 269 ++++++++++++++++++++++++++++++++++++
hw/sparc/leon3.c | 110 +++++++++++++--
include/hw/misc/grlib_ahb_apb_pnp.h | 60 ++++++++
include/hw/sparc/grlib.h | 35 +++--
6 files changed, 451 insertions(+), 26 deletions(-)
create mode 100644 hw/misc/grlib_ahb_apb_pnp.c
create mode 100644 include/hw/misc/grlib_ahb_apb_pnp.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 0/3] Leon3 patches
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, frederic.konrad,
philmd, atar4qemu
Hi all,
Those are some little fixes for the leon3 machine:
* The first part has already been submitted before and has been reworked
to follow Philippe's advice see:
<1519898536-19027-1-git-send-email-frederic.konrad@adacore.com>
"grlib_apbuart: always enable tx and rx"
* The second part adds AHB and APB plug and play devices to allow to boot
linux.
* The third part adds myself to the MAINTAINERS for this board.
The test images are available here: https://www.gaisler.com/anonftp/linux/lin
ux-2.6/images/leon-linux-4.9/leon-linux-4.9-1.0/up/
Tested with:
qemu-system-sparc -M leon3_generic --nographic --kernel image.ram
Regards,
Fred
KONRAD Frederic (3):
leon3: add a little bootloader
leon3: introduce the plug and play mecanism
MAINTAINERS: add myself for leon3
MAINTAINERS | 1 +
hw/misc/Makefile.objs | 2 +
hw/misc/grlib_ahb_apb_pnp.c | 269 ++++++++++++++++++++++++++++++++++++
hw/sparc/leon3.c | 110 +++++++++++++--
include/hw/misc/grlib_ahb_apb_pnp.h | 60 ++++++++
include/hw/sparc/grlib.h | 35 +++--
6 files changed, 451 insertions(+), 26 deletions(-)
create mode 100644 hw/misc/grlib_ahb_apb_pnp.c
create mode 100644 include/hw/misc/grlib_ahb_apb_pnp.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd, chouteau,
frederic.konrad
This adds a little bootloader to the leon3_machine when a ram image is
given through the kernel parameter and no bios are provided:
* The UART transmiter is enabled.
* The TIMER is initialized.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 70 insertions(+), 10 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 774639a..2c6f486 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -1,7 +1,7 @@
/*
* QEMU Leon3 System Emulator
*
- * Copyright (c) 2010-2011 AdaCore
+ * Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,8 @@
#define CPU_CLK (40 * 1000 * 1000)
#define PROM_FILENAME "u-boot.bin"
+#define LEON3_PROM_OFFSET (0x00000000)
+#define LEON3_RAM_OFFSET (0x40000000)
#define MAX_PILS 16
@@ -53,6 +55,55 @@ typedef struct ResetData {
target_ulong sp; /* initial stack pointer */
} ResetData;
+static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
+{
+ stl_p(code++, 0x82100000); /* mov %g0, %g1 */
+ stl_p(code++, 0x84100000); /* mov %g0, %g2 */
+ stl_p(code++, 0x03000000 +
+ extract32(addr, 10, 22));
+ /* sethi %hi(addr), %g1 */
+ stl_p(code++, 0x82106000 +
+ extract32(addr, 0, 10));
+ /* or %g1, addr, %g1 */
+ stl_p(code++, 0x05000000 +
+ extract32(val, 10, 22));
+ /* sethi %hi(val), %g2 */
+ stl_p(code++, 0x8410a000 +
+ extract32(val, 0, 10));
+ /* or %g2, val, %g2 */
+ stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
+
+ return code;
+}
+
+/*
+ * When loading a kernel in RAM the machine is expected to be in a different
+ * state (eg: initialized by the bootloader). This little code reproduces
+ * this behavior.
+ */
+static void write_bootloader(CPUSPARCState *env, uint8_t *base,
+ hwaddr kernel_addr)
+{
+ uint32_t *p = (uint32_t *) base;
+
+ /* Initialize the UARTs */
+ p = gen_write_to_addr(p, 0x80000108, 3);
+
+ /* Initialize the TIMER 0 */
+ p = gen_write_to_addr(p, 0x80000304, 39);
+ p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
+ p = gen_write_to_addr(p, 0x80000318, 3);
+
+ /* JUMP to the entry point */
+ stl_p(p++, 0x82100000); /* mov %g0, %g1 */
+ stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
+ /* sethi %hi(kernel_addr), %g1 */
+ stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
+ /* or kernel_addr, %g1 */
+ stl_p(p++, 0x81c04000); /* jmp %g1 */
+ stl_p(p++, 0x01000000); /* nop */
+}
+
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
@@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Reset data */
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
- reset_info->sp = 0x40000000 + ram_size;
+ reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate IRQ manager */
- grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
+ grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
+ &leon3_set_pil_in);
env->qemu_irq_ack = leon3_irq_manager;
@@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
}
memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
- memory_region_add_subregion(address_space_mem, 0x40000000, ram);
+ memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
/* Allocate BIOS */
prom_size = 8 * MiB;
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_set_readonly(prom, true);
- memory_region_add_subregion(address_space_mem, 0x00000000, prom);
+ memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
if (bios_name == NULL) {
@@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
}
if (bios_size > 0) {
- ret = load_image_targphys(filename, 0x00000000, bios_size);
+ ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
if (ret < 0 || ret > prom_size) {
error_report("could not load prom '%s'", filename);
exit(1);
@@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
exit(1);
}
if (bios_size <= 0) {
- /* If there is no bios/monitor, start the application. */
- env->pc = entry;
- env->npc = entry + 4;
- reset_info->entry = entry;
+ /*
+ * If there is no bios/monitor just start the application but put
+ * the machine in an initialized state through a little
+ * bootloader.
+ */
+ uint8_t *bootloader_entry;
+
+ bootloader_entry = memory_region_get_ram_ptr(prom);
+ write_bootloader(env, bootloader_entry, entry);
+ env->pc = LEON3_PROM_OFFSET;
+ env->npc = LEON3_PROM_OFFSET + 4;
+ reset_info->entry = LEON3_PROM_OFFSET;
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, frederic.konrad,
philmd, atar4qemu
This adds a little bootloader to the leon3_machine when a ram image is
given through the kernel parameter and no bios are provided:
* The UART transmiter is enabled.
* The TIMER is initialized.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 70 insertions(+), 10 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 774639a..2c6f486 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -1,7 +1,7 @@
/*
* QEMU Leon3 System Emulator
*
- * Copyright (c) 2010-2011 AdaCore
+ * Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,8 @@
#define CPU_CLK (40 * 1000 * 1000)
#define PROM_FILENAME "u-boot.bin"
+#define LEON3_PROM_OFFSET (0x00000000)
+#define LEON3_RAM_OFFSET (0x40000000)
#define MAX_PILS 16
@@ -53,6 +55,55 @@ typedef struct ResetData {
target_ulong sp; /* initial stack pointer */
} ResetData;
+static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
+{
+ stl_p(code++, 0x82100000); /* mov %g0, %g1 */
+ stl_p(code++, 0x84100000); /* mov %g0, %g2 */
+ stl_p(code++, 0x03000000 +
+ extract32(addr, 10, 22));
+ /* sethi %hi(addr), %g1 */
+ stl_p(code++, 0x82106000 +
+ extract32(addr, 0, 10));
+ /* or %g1, addr, %g1 */
+ stl_p(code++, 0x05000000 +
+ extract32(val, 10, 22));
+ /* sethi %hi(val), %g2 */
+ stl_p(code++, 0x8410a000 +
+ extract32(val, 0, 10));
+ /* or %g2, val, %g2 */
+ stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
+
+ return code;
+}
+
+/*
+ * When loading a kernel in RAM the machine is expected to be in a different
+ * state (eg: initialized by the bootloader). This little code reproduces
+ * this behavior.
+ */
+static void write_bootloader(CPUSPARCState *env, uint8_t *base,
+ hwaddr kernel_addr)
+{
+ uint32_t *p = (uint32_t *) base;
+
+ /* Initialize the UARTs */
+ p = gen_write_to_addr(p, 0x80000108, 3);
+
+ /* Initialize the TIMER 0 */
+ p = gen_write_to_addr(p, 0x80000304, 39);
+ p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
+ p = gen_write_to_addr(p, 0x80000318, 3);
+
+ /* JUMP to the entry point */
+ stl_p(p++, 0x82100000); /* mov %g0, %g1 */
+ stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
+ /* sethi %hi(kernel_addr), %g1 */
+ stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
+ /* or kernel_addr, %g1 */
+ stl_p(p++, 0x81c04000); /* jmp %g1 */
+ stl_p(p++, 0x01000000); /* nop */
+}
+
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
@@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Reset data */
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
- reset_info->sp = 0x40000000 + ram_size;
+ reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate IRQ manager */
- grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
+ grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
+ &leon3_set_pil_in);
env->qemu_irq_ack = leon3_irq_manager;
@@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
}
memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
- memory_region_add_subregion(address_space_mem, 0x40000000, ram);
+ memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
/* Allocate BIOS */
prom_size = 8 * MiB;
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_set_readonly(prom, true);
- memory_region_add_subregion(address_space_mem, 0x00000000, prom);
+ memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
if (bios_name == NULL) {
@@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
}
if (bios_size > 0) {
- ret = load_image_targphys(filename, 0x00000000, bios_size);
+ ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
if (ret < 0 || ret > prom_size) {
error_report("could not load prom '%s'", filename);
exit(1);
@@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
exit(1);
}
if (bios_size <= 0) {
- /* If there is no bios/monitor, start the application. */
- env->pc = entry;
- env->npc = entry + 4;
- reset_info->entry = entry;
+ /*
+ * If there is no bios/monitor just start the application but put
+ * the machine in an initialized state through a little
+ * bootloader.
+ */
+ uint8_t *bootloader_entry;
+
+ bootloader_entry = memory_region_get_ram_ptr(prom);
+ write_bootloader(env, bootloader_entry, entry);
+ env->pc = LEON3_PROM_OFFSET;
+ env->npc = LEON3_PROM_OFFSET + 4;
+ reset_info->entry = LEON3_PROM_OFFSET;
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 2/3] leon3: introduce the plug and play mecanism
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd, chouteau,
frederic.konrad
This adds the AHB and APB plug and play devices.
They are scanned during the linux boot to discover the various peripheral.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
hw/misc/Makefile.objs | 2 +
hw/misc/grlib_ahb_apb_pnp.c | 269 ++++++++++++++++++++++++++++++++++++
hw/sparc/leon3.c | 34 ++++-
include/hw/misc/grlib_ahb_apb_pnp.h | 60 ++++++++
include/hw/sparc/grlib.h | 35 +++--
5 files changed, 382 insertions(+), 18 deletions(-)
create mode 100644 hw/misc/grlib_ahb_apb_pnp.c
create mode 100644 include/hw/misc/grlib_ahb_apb_pnp.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c71e07a..77b9df9 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -77,3 +77,5 @@ obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
obj-$(CONFIG_MSF2) += msf2-sysreg.o
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
+
+obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o
diff --git a/hw/misc/grlib_ahb_apb_pnp.c b/hw/misc/grlib_ahb_apb_pnp.c
new file mode 100644
index 0000000..90d5f6e
--- /dev/null
+++ b/hw/misc/grlib_ahb_apb_pnp.c
@@ -0,0 +1,269 @@
+/*
+ * GRLIB AHB APB PNP
+ *
+ * Copyright (C) 2019 AdaCore
+ *
+ * Developed by :
+ * Frederic Konrad <frederic.konrad@adacore.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/misc/grlib_ahb_apb_pnp.h"
+
+#define GRLIB_PNP_VENDOR_SHIFT (24)
+#define GRLIB_PNP_VENDOR_SIZE (8)
+#define GRLIB_PNP_DEV_SHIFT (12)
+#define GRLIB_PNP_DEV_SIZE (12)
+#define GRLIB_PNP_VER_SHIFT (5)
+#define GRLIB_PNP_VER_SIZE (5)
+#define GRLIB_PNP_IRQ_SHIFT (0)
+#define GRLIB_PNP_IRQ_SIZE (5)
+#define GRLIB_PNP_ADDR_SHIFT (20)
+#define GRLIB_PNP_ADDR_SIZE (12)
+#define GRLIB_PNP_MASK_SHIFT (4)
+#define GRLIB_PNP_MASK_SIZE (12)
+
+#define GRLIB_AHB_DEV_ADDR_SHIFT (20)
+#define GRLIB_AHB_DEV_ADDR_SIZE (12)
+#define GRLIB_AHB_ENTRY_SIZE (0x20)
+#define GRLIB_AHB_MAX_DEV (64)
+#define GRLIB_AHB_SLAVE_OFFSET (0x800)
+
+#define GRLIB_APB_DEV_ADDR_SHIFT (8)
+#define GRLIB_APB_DEV_ADDR_SIZE (12)
+#define GRLIB_APB_ENTRY_SIZE (0x08)
+#define GRLIB_APB_MAX_DEV (512)
+
+#define GRLIB_PNP_MAX_REGS (0x1000)
+
+typedef struct AHBPnp {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
+ uint8_t master_count;
+ uint8_t slave_count;
+} AHBPnp;
+
+void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, int slave,
+ int type)
+{
+ unsigned int reg_start;
+
+ /*
+ * AHB entries look like this:
+ *
+ * 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0
+ * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ */
+
+ if (slave) {
+ assert(dev->slave_count < GRLIB_AHB_MAX_DEV);
+ reg_start = (GRLIB_AHB_SLAVE_OFFSET
+ + (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2;
+ dev->slave_count++;
+ } else {
+ assert(dev->master_count < GRLIB_AHB_MAX_DEV);
+ reg_start = (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2;
+ dev->master_count++;
+ }
+
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VENDOR_SHIFT,
+ GRLIB_PNP_VENDOR_SIZE,
+ vendor);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_DEV_SHIFT,
+ GRLIB_PNP_DEV_SIZE,
+ device);
+ reg_start += 4;
+ /* AHB Memory Space */
+ dev->regs[reg_start] = type;
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_ADDR_SHIFT,
+ GRLIB_PNP_ADDR_SIZE,
+ extract32(address,
+ GRLIB_AHB_DEV_ADDR_SHIFT,
+ GRLIB_AHB_DEV_ADDR_SIZE));
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_MASK_SHIFT,
+ GRLIB_PNP_MASK_SIZE,
+ mask);
+}
+
+static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
+
+ return ahb_pnp->regs[offset >> 2];
+}
+
+static const MemoryRegionOps grlib_ahb_pnp_ops = {
+ .read = grlib_ahb_pnp_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
+{
+ AHBPnp *ahb_pnp = GRLIB_AHB_PNP(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops,
+ ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS);
+ sysbus_init_mmio(sbd, &ahb_pnp->iomem);
+}
+
+static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = grlib_ahb_pnp_realize;
+}
+
+static const TypeInfo grlib_ahb_pnp_info = {
+ .name = TYPE_GRLIB_AHB_PNP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AHBPnp),
+ .class_init = grlib_ahb_pnp_class_init,
+};
+
+/* APBPnp */
+
+typedef struct APBPnp {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
+ uint32_t entry_count;
+} APBPnp;
+
+void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, uint8_t version,
+ uint8_t irq, int type)
+{
+ unsigned int reg_start;
+
+ /*
+ * APB entries look like this:
+ *
+ * 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0
+ * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
+ *
+ * 31 ---------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[20..8] | 0000 | MASK | TYPE |
+ */
+
+ assert(dev->entry_count < GRLIB_APB_MAX_DEV);
+ reg_start = (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2;
+ dev->entry_count++;
+
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VENDOR_SHIFT,
+ GRLIB_PNP_VENDOR_SIZE,
+ vendor);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_DEV_SHIFT,
+ GRLIB_PNP_DEV_SIZE,
+ device);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VER_SHIFT,
+ GRLIB_PNP_VER_SIZE,
+ version);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_IRQ_SHIFT,
+ GRLIB_PNP_IRQ_SIZE,
+ irq);
+ reg_start += 1;
+ dev->regs[reg_start] = type;
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_ADDR_SHIFT,
+ GRLIB_PNP_ADDR_SIZE,
+ extract32(address,
+ GRLIB_APB_DEV_ADDR_SHIFT,
+ GRLIB_APB_DEV_ADDR_SIZE));
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_MASK_SHIFT,
+ GRLIB_PNP_MASK_SIZE,
+ mask);
+}
+
+static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
+
+ return apb_pnp->regs[offset >> 2];
+}
+
+static const MemoryRegionOps grlib_apb_pnp_ops = {
+ .read = grlib_apb_pnp_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp)
+{
+ APBPnp *apb_pnp = GRLIB_APB_PNP(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops,
+ apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS);
+ sysbus_init_mmio(sbd, &apb_pnp->iomem);
+}
+
+static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = grlib_apb_pnp_realize;
+}
+
+static const TypeInfo grlib_apb_pnp_info = {
+ .name = TYPE_GRLIB_APB_PNP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(APBPnp),
+ .class_init = grlib_apb_pnp_class_init,
+};
+
+static void grlib_ahb_apb_pnp_register_types(void)
+{
+ type_register_static(&grlib_ahb_pnp_info);
+ type_register_static(&grlib_apb_pnp_info);
+}
+
+type_init(grlib_ahb_apb_pnp_register_types)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 2c6f486..74364a1 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -46,6 +46,13 @@
#define PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
+#define LEON3_APBUART_OFFSET (0x80000100)
+#define LEON3_APBUART_IRQ (0x3)
+#define LEON3_IRQMP_OFFSET (0x80000200)
+#define LEON3_GPTIMER_OFFSET (0x80000300)
+#define LEON3_GPTIMER_IRQ (0x6)
+#define LEON3_APB_PNP_OFFSET (0x800FF000)
+#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
#define MAX_PILS 16
@@ -172,6 +179,8 @@ static void leon3_generic_hw_init(MachineState *machine)
int bios_size;
int prom_size;
ResetData *reset_info;
+ AHBPnp *ahb_pnp;
+ APBPnp *apb_pnp;
/* Init CPU */
cpu = SPARC_CPU(cpu_create(machine->cpu_type));
@@ -185,9 +194,23 @@ static void leon3_generic_hw_init(MachineState *machine)
reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
+ ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
+ object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
+ grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
+ GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
+ GRLIB_CPU_AREA);
+
+ apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
+ object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
+ grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
+ GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
+ GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
+
/* Allocate IRQ manager */
- grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
- &leon3_set_pil_in);
+ grlib_irqmp_create(LEON3_IRQMP_OFFSET, env, &cpu_irqs, MAX_PILS,
+ &leon3_set_pil_in, apb_pnp);
env->qemu_irq_ack = leon3_irq_manager;
@@ -266,11 +289,14 @@ static void leon3_generic_hw_init(MachineState *machine)
}
/* Allocate timers */
- grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6);
+ grlib_gptimer_create(LEON3_GPTIMER_OFFSET, 2, CPU_CLK, cpu_irqs,
+ LEON3_GPTIMER_IRQ,
+ apb_pnp);
/* Allocate uart */
if (serial_hd(0)) {
- grlib_apbuart_create(0x80000100, serial_hd(0), cpu_irqs[3]);
+ grlib_apbuart_create(LEON3_APBUART_OFFSET, serial_hd(0), cpu_irqs,
+ LEON3_APBUART_IRQ, apb_pnp);
}
}
diff --git a/include/hw/misc/grlib_ahb_apb_pnp.h b/include/hw/misc/grlib_ahb_apb_pnp.h
new file mode 100644
index 0000000..a0f6dcf
--- /dev/null
+++ b/include/hw/misc/grlib_ahb_apb_pnp.h
@@ -0,0 +1,60 @@
+/*
+ * GRLIB AHB APB PNP
+ *
+ * Copyright (C) 2019 AdaCore
+ *
+ * Developed by :
+ * Frederic Konrad <frederic.konrad@adacore.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef GRLIB_AHB_APB_PNP_H
+#define GRLIB_AHB_APB_PNP_H
+
+#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
+#define GRLIB_AHB_PNP(obj) \
+ OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP)
+typedef struct AHBPnp AHBPnp;
+
+#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
+#define GRLIB_APB_PNP(obj) \
+ OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP)
+typedef struct APBPnp APBPnp;
+
+void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, int slave,
+ int type);
+void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, uint8_t version,
+ uint8_t irq, int type);
+
+/* VENDORS */
+#define GRLIB_VENDOR_GAISLER (0x01)
+/* DEVICES */
+#define GRLIB_LEON3_DEV (0x03)
+#define GRLIB_APBMST_DEV (0x06)
+#define GRLIB_APBUART_DEV (0x0C)
+#define GRLIB_IRQMP_DEV (0x0D)
+#define GRLIB_GPTIMER_DEV (0x11)
+/* TYPE */
+#define GRLIB_CPU_AREA (0x00)
+#define GRLIB_APBIO_AREA (0x01)
+#define GRLIB_AHBMEM_AREA (0x02)
+
+#define GRLIB_AHB_MASTER (0x00)
+#define GRLIB_AHB_SLAVE (0x01)
+
+#endif /* GRLIB_AHB_APB_PNP_H */
diff --git a/include/hw/sparc/grlib.h b/include/hw/sparc/grlib.h
index 61a345c..28320ab 100644
--- a/include/hw/sparc/grlib.h
+++ b/include/hw/sparc/grlib.h
@@ -27,6 +27,7 @@
#include "hw/qdev.h"
#include "hw/sysbus.h"
+#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
* http://www.gaisler.com/products/grlib/grip.pdf
@@ -41,11 +42,9 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
-DeviceState *grlib_irqmp_create(hwaddr base,
- CPUSPARCState *env,
- qemu_irq **cpu_irqs,
- uint32_t nr_irqs,
- set_pil_in_fn set_pil_in)
+DeviceState *grlib_irqmp_create(hwaddr base, CPUSPARCState *env,
+ qemu_irq **cpu_irqs, uint32_t nr_irqs,
+ set_pil_in_fn set_pil_in, APBPnp *apb_pnp)
{
DeviceState *dev;
@@ -65,17 +64,18 @@ DeviceState *grlib_irqmp_create(hwaddr base,
dev,
nr_irqs);
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA);
return dev;
}
/* GPTimer */
static inline
-DeviceState *grlib_gptimer_create(hwaddr base,
- uint32_t nr_timers,
- uint32_t freq,
- qemu_irq *cpu_irqs,
- int base_irq)
+DeviceState *grlib_gptimer_create(hwaddr base, uint32_t nr_timers,
+ uint32_t freq, qemu_irq *cpu_irqs,
+ int base_irq, APBPnp *apb_pnp)
{
DeviceState *dev;
int i;
@@ -93,15 +93,18 @@ DeviceState *grlib_gptimer_create(hwaddr base,
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
}
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_GPTIMER_DEV, 0, base_irq, GRLIB_APBIO_AREA);
return dev;
}
/* APB UART */
static inline
-DeviceState *grlib_apbuart_create(hwaddr base,
- Chardev *serial,
- qemu_irq irq)
+DeviceState *grlib_apbuart_create(hwaddr base, Chardev *serial,
+ qemu_irq *cpu_irqs, int base_irq,
+ APBPnp *apb_pnp)
{
DeviceState *dev;
@@ -112,7 +115,11 @@ DeviceState *grlib_apbuart_create(hwaddr base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[base_irq]);
+
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_APBUART_DEV, 1, base_irq, GRLIB_APBIO_AREA);
return dev;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 2/3] leon3: introduce the plug and play mecanism
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, frederic.konrad,
philmd, atar4qemu
This adds the AHB and APB plug and play devices.
They are scanned during the linux boot to discover the various peripheral.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
hw/misc/Makefile.objs | 2 +
hw/misc/grlib_ahb_apb_pnp.c | 269 ++++++++++++++++++++++++++++++++++++
hw/sparc/leon3.c | 34 ++++-
include/hw/misc/grlib_ahb_apb_pnp.h | 60 ++++++++
include/hw/sparc/grlib.h | 35 +++--
5 files changed, 382 insertions(+), 18 deletions(-)
create mode 100644 hw/misc/grlib_ahb_apb_pnp.c
create mode 100644 include/hw/misc/grlib_ahb_apb_pnp.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c71e07a..77b9df9 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -77,3 +77,5 @@ obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
obj-$(CONFIG_MSF2) += msf2-sysreg.o
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
+
+obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o
diff --git a/hw/misc/grlib_ahb_apb_pnp.c b/hw/misc/grlib_ahb_apb_pnp.c
new file mode 100644
index 0000000..90d5f6e
--- /dev/null
+++ b/hw/misc/grlib_ahb_apb_pnp.c
@@ -0,0 +1,269 @@
+/*
+ * GRLIB AHB APB PNP
+ *
+ * Copyright (C) 2019 AdaCore
+ *
+ * Developed by :
+ * Frederic Konrad <frederic.konrad@adacore.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/misc/grlib_ahb_apb_pnp.h"
+
+#define GRLIB_PNP_VENDOR_SHIFT (24)
+#define GRLIB_PNP_VENDOR_SIZE (8)
+#define GRLIB_PNP_DEV_SHIFT (12)
+#define GRLIB_PNP_DEV_SIZE (12)
+#define GRLIB_PNP_VER_SHIFT (5)
+#define GRLIB_PNP_VER_SIZE (5)
+#define GRLIB_PNP_IRQ_SHIFT (0)
+#define GRLIB_PNP_IRQ_SIZE (5)
+#define GRLIB_PNP_ADDR_SHIFT (20)
+#define GRLIB_PNP_ADDR_SIZE (12)
+#define GRLIB_PNP_MASK_SHIFT (4)
+#define GRLIB_PNP_MASK_SIZE (12)
+
+#define GRLIB_AHB_DEV_ADDR_SHIFT (20)
+#define GRLIB_AHB_DEV_ADDR_SIZE (12)
+#define GRLIB_AHB_ENTRY_SIZE (0x20)
+#define GRLIB_AHB_MAX_DEV (64)
+#define GRLIB_AHB_SLAVE_OFFSET (0x800)
+
+#define GRLIB_APB_DEV_ADDR_SHIFT (8)
+#define GRLIB_APB_DEV_ADDR_SIZE (12)
+#define GRLIB_APB_ENTRY_SIZE (0x08)
+#define GRLIB_APB_MAX_DEV (512)
+
+#define GRLIB_PNP_MAX_REGS (0x1000)
+
+typedef struct AHBPnp {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
+ uint8_t master_count;
+ uint8_t slave_count;
+} AHBPnp;
+
+void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, int slave,
+ int type)
+{
+ unsigned int reg_start;
+
+ /*
+ * AHB entries look like this:
+ *
+ * 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0
+ * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * | USER |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ * 31 ----------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[31..12] | 00PC | MASK | TYPE |
+ * --------------------------------------------------
+ */
+
+ if (slave) {
+ assert(dev->slave_count < GRLIB_AHB_MAX_DEV);
+ reg_start = (GRLIB_AHB_SLAVE_OFFSET
+ + (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2;
+ dev->slave_count++;
+ } else {
+ assert(dev->master_count < GRLIB_AHB_MAX_DEV);
+ reg_start = (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2;
+ dev->master_count++;
+ }
+
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VENDOR_SHIFT,
+ GRLIB_PNP_VENDOR_SIZE,
+ vendor);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_DEV_SHIFT,
+ GRLIB_PNP_DEV_SIZE,
+ device);
+ reg_start += 4;
+ /* AHB Memory Space */
+ dev->regs[reg_start] = type;
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_ADDR_SHIFT,
+ GRLIB_PNP_ADDR_SIZE,
+ extract32(address,
+ GRLIB_AHB_DEV_ADDR_SHIFT,
+ GRLIB_AHB_DEV_ADDR_SIZE));
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_MASK_SHIFT,
+ GRLIB_PNP_MASK_SIZE,
+ mask);
+}
+
+static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
+
+ return ahb_pnp->regs[offset >> 2];
+}
+
+static const MemoryRegionOps grlib_ahb_pnp_ops = {
+ .read = grlib_ahb_pnp_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
+{
+ AHBPnp *ahb_pnp = GRLIB_AHB_PNP(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops,
+ ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS);
+ sysbus_init_mmio(sbd, &ahb_pnp->iomem);
+}
+
+static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = grlib_ahb_pnp_realize;
+}
+
+static const TypeInfo grlib_ahb_pnp_info = {
+ .name = TYPE_GRLIB_AHB_PNP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AHBPnp),
+ .class_init = grlib_ahb_pnp_class_init,
+};
+
+/* APBPnp */
+
+typedef struct APBPnp {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
+ uint32_t entry_count;
+} APBPnp;
+
+void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, uint8_t version,
+ uint8_t irq, int type)
+{
+ unsigned int reg_start;
+
+ /*
+ * APB entries look like this:
+ *
+ * 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0
+ * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
+ *
+ * 31 ---------- 20 --- 15 ----------------- 3 ---- 0
+ * | ADDR[20..8] | 0000 | MASK | TYPE |
+ */
+
+ assert(dev->entry_count < GRLIB_APB_MAX_DEV);
+ reg_start = (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2;
+ dev->entry_count++;
+
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VENDOR_SHIFT,
+ GRLIB_PNP_VENDOR_SIZE,
+ vendor);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_DEV_SHIFT,
+ GRLIB_PNP_DEV_SIZE,
+ device);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_VER_SHIFT,
+ GRLIB_PNP_VER_SIZE,
+ version);
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_IRQ_SHIFT,
+ GRLIB_PNP_IRQ_SIZE,
+ irq);
+ reg_start += 1;
+ dev->regs[reg_start] = type;
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_ADDR_SHIFT,
+ GRLIB_PNP_ADDR_SIZE,
+ extract32(address,
+ GRLIB_APB_DEV_ADDR_SHIFT,
+ GRLIB_APB_DEV_ADDR_SIZE));
+ dev->regs[reg_start] = deposit32(dev->regs[reg_start],
+ GRLIB_PNP_MASK_SHIFT,
+ GRLIB_PNP_MASK_SIZE,
+ mask);
+}
+
+static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
+
+ return apb_pnp->regs[offset >> 2];
+}
+
+static const MemoryRegionOps grlib_apb_pnp_ops = {
+ .read = grlib_apb_pnp_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp)
+{
+ APBPnp *apb_pnp = GRLIB_APB_PNP(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops,
+ apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS);
+ sysbus_init_mmio(sbd, &apb_pnp->iomem);
+}
+
+static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = grlib_apb_pnp_realize;
+}
+
+static const TypeInfo grlib_apb_pnp_info = {
+ .name = TYPE_GRLIB_APB_PNP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(APBPnp),
+ .class_init = grlib_apb_pnp_class_init,
+};
+
+static void grlib_ahb_apb_pnp_register_types(void)
+{
+ type_register_static(&grlib_ahb_pnp_info);
+ type_register_static(&grlib_apb_pnp_info);
+}
+
+type_init(grlib_ahb_apb_pnp_register_types)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 2c6f486..74364a1 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -46,6 +46,13 @@
#define PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
+#define LEON3_APBUART_OFFSET (0x80000100)
+#define LEON3_APBUART_IRQ (0x3)
+#define LEON3_IRQMP_OFFSET (0x80000200)
+#define LEON3_GPTIMER_OFFSET (0x80000300)
+#define LEON3_GPTIMER_IRQ (0x6)
+#define LEON3_APB_PNP_OFFSET (0x800FF000)
+#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
#define MAX_PILS 16
@@ -172,6 +179,8 @@ static void leon3_generic_hw_init(MachineState *machine)
int bios_size;
int prom_size;
ResetData *reset_info;
+ AHBPnp *ahb_pnp;
+ APBPnp *apb_pnp;
/* Init CPU */
cpu = SPARC_CPU(cpu_create(machine->cpu_type));
@@ -185,9 +194,23 @@ static void leon3_generic_hw_init(MachineState *machine)
reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
+ ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
+ object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
+ grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
+ GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
+ GRLIB_CPU_AREA);
+
+ apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
+ object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
+ grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
+ GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
+ GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
+
/* Allocate IRQ manager */
- grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
- &leon3_set_pil_in);
+ grlib_irqmp_create(LEON3_IRQMP_OFFSET, env, &cpu_irqs, MAX_PILS,
+ &leon3_set_pil_in, apb_pnp);
env->qemu_irq_ack = leon3_irq_manager;
@@ -266,11 +289,14 @@ static void leon3_generic_hw_init(MachineState *machine)
}
/* Allocate timers */
- grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6);
+ grlib_gptimer_create(LEON3_GPTIMER_OFFSET, 2, CPU_CLK, cpu_irqs,
+ LEON3_GPTIMER_IRQ,
+ apb_pnp);
/* Allocate uart */
if (serial_hd(0)) {
- grlib_apbuart_create(0x80000100, serial_hd(0), cpu_irqs[3]);
+ grlib_apbuart_create(LEON3_APBUART_OFFSET, serial_hd(0), cpu_irqs,
+ LEON3_APBUART_IRQ, apb_pnp);
}
}
diff --git a/include/hw/misc/grlib_ahb_apb_pnp.h b/include/hw/misc/grlib_ahb_apb_pnp.h
new file mode 100644
index 0000000..a0f6dcf
--- /dev/null
+++ b/include/hw/misc/grlib_ahb_apb_pnp.h
@@ -0,0 +1,60 @@
+/*
+ * GRLIB AHB APB PNP
+ *
+ * Copyright (C) 2019 AdaCore
+ *
+ * Developed by :
+ * Frederic Konrad <frederic.konrad@adacore.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef GRLIB_AHB_APB_PNP_H
+#define GRLIB_AHB_APB_PNP_H
+
+#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
+#define GRLIB_AHB_PNP(obj) \
+ OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP)
+typedef struct AHBPnp AHBPnp;
+
+#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
+#define GRLIB_APB_PNP(obj) \
+ OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP)
+typedef struct APBPnp APBPnp;
+
+void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, int slave,
+ int type);
+void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
+ uint8_t vendor, uint16_t device, uint8_t version,
+ uint8_t irq, int type);
+
+/* VENDORS */
+#define GRLIB_VENDOR_GAISLER (0x01)
+/* DEVICES */
+#define GRLIB_LEON3_DEV (0x03)
+#define GRLIB_APBMST_DEV (0x06)
+#define GRLIB_APBUART_DEV (0x0C)
+#define GRLIB_IRQMP_DEV (0x0D)
+#define GRLIB_GPTIMER_DEV (0x11)
+/* TYPE */
+#define GRLIB_CPU_AREA (0x00)
+#define GRLIB_APBIO_AREA (0x01)
+#define GRLIB_AHBMEM_AREA (0x02)
+
+#define GRLIB_AHB_MASTER (0x00)
+#define GRLIB_AHB_SLAVE (0x01)
+
+#endif /* GRLIB_AHB_APB_PNP_H */
diff --git a/include/hw/sparc/grlib.h b/include/hw/sparc/grlib.h
index 61a345c..28320ab 100644
--- a/include/hw/sparc/grlib.h
+++ b/include/hw/sparc/grlib.h
@@ -27,6 +27,7 @@
#include "hw/qdev.h"
#include "hw/sysbus.h"
+#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
* http://www.gaisler.com/products/grlib/grip.pdf
@@ -41,11 +42,9 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
-DeviceState *grlib_irqmp_create(hwaddr base,
- CPUSPARCState *env,
- qemu_irq **cpu_irqs,
- uint32_t nr_irqs,
- set_pil_in_fn set_pil_in)
+DeviceState *grlib_irqmp_create(hwaddr base, CPUSPARCState *env,
+ qemu_irq **cpu_irqs, uint32_t nr_irqs,
+ set_pil_in_fn set_pil_in, APBPnp *apb_pnp)
{
DeviceState *dev;
@@ -65,17 +64,18 @@ DeviceState *grlib_irqmp_create(hwaddr base,
dev,
nr_irqs);
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA);
return dev;
}
/* GPTimer */
static inline
-DeviceState *grlib_gptimer_create(hwaddr base,
- uint32_t nr_timers,
- uint32_t freq,
- qemu_irq *cpu_irqs,
- int base_irq)
+DeviceState *grlib_gptimer_create(hwaddr base, uint32_t nr_timers,
+ uint32_t freq, qemu_irq *cpu_irqs,
+ int base_irq, APBPnp *apb_pnp)
{
DeviceState *dev;
int i;
@@ -93,15 +93,18 @@ DeviceState *grlib_gptimer_create(hwaddr base,
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
}
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_GPTIMER_DEV, 0, base_irq, GRLIB_APBIO_AREA);
return dev;
}
/* APB UART */
static inline
-DeviceState *grlib_apbuart_create(hwaddr base,
- Chardev *serial,
- qemu_irq irq)
+DeviceState *grlib_apbuart_create(hwaddr base, Chardev *serial,
+ qemu_irq *cpu_irqs, int base_irq,
+ APBPnp *apb_pnp)
{
DeviceState *dev;
@@ -112,7 +115,11 @@ DeviceState *grlib_apbuart_create(hwaddr base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[base_irq]);
+
+ /* Register this device in the APB PNP device */
+ grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER,
+ GRLIB_APBUART_DEV, 1, base_irq, GRLIB_APBIO_AREA);
return dev;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd, chouteau,
frederic.konrad
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 56139ac..3543035 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1151,6 +1151,7 @@ F: include/hw/timer/sun4v-rtc.h
Leon3
M: Fabien Chouteau <chouteau@adacore.com>
+M: KONRAD Frederic <frederic.konrad@adacore.com>
S: Maintained
F: hw/sparc/leon3.c
F: hw/*/grlib*
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-19 10:18 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-19 10:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, frederic.konrad,
philmd, atar4qemu
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 56139ac..3543035 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1151,6 +1151,7 @@ F: include/hw/timer/sun4v-rtc.h
Leon3
M: Fabien Chouteau <chouteau@adacore.com>
+M: KONRAD Frederic <frederic.konrad@adacore.com>
S: Maintained
F: hw/sparc/leon3.c
F: hw/*/grlib*
--
1.8.3.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 10:58 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:58 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, philmd, atar4qemu
On 19/04/2019 12:18, KONRAD Frederic wrote:
> This adds a little bootloader to the leon3_machine when a ram image is
> given through the kernel parameter and no bios are provided:
> * The UART transmiter is enabled.
> * The TIMER is initialized.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 10:58 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:58 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd
On 19/04/2019 12:18, KONRAD Frederic wrote:
> This adds a little bootloader to the leon3_machine when a ram image is
> given through the kernel parameter and no bios are provided:
> * The UART transmiter is enabled.
> * The TIMER is initialized.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 2/3] leon3: introduce the plug and play mecanism
@ 2019-04-23 10:59 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:59 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, philmd, atar4qemu
On 19/04/2019 12:18, KONRAD Frederic wrote:
> This adds the AHB and APB plug and play devices.
> They are scanned during the linux boot to discover the various peripheral.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 2/3] leon3: introduce the plug and play mecanism
@ 2019-04-23 10:59 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:59 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd
On 19/04/2019 12:18, KONRAD Frederic wrote:
> This adds the AHB and APB plug and play devices.
> They are scanned during the linux boot to discover the various peripheral.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-23 10:59 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:59 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, philmd, atar4qemu
On 19/04/2019 12:18, KONRAD Frederic wrote:
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-23 10:59 ` Fabien Chouteau
0 siblings, 0 replies; 20+ messages in thread
From: Fabien Chouteau @ 2019-04-23 10:59 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, philmd
On 19/04/2019 12:18, KONRAD Frederic wrote:
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-23 14:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-04-23 14:03 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, chouteau
On 4/19/19 12:18 PM, KONRAD Frederic wrote:
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 56139ac..3543035 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1151,6 +1151,7 @@ F: include/hw/timer/sun4v-rtc.h
>
> Leon3
> M: Fabien Chouteau <chouteau@adacore.com>
> +M: KONRAD Frederic <frederic.konrad@adacore.com>
> S: Maintained
> F: hw/sparc/leon3.c
> F: hw/*/grlib*
>
Thank you for stepping in!
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3
@ 2019-04-23 14:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-04-23 14:03 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, atar4qemu
On 4/19/19 12:18 PM, KONRAD Frederic wrote:
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 56139ac..3543035 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1151,6 +1151,7 @@ F: include/hw/timer/sun4v-rtc.h
>
> Leon3
> M: Fabien Chouteau <chouteau@adacore.com>
> +M: KONRAD Frederic <frederic.konrad@adacore.com>
> S: Maintained
> F: hw/sparc/leon3.c
> F: hw/*/grlib*
>
Thank you for stepping in!
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 14:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-04-23 14:20 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, chouteau
Hi Frederic,
On 4/19/19 12:18 PM, KONRAD Frederic wrote:
> This adds a little bootloader to the leon3_machine when a ram image is
> given through the kernel parameter and no bios are provided:
> * The UART transmiter is enabled.
> * The TIMER is initialized.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 70 insertions(+), 10 deletions(-)
>
> diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
> index 774639a..2c6f486 100644
> --- a/hw/sparc/leon3.c
> +++ b/hw/sparc/leon3.c
> @@ -1,7 +1,7 @@
> /*
> * QEMU Leon3 System Emulator
> *
> - * Copyright (c) 2010-2011 AdaCore
> + * Copyright (c) 2010-2019 AdaCore
> *
> * Permission is hereby granted, free of charge, to any person obtaining a copy
> * of this software and associated documentation files (the "Software"), to deal
> @@ -44,6 +44,8 @@
> #define CPU_CLK (40 * 1000 * 1000)
>
> #define PROM_FILENAME "u-boot.bin"
> +#define LEON3_PROM_OFFSET (0x00000000)
> +#define LEON3_RAM_OFFSET (0x40000000)
I'd have split this patch in 2, first add/use these definitions, then
the bootloader code, but that's OK.
>
> #define MAX_PILS 16
>
> @@ -53,6 +55,55 @@ typedef struct ResetData {
> target_ulong sp; /* initial stack pointer */
> } ResetData;
>
> +static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
Can you rename that gen_store_u32()?
If you prefer gen_write_to_addr() that's fine.
> +{
> + stl_p(code++, 0x82100000); /* mov %g0, %g1 */
> + stl_p(code++, 0x84100000); /* mov %g0, %g2 */
> + stl_p(code++, 0x03000000 +
> + extract32(addr, 10, 22));
> + /* sethi %hi(addr), %g1 */
> + stl_p(code++, 0x82106000 +
> + extract32(addr, 0, 10));
> + /* or %g1, addr, %g1 */
> + stl_p(code++, 0x05000000 +
> + extract32(val, 10, 22));
> + /* sethi %hi(val), %g2 */
> + stl_p(code++, 0x8410a000 +
> + extract32(val, 0, 10));
> + /* or %g2, val, %g2 */
> + stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
> +
> + return code;
> +}
> +
> +/*
> + * When loading a kernel in RAM the machine is expected to be in a different
> + * state (eg: initialized by the bootloader). This little code reproduces
> + * this behavior.
> + */
> +static void write_bootloader(CPUSPARCState *env, uint8_t *base,
> + hwaddr kernel_addr)
> +{
> + uint32_t *p = (uint32_t *) base;
> +
> + /* Initialize the UARTs */
> + p = gen_write_to_addr(p, 0x80000108, 3);
Can you add comments?
Here are the notes I took while reviewing, they might be enough:
// *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE;
> +
> + /* Initialize the TIMER 0 */
> + p = gen_write_to_addr(p, 0x80000304, 39);
// *GPTIMER_SCALER_RELOAD = 40 - 1;
> + p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
// *GPTIMER0_COUNTER_RELOAD = 0xFFFE;
> + p = gen_write_to_addr(p, 0x80000318, 3);
// *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;
> +
> + /* JUMP to the entry point */
> + stl_p(p++, 0x82100000); /* mov %g0, %g1 */
> + stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
> + /* sethi %hi(kernel_addr), %g1 */
> + stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
> + /* or kernel_addr, %g1 */
> + stl_p(p++, 0x81c04000); /* jmp %g1 */
> + stl_p(p++, 0x01000000); /* nop */
> +}
Thanks for adding write_bootloader(), I really appreciate your effort.
With the comments:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> +
> static void main_cpu_reset(void *opaque)
> {
> ResetData *s = (ResetData *)opaque;
> @@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
> /* Reset data */
> reset_info = g_malloc0(sizeof(ResetData));
> reset_info->cpu = cpu;
> - reset_info->sp = 0x40000000 + ram_size;
> + reset_info->sp = LEON3_RAM_OFFSET + ram_size;
> qemu_register_reset(main_cpu_reset, reset_info);
>
> /* Allocate IRQ manager */
> - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
> + grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
> + &leon3_set_pil_in);
>
> env->qemu_irq_ack = leon3_irq_manager;
>
> @@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
> }
>
> memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
> - memory_region_add_subregion(address_space_mem, 0x40000000, ram);
> + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
>
> /* Allocate BIOS */
> prom_size = 8 * MiB;
> memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
> memory_region_set_readonly(prom, true);
> - memory_region_add_subregion(address_space_mem, 0x00000000, prom);
> + memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
>
> /* Load boot prom */
> if (bios_name == NULL) {
> @@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
> }
>
> if (bios_size > 0) {
> - ret = load_image_targphys(filename, 0x00000000, bios_size);
> + ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
> if (ret < 0 || ret > prom_size) {
> error_report("could not load prom '%s'", filename);
> exit(1);
> @@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
> exit(1);
> }
> if (bios_size <= 0) {
> - /* If there is no bios/monitor, start the application. */
> - env->pc = entry;
> - env->npc = entry + 4;
> - reset_info->entry = entry;
> + /*
> + * If there is no bios/monitor just start the application but put
> + * the machine in an initialized state through a little
> + * bootloader.
> + */
> + uint8_t *bootloader_entry;
> +
> + bootloader_entry = memory_region_get_ram_ptr(prom);
> + write_bootloader(env, bootloader_entry, entry);
> + env->pc = LEON3_PROM_OFFSET;
> + env->npc = LEON3_PROM_OFFSET + 4;
> + reset_info->entry = LEON3_PROM_OFFSET;
> }
> }
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 14:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-04-23 14:20 UTC (permalink / raw)
To: KONRAD Frederic, qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, atar4qemu
Hi Frederic,
On 4/19/19 12:18 PM, KONRAD Frederic wrote:
> This adds a little bootloader to the leon3_machine when a ram image is
> given through the kernel parameter and no bios are provided:
> * The UART transmiter is enabled.
> * The TIMER is initialized.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 70 insertions(+), 10 deletions(-)
>
> diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
> index 774639a..2c6f486 100644
> --- a/hw/sparc/leon3.c
> +++ b/hw/sparc/leon3.c
> @@ -1,7 +1,7 @@
> /*
> * QEMU Leon3 System Emulator
> *
> - * Copyright (c) 2010-2011 AdaCore
> + * Copyright (c) 2010-2019 AdaCore
> *
> * Permission is hereby granted, free of charge, to any person obtaining a copy
> * of this software and associated documentation files (the "Software"), to deal
> @@ -44,6 +44,8 @@
> #define CPU_CLK (40 * 1000 * 1000)
>
> #define PROM_FILENAME "u-boot.bin"
> +#define LEON3_PROM_OFFSET (0x00000000)
> +#define LEON3_RAM_OFFSET (0x40000000)
I'd have split this patch in 2, first add/use these definitions, then
the bootloader code, but that's OK.
>
> #define MAX_PILS 16
>
> @@ -53,6 +55,55 @@ typedef struct ResetData {
> target_ulong sp; /* initial stack pointer */
> } ResetData;
>
> +static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
Can you rename that gen_store_u32()?
If you prefer gen_write_to_addr() that's fine.
> +{
> + stl_p(code++, 0x82100000); /* mov %g0, %g1 */
> + stl_p(code++, 0x84100000); /* mov %g0, %g2 */
> + stl_p(code++, 0x03000000 +
> + extract32(addr, 10, 22));
> + /* sethi %hi(addr), %g1 */
> + stl_p(code++, 0x82106000 +
> + extract32(addr, 0, 10));
> + /* or %g1, addr, %g1 */
> + stl_p(code++, 0x05000000 +
> + extract32(val, 10, 22));
> + /* sethi %hi(val), %g2 */
> + stl_p(code++, 0x8410a000 +
> + extract32(val, 0, 10));
> + /* or %g2, val, %g2 */
> + stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
> +
> + return code;
> +}
> +
> +/*
> + * When loading a kernel in RAM the machine is expected to be in a different
> + * state (eg: initialized by the bootloader). This little code reproduces
> + * this behavior.
> + */
> +static void write_bootloader(CPUSPARCState *env, uint8_t *base,
> + hwaddr kernel_addr)
> +{
> + uint32_t *p = (uint32_t *) base;
> +
> + /* Initialize the UARTs */
> + p = gen_write_to_addr(p, 0x80000108, 3);
Can you add comments?
Here are the notes I took while reviewing, they might be enough:
// *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE;
> +
> + /* Initialize the TIMER 0 */
> + p = gen_write_to_addr(p, 0x80000304, 39);
// *GPTIMER_SCALER_RELOAD = 40 - 1;
> + p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
// *GPTIMER0_COUNTER_RELOAD = 0xFFFE;
> + p = gen_write_to_addr(p, 0x80000318, 3);
// *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;
> +
> + /* JUMP to the entry point */
> + stl_p(p++, 0x82100000); /* mov %g0, %g1 */
> + stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
> + /* sethi %hi(kernel_addr), %g1 */
> + stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
> + /* or kernel_addr, %g1 */
> + stl_p(p++, 0x81c04000); /* jmp %g1 */
> + stl_p(p++, 0x01000000); /* nop */
> +}
Thanks for adding write_bootloader(), I really appreciate your effort.
With the comments:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> +
> static void main_cpu_reset(void *opaque)
> {
> ResetData *s = (ResetData *)opaque;
> @@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
> /* Reset data */
> reset_info = g_malloc0(sizeof(ResetData));
> reset_info->cpu = cpu;
> - reset_info->sp = 0x40000000 + ram_size;
> + reset_info->sp = LEON3_RAM_OFFSET + ram_size;
> qemu_register_reset(main_cpu_reset, reset_info);
>
> /* Allocate IRQ manager */
> - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
> + grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
> + &leon3_set_pil_in);
>
> env->qemu_irq_ack = leon3_irq_manager;
>
> @@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
> }
>
> memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
> - memory_region_add_subregion(address_space_mem, 0x40000000, ram);
> + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
>
> /* Allocate BIOS */
> prom_size = 8 * MiB;
> memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
> memory_region_set_readonly(prom, true);
> - memory_region_add_subregion(address_space_mem, 0x00000000, prom);
> + memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
>
> /* Load boot prom */
> if (bios_name == NULL) {
> @@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
> }
>
> if (bios_size > 0) {
> - ret = load_image_targphys(filename, 0x00000000, bios_size);
> + ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
> if (ret < 0 || ret > prom_size) {
> error_report("could not load prom '%s'", filename);
> exit(1);
> @@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
> exit(1);
> }
> if (bios_size <= 0) {
> - /* If there is no bios/monitor, start the application. */
> - env->pc = entry;
> - env->npc = entry + 4;
> - reset_info->entry = entry;
> + /*
> + * If there is no bios/monitor just start the application but put
> + * the machine in an initialized state through a little
> + * bootloader.
> + */
> + uint8_t *bootloader_entry;
> +
> + bootloader_entry = memory_region_get_ram_ptr(prom);
> + write_bootloader(env, bootloader_entry, entry);
> + env->pc = LEON3_PROM_OFFSET;
> + env->npc = LEON3_PROM_OFFSET + 4;
> + reset_info->entry = LEON3_PROM_OFFSET;
> }
> }
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 14:37 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-23 14:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: peter.maydell, mark.cave-ayland, atar4qemu, chouteau
Hi Philippe,
Le 4/23/19 à 4:20 PM, Philippe Mathieu-Daudé a écrit :
> Hi Frederic,
>
> On 4/19/19 12:18 PM, KONRAD Frederic wrote:
>> This adds a little bootloader to the leon3_machine when a ram image is
>> given through the kernel parameter and no bios are provided:
>> * The UART transmiter is enabled.
>> * The TIMER is initialized.
>>
>> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
>> ---
>> hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
>> 1 file changed, 70 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
>> index 774639a..2c6f486 100644
>> --- a/hw/sparc/leon3.c
>> +++ b/hw/sparc/leon3.c
>> @@ -1,7 +1,7 @@
>> /*
>> * QEMU Leon3 System Emulator
>> *
>> - * Copyright (c) 2010-2011 AdaCore
>> + * Copyright (c) 2010-2019 AdaCore
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a copy
>> * of this software and associated documentation files (the "Software"), to deal
>> @@ -44,6 +44,8 @@
>> #define CPU_CLK (40 * 1000 * 1000)
>>
>> #define PROM_FILENAME "u-boot.bin"
>> +#define LEON3_PROM_OFFSET (0x00000000)
>> +#define LEON3_RAM_OFFSET (0x40000000)
>
> I'd have split this patch in 2, first add/use these definitions, then
> the bootloader code, but that's OK.
I hesitated but finally I choose to do it like that since all the other OFFSET
comes in the second patch.
>
>>
>> #define MAX_PILS 16
>>
>> @@ -53,6 +55,55 @@ typedef struct ResetData {
>> target_ulong sp; /* initial stack pointer */
>> } ResetData;
>>
>> +static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
>
> Can you rename that gen_store_u32()?
> If you prefer gen_write_to_addr() that's fine.
>
>> +{
>> + stl_p(code++, 0x82100000); /* mov %g0, %g1 */
>> + stl_p(code++, 0x84100000); /* mov %g0, %g2 */
>> + stl_p(code++, 0x03000000 +
>> + extract32(addr, 10, 22));
>> + /* sethi %hi(addr), %g1 */
>> + stl_p(code++, 0x82106000 +
>> + extract32(addr, 0, 10));
>> + /* or %g1, addr, %g1 */
>> + stl_p(code++, 0x05000000 +
>> + extract32(val, 10, 22));
>> + /* sethi %hi(val), %g2 */
>> + stl_p(code++, 0x8410a000 +
>> + extract32(val, 0, 10));
>> + /* or %g2, val, %g2 */
>> + stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
>> +
>> + return code;
>> +}
>> +
>> +/*
>> + * When loading a kernel in RAM the machine is expected to be in a different
>> + * state (eg: initialized by the bootloader). This little code reproduces
>> + * this behavior.
>> + */
>> +static void write_bootloader(CPUSPARCState *env, uint8_t *base,
>> + hwaddr kernel_addr)
>> +{
>> + uint32_t *p = (uint32_t *) base;
>> +
>> + /* Initialize the UARTs */
>> + p = gen_write_to_addr(p, 0x80000108, 3);
>
> Can you add comments?
> Here are the notes I took while reviewing, they might be enough:
>
> // *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE;
>
>> +
>> + /* Initialize the TIMER 0 */
>> + p = gen_write_to_addr(p, 0x80000304, 39);
>
> // *GPTIMER_SCALER_RELOAD = 40 - 1;
>
>> + p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
>
> // *GPTIMER0_COUNTER_RELOAD = 0xFFFE;
>
>> + p = gen_write_to_addr(p, 0x80000318, 3);
>
> // *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;
>
>> +
>> + /* JUMP to the entry point */
>> + stl_p(p++, 0x82100000); /* mov %g0, %g1 */
>> + stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
>> + /* sethi %hi(kernel_addr), %g1 */
>> + stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
>> + /* or kernel_addr, %g1 */
>> + stl_p(p++, 0x81c04000); /* jmp %g1 */
>> + stl_p(p++, 0x01000000); /* nop */
>> +}
>
> Thanks for adding write_bootloader(), I really appreciate your effort.
No problem. Thanks YOU for the review.
>
> With the comments:
Will add the comments in the V2.
Regards,
Fred
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
>> +
>> static void main_cpu_reset(void *opaque)
>> {
>> ResetData *s = (ResetData *)opaque;
>> @@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
>> /* Reset data */
>> reset_info = g_malloc0(sizeof(ResetData));
>> reset_info->cpu = cpu;
>> - reset_info->sp = 0x40000000 + ram_size;
>> + reset_info->sp = LEON3_RAM_OFFSET + ram_size;
>> qemu_register_reset(main_cpu_reset, reset_info);
>>
>> /* Allocate IRQ manager */
>> - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
>> + grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
>> + &leon3_set_pil_in);
>>
>> env->qemu_irq_ack = leon3_irq_manager;
>>
>> @@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
>> }
>>
>> memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
>> - memory_region_add_subregion(address_space_mem, 0x40000000, ram);
>> + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
>>
>> /* Allocate BIOS */
>> prom_size = 8 * MiB;
>> memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
>> memory_region_set_readonly(prom, true);
>> - memory_region_add_subregion(address_space_mem, 0x00000000, prom);
>> + memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
>>
>> /* Load boot prom */
>> if (bios_name == NULL) {
>> @@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
>> }
>>
>> if (bios_size > 0) {
>> - ret = load_image_targphys(filename, 0x00000000, bios_size);
>> + ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
>> if (ret < 0 || ret > prom_size) {
>> error_report("could not load prom '%s'", filename);
>> exit(1);
>> @@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
>> exit(1);
>> }
>> if (bios_size <= 0) {
>> - /* If there is no bios/monitor, start the application. */
>> - env->pc = entry;
>> - env->npc = entry + 4;
>> - reset_info->entry = entry;
>> + /*
>> + * If there is no bios/monitor just start the application but put
>> + * the machine in an initialized state through a little
>> + * bootloader.
>> + */
>> + uint8_t *bootloader_entry;
>> +
>> + bootloader_entry = memory_region_get_ram_ptr(prom);
>> + write_bootloader(env, bootloader_entry, entry);
>> + env->pc = LEON3_PROM_OFFSET;
>> + env->npc = LEON3_PROM_OFFSET + 4;
>> + reset_info->entry = LEON3_PROM_OFFSET;
>> }
>> }
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader
@ 2019-04-23 14:37 ` KONRAD Frederic
0 siblings, 0 replies; 20+ messages in thread
From: KONRAD Frederic @ 2019-04-23 14:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: peter.maydell, mark.cave-ayland, chouteau, atar4qemu
Hi Philippe,
Le 4/23/19 à 4:20 PM, Philippe Mathieu-Daudé a écrit :
> Hi Frederic,
>
> On 4/19/19 12:18 PM, KONRAD Frederic wrote:
>> This adds a little bootloader to the leon3_machine when a ram image is
>> given through the kernel parameter and no bios are provided:
>> * The UART transmiter is enabled.
>> * The TIMER is initialized.
>>
>> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
>> ---
>> hw/sparc/leon3.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------
>> 1 file changed, 70 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
>> index 774639a..2c6f486 100644
>> --- a/hw/sparc/leon3.c
>> +++ b/hw/sparc/leon3.c
>> @@ -1,7 +1,7 @@
>> /*
>> * QEMU Leon3 System Emulator
>> *
>> - * Copyright (c) 2010-2011 AdaCore
>> + * Copyright (c) 2010-2019 AdaCore
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a copy
>> * of this software and associated documentation files (the "Software"), to deal
>> @@ -44,6 +44,8 @@
>> #define CPU_CLK (40 * 1000 * 1000)
>>
>> #define PROM_FILENAME "u-boot.bin"
>> +#define LEON3_PROM_OFFSET (0x00000000)
>> +#define LEON3_RAM_OFFSET (0x40000000)
>
> I'd have split this patch in 2, first add/use these definitions, then
> the bootloader code, but that's OK.
I hesitated but finally I choose to do it like that since all the other OFFSET
comes in the second patch.
>
>>
>> #define MAX_PILS 16
>>
>> @@ -53,6 +55,55 @@ typedef struct ResetData {
>> target_ulong sp; /* initial stack pointer */
>> } ResetData;
>>
>> +static uint32_t *gen_write_to_addr(uint32_t *code, hwaddr addr, uint32_t val)
>
> Can you rename that gen_store_u32()?
> If you prefer gen_write_to_addr() that's fine.
>
>> +{
>> + stl_p(code++, 0x82100000); /* mov %g0, %g1 */
>> + stl_p(code++, 0x84100000); /* mov %g0, %g2 */
>> + stl_p(code++, 0x03000000 +
>> + extract32(addr, 10, 22));
>> + /* sethi %hi(addr), %g1 */
>> + stl_p(code++, 0x82106000 +
>> + extract32(addr, 0, 10));
>> + /* or %g1, addr, %g1 */
>> + stl_p(code++, 0x05000000 +
>> + extract32(val, 10, 22));
>> + /* sethi %hi(val), %g2 */
>> + stl_p(code++, 0x8410a000 +
>> + extract32(val, 0, 10));
>> + /* or %g2, val, %g2 */
>> + stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
>> +
>> + return code;
>> +}
>> +
>> +/*
>> + * When loading a kernel in RAM the machine is expected to be in a different
>> + * state (eg: initialized by the bootloader). This little code reproduces
>> + * this behavior.
>> + */
>> +static void write_bootloader(CPUSPARCState *env, uint8_t *base,
>> + hwaddr kernel_addr)
>> +{
>> + uint32_t *p = (uint32_t *) base;
>> +
>> + /* Initialize the UARTs */
>> + p = gen_write_to_addr(p, 0x80000108, 3);
>
> Can you add comments?
> Here are the notes I took while reviewing, they might be enough:
>
> // *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE;
>
>> +
>> + /* Initialize the TIMER 0 */
>> + p = gen_write_to_addr(p, 0x80000304, 39);
>
> // *GPTIMER_SCALER_RELOAD = 40 - 1;
>
>> + p = gen_write_to_addr(p, 0x80000314, 0xFFFFFFFE);
>
> // *GPTIMER0_COUNTER_RELOAD = 0xFFFE;
>
>> + p = gen_write_to_addr(p, 0x80000318, 3);
>
> // *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;
>
>> +
>> + /* JUMP to the entry point */
>> + stl_p(p++, 0x82100000); /* mov %g0, %g1 */
>> + stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
>> + /* sethi %hi(kernel_addr), %g1 */
>> + stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
>> + /* or kernel_addr, %g1 */
>> + stl_p(p++, 0x81c04000); /* jmp %g1 */
>> + stl_p(p++, 0x01000000); /* nop */
>> +}
>
> Thanks for adding write_bootloader(), I really appreciate your effort.
No problem. Thanks YOU for the review.
>
> With the comments:
Will add the comments in the V2.
Regards,
Fred
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
>> +
>> static void main_cpu_reset(void *opaque)
>> {
>> ResetData *s = (ResetData *)opaque;
>> @@ -131,11 +182,12 @@ static void leon3_generic_hw_init(MachineState *machine)
>> /* Reset data */
>> reset_info = g_malloc0(sizeof(ResetData));
>> reset_info->cpu = cpu;
>> - reset_info->sp = 0x40000000 + ram_size;
>> + reset_info->sp = LEON3_RAM_OFFSET + ram_size;
>> qemu_register_reset(main_cpu_reset, reset_info);
>>
>> /* Allocate IRQ manager */
>> - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
>> + grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS,
>> + &leon3_set_pil_in);
>>
>> env->qemu_irq_ack = leon3_irq_manager;
>>
>> @@ -148,13 +200,13 @@ static void leon3_generic_hw_init(MachineState *machine)
>> }
>>
>> memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size);
>> - memory_region_add_subregion(address_space_mem, 0x40000000, ram);
>> + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram);
>>
>> /* Allocate BIOS */
>> prom_size = 8 * MiB;
>> memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
>> memory_region_set_readonly(prom, true);
>> - memory_region_add_subregion(address_space_mem, 0x00000000, prom);
>> + memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
>>
>> /* Load boot prom */
>> if (bios_name == NULL) {
>> @@ -174,7 +226,7 @@ static void leon3_generic_hw_init(MachineState *machine)
>> }
>>
>> if (bios_size > 0) {
>> - ret = load_image_targphys(filename, 0x00000000, bios_size);
>> + ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
>> if (ret < 0 || ret > prom_size) {
>> error_report("could not load prom '%s'", filename);
>> exit(1);
>> @@ -198,10 +250,18 @@ static void leon3_generic_hw_init(MachineState *machine)
>> exit(1);
>> }
>> if (bios_size <= 0) {
>> - /* If there is no bios/monitor, start the application. */
>> - env->pc = entry;
>> - env->npc = entry + 4;
>> - reset_info->entry = entry;
>> + /*
>> + * If there is no bios/monitor just start the application but put
>> + * the machine in an initialized state through a little
>> + * bootloader.
>> + */
>> + uint8_t *bootloader_entry;
>> +
>> + bootloader_entry = memory_region_get_ram_ptr(prom);
>> + write_bootloader(env, bootloader_entry, entry);
>> + env->pc = LEON3_PROM_OFFSET;
>> + env->npc = LEON3_PROM_OFFSET + 4;
>> + reset_info->entry = LEON3_PROM_OFFSET;
>> }
>> }
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-04-23 14:38 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-19 10:18 [Qemu-devel] [PATCH V1 0/3] Leon3 patches KONRAD Frederic
2019-04-19 10:18 ` KONRAD Frederic
2019-04-19 10:18 ` [Qemu-devel] [PATCH V1 1/3] leon3: add a little bootloader KONRAD Frederic
2019-04-19 10:18 ` KONRAD Frederic
2019-04-23 10:58 ` Fabien Chouteau
2019-04-23 10:58 ` Fabien Chouteau
2019-04-23 14:20 ` Philippe Mathieu-Daudé
2019-04-23 14:20 ` Philippe Mathieu-Daudé
2019-04-23 14:37 ` KONRAD Frederic
2019-04-23 14:37 ` KONRAD Frederic
2019-04-19 10:18 ` [Qemu-devel] [PATCH V1 2/3] leon3: introduce the plug and play mecanism KONRAD Frederic
2019-04-19 10:18 ` KONRAD Frederic
2019-04-23 10:59 ` Fabien Chouteau
2019-04-23 10:59 ` Fabien Chouteau
2019-04-19 10:18 ` [Qemu-devel] [PATCH V1 3/3] MAINTAINERS: add myself for leon3 KONRAD Frederic
2019-04-19 10:18 ` KONRAD Frederic
2019-04-23 10:59 ` Fabien Chouteau
2019-04-23 10:59 ` Fabien Chouteau
2019-04-23 14:03 ` Philippe Mathieu-Daudé
2019-04-23 14:03 ` Philippe Mathieu-Daudé
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.