[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct
v4: Use more generic name for remapped page
    Expose register offset in kfd_ioctl.h

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 ++++++
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 18 ++++++++++++++++++
 include/uapi/linux/kfd_ioctl.h         |  7 +++++++
 5 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..d71aa6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -642,6 +642,11 @@ struct nbio_hdp_flush_reg {
 	u32 ref_and_mask_sdma1;
 };
 
+struct amdgpu_mmio_remap {
+	u32 reg_offset;
+	resource_size_t bus_addr;
+};
+
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -767,6 +772,7 @@ struct amdgpu_device {
 	void __iomem			*rmmio;
 	/* protects concurrent MM_INDEX/DATA based register access */
 	spinlock_t mmio_idx_lock;
+	struct amdgpu_mmio_remap        rmmio_remap;
 	/* protects concurrent SMC based register access */
 	spinlock_t smc_idx_lock;
 	amdgpu_rreg_t			smc_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..afd1586 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -29,6 +29,7 @@
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
 
@@ -55,10 +56,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..c211b1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -27,6 +27,7 @@
 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "nbio/nbio_7_4_0_smn.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
 
@@ -53,10 +54,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..291290d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -64,6 +65,7 @@
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
 #include "amdgpu_smu.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
@@ -775,6 +777,21 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 	.need_reset_on_init = &soc15_need_reset_on_init,
 };
 
+static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
+{
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+	/* Remap hdp coherency registers to a hole in register space,
+	 * for the purpose of mapping them to process space(so process
+	 * can flush hdp)
+	 */
+	adev->rmmio_remap.reg_offset = (MMIO_REG_HOLE_OFFSET) >> 2;
+	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_REG_FLUSH_CNTL);
+}
+
 static int soc15_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -794,6 +811,7 @@ static int soc15_common_early_init(void *handle)
 
 
 	adev->external_rev_id = 0xFF;
+	soc15_remap_hdp_coherency_registers(adev);
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		adev->asic_funcs = &soc15_asic_funcs;
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index dc067ed..7524e6e 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -426,6 +426,13 @@ struct kfd_ioctl_import_dmabuf_args {
 	__u32 dmabuf_fd;	/* to KFD */
 };
 
+/* Register offset inside the remapped mmio page
+ */
+enum kfd_mmio_remap {
+	HDP_MEM_FLUSH_CNTL = 0,
+	HDP_REG_FLUSH_CNTL = 4,
+};
+
 #define AMDKFD_IOCTL_BASE 'K'
 #define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
 #define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
-- 
2.7.4

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[PATCH 2/2] drm/amdkfd: Expose HDP registers to user space

[Zeng, Oak]

Introduce a new memory type (KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) and
expose mmio page of HDP registers to user space through this new
memory type.

v2: moved remapped hdp regs to adev struct
v3: rename the new memory type to ALLOC_MEM_FLAGS_MMIO_REMAP
v4: use more generic function name

Change-Id: If5ac13c46ea7fbd2194ddc8b2ece26ef4f76c330
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c       | 7 +++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h       | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 7 ++++---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c         | 4 ++++
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h  | 1 +
 include/uapi/linux/kfd_ioctl.h                   | 1 +
 6 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index acf8ae0..03c3ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -482,6 +482,13 @@ uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
 	return adev->gmc.xgmi.hive_id;
 }
 
+uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+
+	return adev->rmmio_remap.bus_addr;
+}
+
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 				uint32_t vmid, uint64_t gpu_addr,
 				uint32_t *ib_cmd, uint32_t ib_len)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index e6a5037..e45ba9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -154,6 +154,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
 				  uint32_t *flags);
 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
+uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
 
 #define read_user_wptr(mmptr, wptr, dst)				\
 	({								\
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 047bba8..697b8ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1087,7 +1087,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		if (!offset || !*offset)
 			return -EINVAL;
 		user_addr = *offset;
-	} else if (flags & ALLOC_MEM_FLAGS_DOORBELL) {
+	} else if (flags & (ALLOC_MEM_FLAGS_DOORBELL |
+			ALLOC_MEM_FLAGS_MMIO_REMAP)) {
 		domain = AMDGPU_GEM_DOMAIN_GTT;
 		alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
 		bo_type = ttm_bo_type_sg;
@@ -1263,8 +1264,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 	/* Free the sync object */
 	amdgpu_sync_free(&mem->sync);
 
-	/* If the SG is not NULL, it's one we created for a doorbell
-	 * BO. We need to free it.
+	/* If the SG is not NULL, it's one we created for a doorbell or mmio
+	 * remap BO. We need to free it.
 	 */
 	if (mem->bo->tbo.sg) {
 		sg_free_table(mem->bo->tbo.sg);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 083bd81..9b907e1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1272,6 +1272,10 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
 		if (args->size != kfd_doorbell_process_slice(dev))
 			return -EINVAL;
 		offset = kfd_get_process_doorbells(dev, p);
+	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
+		if (args->size != PAGE_SIZE)
+			return -EINVAL;
+		offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
 	}
 
 	mutex_lock(&p->mutex);
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 5f3c10e..3ecb109 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -186,6 +186,7 @@ struct tile_config {
 #define ALLOC_MEM_FLAGS_GTT		(1 << 1)
 #define ALLOC_MEM_FLAGS_USERPTR		(1 << 2)
 #define ALLOC_MEM_FLAGS_DOORBELL	(1 << 3)
+#define ALLOC_MEM_FLAGS_MMIO_REMAP	(1 << 4)
 
 /*
  * Allocation flags attributes/access options.
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 7524e6e..f5aada4 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -338,6 +338,7 @@ struct kfd_ioctl_acquire_vm_args {
 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT		(1 << 1)
 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR		(1 << 2)
 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL	(1 << 3)
+#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP	(1 << 4)
 /* Allocation flags: attributes/access options */
 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE	(1 << 31)
 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE	(1 << 30)
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct
v4: Use more generic name for remapped page
    Expose register offset in kfd_ioctl.h
v5: Move hdp register remap function to nbio ip function
v6: Fixed operator precedence issue and other bugs

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  7 +++++++
 drivers/gpu/drm/amd/amdgpu/cik.c       |  1 +
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 ++++++++++++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 15 ++++++++++++---
 drivers/gpu/drm/amd/amdgpu/si.c        |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 11 +++++++++++
 drivers/gpu/drm/amd/amdgpu/vi.c        |  1 +
 include/uapi/linux/kfd_ioctl.h         |  7 +++++++
 8 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..e16dcee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -642,6 +642,11 @@ struct nbio_hdp_flush_reg {
 	u32 ref_and_mask_sdma1;
 };
 
+struct amdgpu_mmio_remap {
+	u32 reg_offset;
+	resource_size_t bus_addr;
+};
+
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -669,6 +674,7 @@ struct amdgpu_nbio_funcs {
 	void (*ih_control)(struct amdgpu_device *adev);
 	void (*init_registers)(struct amdgpu_device *adev);
 	void (*detect_hw_virt)(struct amdgpu_device *adev);
+	void (*remap_hdp_registers)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_df_funcs {
@@ -767,6 +773,7 @@ struct amdgpu_device {
 	void __iomem			*rmmio;
 	/* protects concurrent MM_INDEX/DATA based register access */
 	spinlock_t mmio_idx_lock;
+	struct amdgpu_mmio_remap        rmmio_remap;
 	/* protects concurrent SMC based register access */
 	spinlock_t smc_idx_lock;
 	amdgpu_rreg_t			smc_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 07c1f23..3f7ec6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1827,6 +1827,7 @@ static int cik_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->smc_rreg = &cik_smc_rreg;
 	adev->smc_wreg = &cik_smc_wreg;
 	adev->pcie_rreg = &cik_pcie_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..73419fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -29,9 +29,18 @@
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
 
+static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -55,10 +64,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
@@ -283,4 +291,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 	.ih_control = nbio_v7_0_ih_control,
 	.init_registers = nbio_v7_0_init_registers,
 	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
+	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..bfaaa32 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -27,9 +27,18 @@
 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "nbio/nbio_7_4_0_smn.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
 
+static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -53,10 +62,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
@@ -262,4 +270,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 	.ih_control = nbio_v7_4_ih_control,
 	.init_registers = nbio_v7_4_init_registers,
 	.detect_hw_virt = nbio_v7_4_detect_hw_virt,
+	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 9d8df68..c6b89c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1405,6 +1405,7 @@ static int si_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->smc_rreg = &si_smc_rreg;
 	adev->smc_wreg = &si_smc_wreg;
 	adev->pcie_rreg = &si_pcie_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..ea416ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -64,6 +65,7 @@
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
 #include "amdgpu_smu.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
@@ -777,8 +779,11 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 
 static int soc15_common_early_init(void *handle)
 {
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 	adev->smc_rreg = NULL;
 	adev->smc_wreg = NULL;
 	adev->pcie_rreg = &soc15_pcie_rreg;
@@ -1007,6 +1012,12 @@ static int soc15_common_hw_init(void *handle)
 	soc15_program_aspm(adev);
 	/* setup nbio registers */
 	adev->nbio_funcs->init_registers(adev);
+	/* remap HDP registers to a hole in mmio space,
+	 * for the purpose of expose those registers
+	 * to process space
+	 */
+	if (adev->nbio_funcs->remap_hdp_registers)
+		adev->nbio_funcs->remap_hdp_registers(adev);
 	/* enable the doorbell aperture */
 	soc15_enable_doorbell_aperture(adev, true);
 	/* HW doorbell routing policy: doorbell writing not
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5e5b42a..44565b23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1037,6 +1037,7 @@ static int vi_common_early_init(void *handle)
 		adev->smc_rreg = &vi_smc_rreg;
 		adev->smc_wreg = &vi_smc_wreg;
 	}
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->pcie_rreg = &vi_pcie_rreg;
 	adev->pcie_wreg = &vi_pcie_wreg;
 	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index dc067ed..bb1b428 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -426,6 +426,13 @@ struct kfd_ioctl_import_dmabuf_args {
 	__u32 dmabuf_fd;	/* to KFD */
 };
 
+/* Register offset inside the remapped mmio page
+ */
+enum kfd_mmio_remap {
+	KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
+	KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
+};
+
 #define AMDKFD_IOCTL_BASE 'K'
 #define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
 #define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Kuehling, Felix]

One more nit-pick inline.

On 2019-04-23 4:59 p.m., Zeng, Oak wrote:
> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
> to an empty page in mmio space. We will later map this page to process
> space so application can flush hdp. This can't be done properly at
> those registers' original location because it will expose more than
> desired registers to process space.
>
> v2: Use explicit register hole location
> v3: Moved remapped hdp registers into adev struct
> v4: Use more generic name for remapped page
>      Expose register offset in kfd_ioctl.h
> v5: Move hdp register remap function to nbio ip function
> v6: Fixed operator precedence issue and other bugs
>
> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  7 +++++++
>   drivers/gpu/drm/amd/amdgpu/cik.c       |  1 +
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 ++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 15 ++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/si.c        |  1 +
>   drivers/gpu/drm/amd/amdgpu/soc15.c     | 11 +++++++++++
>   drivers/gpu/drm/amd/amdgpu/vi.c        |  1 +
>   include/uapi/linux/kfd_ioctl.h         |  7 +++++++
>   8 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bc96ec4..e16dcee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -642,6 +642,11 @@ struct nbio_hdp_flush_reg {
>   	u32 ref_and_mask_sdma1;
>   };
>   
> +struct amdgpu_mmio_remap {
> +	u32 reg_offset;
> +	resource_size_t bus_addr;
> +};
> +
>   struct amdgpu_nbio_funcs {
>   	const struct nbio_hdp_flush_reg *hdp_flush_reg;
>   	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
> @@ -669,6 +674,7 @@ struct amdgpu_nbio_funcs {
>   	void (*ih_control)(struct amdgpu_device *adev);
>   	void (*init_registers)(struct amdgpu_device *adev);
>   	void (*detect_hw_virt)(struct amdgpu_device *adev);
> +	void (*remap_hdp_registers)(struct amdgpu_device *adev);
>   };
>   
>   struct amdgpu_df_funcs {
> @@ -767,6 +773,7 @@ struct amdgpu_device {
>   	void __iomem			*rmmio;
>   	/* protects concurrent MM_INDEX/DATA based register access */
>   	spinlock_t mmio_idx_lock;
> +	struct amdgpu_mmio_remap        rmmio_remap;
>   	/* protects concurrent SMC based register access */
>   	spinlock_t smc_idx_lock;
>   	amdgpu_rreg_t			smc_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 07c1f23..3f7ec6a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1827,6 +1827,7 @@ static int cik_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;

It would be easier to just not do this and define 0 as "no MMIO 
remapping". That way you don't have to change cik.c, si.c and vi.c and 
only need to worry about chips that actually do support it.

Then the condition in patch 2 would need to change as well:

> +		offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
> +		if (!offset)
> +			return -ENOMEM;

With that fixed, the series is Reviewed-by: Felix Kuehling 
<Felix.Kuehling@amd.com>


>   	adev->smc_rreg = &cik_smc_rreg;
>   	adev->smc_wreg = &cik_smc_wreg;
>   	adev->pcie_rreg = &cik_pcie_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98a..73419fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -29,9 +29,18 @@
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "vega10_enum.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
>   
> +static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
> +{
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> +}
> +
>   static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
>   {
>           u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> @@ -55,10 +64,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>   }
>   
>   static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> @@ -283,4 +291,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>   	.ih_control = nbio_v7_0_ih_control,
>   	.init_registers = nbio_v7_0_init_registers,
>   	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
> +	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index c69d515..bfaaa32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -27,9 +27,18 @@
>   #include "nbio/nbio_7_4_offset.h"
>   #include "nbio/nbio_7_4_sh_mask.h"
>   #include "nbio/nbio_7_4_0_smn.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
>   
> +static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
> +{
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> +}
> +
>   static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
>   {
>   	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> @@ -53,10 +62,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>   }
>   
>   static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> @@ -262,4 +270,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>   	.ih_control = nbio_v7_4_ih_control,
>   	.init_registers = nbio_v7_4_init_registers,
>   	.detect_hw_virt = nbio_v7_4_detect_hw_virt,
> +	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 9d8df68..c6b89c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1405,6 +1405,7 @@ static int si_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;
>   	adev->smc_rreg = &si_smc_rreg;
>   	adev->smc_wreg = &si_smc_wreg;
>   	adev->pcie_rreg = &si_pcie_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bdb5ad9..ea416ff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -44,6 +44,7 @@
>   #include "smuio/smuio_9_0_offset.h"
>   #include "smuio/smuio_9_0_sh_mask.h"
>   #include "nbio/nbio_7_0_default.h"
> +#include "nbio/nbio_7_0_offset.h"
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "mp/mp_9_0_offset.h"
> @@ -64,6 +65,7 @@
>   #include "dce_virtual.h"
>   #include "mxgpu_ai.h"
>   #include "amdgpu_smu.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
>   #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
> @@ -777,8 +779,11 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>   
>   static int soc15_common_early_init(void *handle)
>   {
> +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
> +	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
>   	adev->smc_rreg = NULL;
>   	adev->smc_wreg = NULL;
>   	adev->pcie_rreg = &soc15_pcie_rreg;
> @@ -1007,6 +1012,12 @@ static int soc15_common_hw_init(void *handle)
>   	soc15_program_aspm(adev);
>   	/* setup nbio registers */
>   	adev->nbio_funcs->init_registers(adev);
> +	/* remap HDP registers to a hole in mmio space,
> +	 * for the purpose of expose those registers
> +	 * to process space
> +	 */
> +	if (adev->nbio_funcs->remap_hdp_registers)
> +		adev->nbio_funcs->remap_hdp_registers(adev);
>   	/* enable the doorbell aperture */
>   	soc15_enable_doorbell_aperture(adev, true);
>   	/* HW doorbell routing policy: doorbell writing not
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 5e5b42a..44565b23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1037,6 +1037,7 @@ static int vi_common_early_init(void *handle)
>   		adev->smc_rreg = &vi_smc_rreg;
>   		adev->smc_wreg = &vi_smc_wreg;
>   	}
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;
>   	adev->pcie_rreg = &vi_pcie_rreg;
>   	adev->pcie_wreg = &vi_pcie_wreg;
>   	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
> diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
> index dc067ed..bb1b428 100644
> --- a/include/uapi/linux/kfd_ioctl.h
> +++ b/include/uapi/linux/kfd_ioctl.h
> @@ -426,6 +426,13 @@ struct kfd_ioctl_import_dmabuf_args {
>   	__u32 dmabuf_fd;	/* to KFD */
>   };
>   
> +/* Register offset inside the remapped mmio page
> + */
> +enum kfd_mmio_remap {
> +	KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
> +	KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
> +};
> +
>   #define AMDKFD_IOCTL_BASE 'K'
>   #define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
>   #define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
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[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct
v4: Use more generic name for remapped page
    Expose register offset in kfd_ioctl.h
v5: Move hdp register remap function to nbio ip function

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  7 +++++++
 drivers/gpu/drm/amd/amdgpu/cik.c       |  1 +
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 ++++++++++++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 15 ++++++++++++---
 drivers/gpu/drm/amd/amdgpu/si.c        |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 11 +++++++++++
 drivers/gpu/drm/amd/amdgpu/vi.c        |  1 +
 include/uapi/linux/kfd_ioctl.h         |  7 +++++++
 8 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..e16dcee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -642,6 +642,11 @@ struct nbio_hdp_flush_reg {
 	u32 ref_and_mask_sdma1;
 };
 
+struct amdgpu_mmio_remap {
+	u32 reg_offset;
+	resource_size_t bus_addr;
+};
+
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -669,6 +674,7 @@ struct amdgpu_nbio_funcs {
 	void (*ih_control)(struct amdgpu_device *adev);
 	void (*init_registers)(struct amdgpu_device *adev);
 	void (*detect_hw_virt)(struct amdgpu_device *adev);
+	void (*remap_hdp_registers)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_df_funcs {
@@ -767,6 +773,7 @@ struct amdgpu_device {
 	void __iomem			*rmmio;
 	/* protects concurrent MM_INDEX/DATA based register access */
 	spinlock_t mmio_idx_lock;
+	struct amdgpu_mmio_remap        rmmio_remap;
 	/* protects concurrent SMC based register access */
 	spinlock_t smc_idx_lock;
 	amdgpu_rreg_t			smc_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 07c1f23..3f7ec6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1827,6 +1827,7 @@ static int cik_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->smc_rreg = &cik_smc_rreg;
 	adev->smc_wreg = &cik_smc_wreg;
 	adev->pcie_rreg = &cik_pcie_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..83f1f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -29,9 +29,18 @@
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
 
+static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_REG_FLUSH_CNTL);
+}
+
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -55,10 +64,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
@@ -283,4 +291,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 	.ih_control = nbio_v7_0_ih_control,
 	.init_registers = nbio_v7_0_init_registers,
 	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
+	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..fa67772 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -27,9 +27,18 @@
 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "nbio/nbio_7_4_0_smn.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
 
+static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset << 2 + HDP_REG_FLUSH_CNTL);
+}
+
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -53,10 +62,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
@@ -262,4 +270,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 	.ih_control = nbio_v7_4_ih_control,
 	.init_registers = nbio_v7_4_init_registers,
 	.detect_hw_virt = nbio_v7_4_detect_hw_virt,
+	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 9d8df68..c6b89c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1405,6 +1405,7 @@ static int si_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->smc_rreg = &si_smc_rreg;
 	adev->smc_wreg = &si_smc_wreg;
 	adev->pcie_rreg = &si_pcie_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..3685944 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -64,6 +65,7 @@
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
 #include "amdgpu_smu.h"
+#include <uapi/linux/kfd_ioctl.h>
 
 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
@@ -777,8 +779,11 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 
 static int soc15_common_early_init(void *handle)
 {
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->rmmio_remap.reg_offset = (MMIO_REG_HOLE_OFFSET) >> 2;
+	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 	adev->smc_rreg = NULL;
 	adev->smc_wreg = NULL;
 	adev->pcie_rreg = &soc15_pcie_rreg;
@@ -1007,6 +1012,12 @@ static int soc15_common_hw_init(void *handle)
 	soc15_program_aspm(adev);
 	/* setup nbio registers */
 	adev->nbio_funcs->init_registers(adev);
+	/* remap HDP registers to a hole in mmio space,
+	 * for the purpose of expose those registers
+	 * to process space
+	 */
+	if (adev->nbio_funcs->remap_hdp_registers)
+		adev->nbio_funcs->remap_hdp_registers(adev);
 	/* enable the doorbell aperture */
 	soc15_enable_doorbell_aperture(adev, true);
 	/* HW doorbell routing policy: doorbell writing not
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5e5b42a..44565b23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1037,6 +1037,7 @@ static int vi_common_early_init(void *handle)
 		adev->smc_rreg = &vi_smc_rreg;
 		adev->smc_wreg = &vi_smc_wreg;
 	}
+	adev->rmmio_remap.bus_addr = ULLONG_MAX;
 	adev->pcie_rreg = &vi_pcie_rreg;
 	adev->pcie_wreg = &vi_pcie_wreg;
 	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index dc067ed..7524e6e 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -426,6 +426,13 @@ struct kfd_ioctl_import_dmabuf_args {
 	__u32 dmabuf_fd;	/* to KFD */
 };
 
+/* Register offset inside the remapped mmio page
+ */
+enum kfd_mmio_remap {
+	HDP_MEM_FLUSH_CNTL = 0,
+	HDP_REG_FLUSH_CNTL = 4,
+};
+
 #define AMDKFD_IOCTL_BASE 'K'
 #define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
 #define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Kuehling, Felix]

See inline.

On 2019-04-23 3:23 p.m., Zeng, Oak wrote:
> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
> to an empty page in mmio space. We will later map this page to process
> space so application can flush hdp. This can't be done properly at
> those registers' original location because it will expose more than
> desired registers to process space.
>
> v2: Use explicit register hole location
> v3: Moved remapped hdp registers into adev struct
> v4: Use more generic name for remapped page
>      Expose register offset in kfd_ioctl.h
> v5: Move hdp register remap function to nbio ip function
>
> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  7 +++++++
>   drivers/gpu/drm/amd/amdgpu/cik.c       |  1 +
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 ++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 15 ++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/si.c        |  1 +
>   drivers/gpu/drm/amd/amdgpu/soc15.c     | 11 +++++++++++
>   drivers/gpu/drm/amd/amdgpu/vi.c        |  1 +
>   include/uapi/linux/kfd_ioctl.h         |  7 +++++++
>   8 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bc96ec4..e16dcee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -642,6 +642,11 @@ struct nbio_hdp_flush_reg {
>   	u32 ref_and_mask_sdma1;
>   };
>   
> +struct amdgpu_mmio_remap {
> +	u32 reg_offset;
> +	resource_size_t bus_addr;
> +};
> +
>   struct amdgpu_nbio_funcs {
>   	const struct nbio_hdp_flush_reg *hdp_flush_reg;
>   	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
> @@ -669,6 +674,7 @@ struct amdgpu_nbio_funcs {
>   	void (*ih_control)(struct amdgpu_device *adev);
>   	void (*init_registers)(struct amdgpu_device *adev);
>   	void (*detect_hw_virt)(struct amdgpu_device *adev);
> +	void (*remap_hdp_registers)(struct amdgpu_device *adev);
>   };
>   
>   struct amdgpu_df_funcs {
> @@ -767,6 +773,7 @@ struct amdgpu_device {
>   	void __iomem			*rmmio;
>   	/* protects concurrent MM_INDEX/DATA based register access */
>   	spinlock_t mmio_idx_lock;
> +	struct amdgpu_mmio_remap        rmmio_remap;
>   	/* protects concurrent SMC based register access */
>   	spinlock_t smc_idx_lock;
>   	amdgpu_rreg_t			smc_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 07c1f23..3f7ec6a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1827,6 +1827,7 @@ static int cik_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;
>   	adev->smc_rreg = &cik_smc_rreg;
>   	adev->smc_wreg = &cik_smc_wreg;
>   	adev->pcie_rreg = &cik_pcie_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98a..83f1f75 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -29,9 +29,18 @@
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "vega10_enum.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
>   
> +static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
> +{
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset << 2 + HDP_MEM_FLUSH_CNTL);

I don't think this does what you intend. I think + binds stronger than 
<<, so you should write this as

     (adev->rmmio_remap.reg_offset << 2) + HDP_MEM_FLUSH_CNTL


> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset << 2 + HDP_REG_FLUSH_CNTL);

Same as above.


> +}
> +
>   static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
>   {
>           u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> @@ -55,10 +64,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);

Are you sure this is correct? As I understand it from the above, 
adev->rmmio_remap.reg_offset is in dwords, HDP_MEM_FLUSH_CNTL is in 
bytes. Something will need to be shifted.


>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);

Same as above.


>   }
>   
>   static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> @@ -283,4 +291,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>   	.ih_control = nbio_v7_0_ih_control,
>   	.init_registers = nbio_v7_0_init_registers,
>   	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
> +	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index c69d515..fa67772 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -27,9 +27,18 @@
>   #include "nbio/nbio_7_4_offset.h"
>   #include "nbio/nbio_7_4_sh_mask.h"
>   #include "nbio/nbio_7_4_0_smn.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
>   
> +static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
> +{
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset << 2 + HDP_MEM_FLUSH_CNTL);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +		adev->rmmio_remap.reg_offset << 2 + HDP_REG_FLUSH_CNTL);

Operator precedence. See above.


> +}
> +
>   static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
>   {
>   	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> @@ -53,10 +62,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
Are adev->rmmio_remap.reg_offset and HDP_MEM_FLUSH_CNTL in the same units?
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->rmmio_remap.reg_offset + HDP_MEM_FLUSH_CNTL, 0);
>   }
>   
>   static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> @@ -262,4 +270,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>   	.ih_control = nbio_v7_4_ih_control,
>   	.init_registers = nbio_v7_4_init_registers,
>   	.detect_hw_virt = nbio_v7_4_detect_hw_virt,
> +	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 9d8df68..c6b89c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1405,6 +1405,7 @@ static int si_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;
>   	adev->smc_rreg = &si_smc_rreg;
>   	adev->smc_wreg = &si_smc_wreg;
>   	adev->pcie_rreg = &si_pcie_rreg;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bdb5ad9..3685944 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -44,6 +44,7 @@
>   #include "smuio/smuio_9_0_offset.h"
>   #include "smuio/smuio_9_0_sh_mask.h"
>   #include "nbio/nbio_7_0_default.h"
> +#include "nbio/nbio_7_0_offset.h"
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "mp/mp_9_0_offset.h"
> @@ -64,6 +65,7 @@
>   #include "dce_virtual.h"
>   #include "mxgpu_ai.h"
>   #include "amdgpu_smu.h"
> +#include <uapi/linux/kfd_ioctl.h>
>   
>   #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
>   #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
> @@ -777,8 +779,11 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>   
>   static int soc15_common_early_init(void *handle)
>   {
> +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> +	adev->rmmio_remap.reg_offset = (MMIO_REG_HOLE_OFFSET) >> 2;

Why is this shifted? I think this creates some of the confusion above 
where things have different units.


> +	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
>   	adev->smc_rreg = NULL;
>   	adev->smc_wreg = NULL;
>   	adev->pcie_rreg = &soc15_pcie_rreg;
> @@ -1007,6 +1012,12 @@ static int soc15_common_hw_init(void *handle)
>   	soc15_program_aspm(adev);
>   	/* setup nbio registers */
>   	adev->nbio_funcs->init_registers(adev);
> +	/* remap HDP registers to a hole in mmio space,
> +	 * for the purpose of expose those registers
> +	 * to process space
> +	 */
> +	if (adev->nbio_funcs->remap_hdp_registers)
> +		adev->nbio_funcs->remap_hdp_registers(adev);
>   	/* enable the doorbell aperture */
>   	soc15_enable_doorbell_aperture(adev, true);
>   	/* HW doorbell routing policy: doorbell writing not
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 5e5b42a..44565b23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1037,6 +1037,7 @@ static int vi_common_early_init(void *handle)
>   		adev->smc_rreg = &vi_smc_rreg;
>   		adev->smc_wreg = &vi_smc_wreg;
>   	}
> +	adev->rmmio_remap.bus_addr = ULLONG_MAX;
>   	adev->pcie_rreg = &vi_pcie_rreg;
>   	adev->pcie_wreg = &vi_pcie_wreg;
>   	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
> diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
> index dc067ed..7524e6e 100644
> --- a/include/uapi/linux/kfd_ioctl.h
> +++ b/include/uapi/linux/kfd_ioctl.h
> @@ -426,6 +426,13 @@ struct kfd_ioctl_import_dmabuf_args {
>   	__u32 dmabuf_fd;	/* to KFD */
>   };
>   
> +/* Register offset inside the remapped mmio page
> + */
> +enum kfd_mmio_remap {
> +	HDP_MEM_FLUSH_CNTL = 0,

This needs some prefix to disambiguate. Something to make it clear that 
this is not the MMIO register address, but an offset in a remapped 
address range. This is a bit verbose, but it's the best I can come up with:

KFD_MMIO_REMAP_HPD_MEM_FLUSH_CNTL = 0,
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,

Regards,
   Felix


> +	HDP_REG_FLUSH_CNTL = 4,
> +};
> +
>   #define AMDKFD_IOCTL_BASE 'K'
>   #define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
>   #define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
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[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location
v3: Moved remapped hdp registers into adev struct

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  8 ++++++++
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 23 +++++++++++++++++++++++
 4 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..40c3ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -642,6 +642,13 @@ struct nbio_hdp_flush_reg {
 	u32 ref_and_mask_sdma1;
 };
 
+struct remapped_hdp_reg {
+	u32 remapped_hdp_mem_flush_cntl_reg_offset;
+	u32 remapped_hdp_reg_flush_cntl_reg_offset;
+	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
+	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
+};
+
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -939,6 +946,7 @@ struct amdgpu_device {
 	struct work_struct		xgmi_reset_work;
 
 	bool                            in_baco_reset;
+	struct remapped_hdp_reg         remapped_hdp_reg;
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..d41e333 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..8f0a30e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..b84ef21 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -775,6 +776,27 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 	.need_reset_on_init = &soc15_need_reset_on_init,
 };
 
+static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
+{
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+	/* Remap hdp coherency registers to a hole in register space,
+	 * for the purpose of mapping them to process space(so process
+	 * can flush hdp)
+	 */
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+			MMIO_REG_HOLE_OFFSET);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+			MMIO_REG_HOLE_OFFSET+ 4);
+	adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset =
+			(MMIO_REG_HOLE_OFFSET) >> 2;
+	adev->remapped_hdp_reg.remapped_hdp_reg_flush_cntl_reg_offset =
+			(MMIO_REG_HOLE_OFFSET + 4) >> 2;
+	adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_physical_addr =
+			adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+	adev->remapped_hdp_reg.remapped_hdp_reg_flush_cntl_physical_addr =
+			adev->rmmio_base + MMIO_REG_HOLE_OFFSET + 4;
+}
+
 static int soc15_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -794,6 +816,7 @@ static int soc15_common_early_init(void *handle)
 
 
 	adev->external_rev_id = 0xFF;
+	soc15_remap_hdp_coherency_registers(adev);
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		adev->asic_funcs = &soc15_asic_funcs;
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Kuehling, Felix]

On 2019-04-17 10:20 a.m., Zeng, Oak wrote:
> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
> to an empty page in mmio space. We will later map this page to process
> space so application can flush hdp. This can't be done properly at
> those registers' original location because it will expose more than
> desired registers to process space.
>
> v2: Use explicit register hole location
> v3: Moved remapped hdp registers into adev struct
>
> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  8 ++++++++
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  5 ++---
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 ++---
>   drivers/gpu/drm/amd/amdgpu/soc15.c     | 23 +++++++++++++++++++++++
>   4 files changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bc96ec4..40c3ba6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -642,6 +642,13 @@ struct nbio_hdp_flush_reg {
>   	u32 ref_and_mask_sdma1;
>   };
>   
> +struct remapped_hdp_reg {
> +	u32 remapped_hdp_mem_flush_cntl_reg_offset;
> +	u32 remapped_hdp_reg_flush_cntl_reg_offset;
I think the offsets or indexes of the remapped register inside the 
remapped MMIO page should not be variable. We need an agreed convention 
between user mode and kernel mode, which register is mapped where. This 
will be part of the driver ABI that must be maintained for backwards 
compatibility. This should probably be defined in 
include/uapi/linux/kfd_ioctl.h as an enum or #define.


> +	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
> +	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
> +};

The variable names are a bit verbose.

Alex suggested in patch 2 to use a more generic name for the buffer 
type. Maybe a more generic name makes sense here too for any future mmio 
remappings. Maybe struct amdgpu_mmio_remap.

I don't think we need both the offset and the physical address. I don't 
see that we need the physical address of each remapped register. Your 
patch 2 only needs the physical address of the first remapped register, 
for the start address of the remapped MMIO page. So instead of adding 
the physical address of each register just add one member phys_addr (or 
bus_addr) that is the bus address of the remapped MMIO page.


> +
>   struct amdgpu_nbio_funcs {
>   	const struct nbio_hdp_flush_reg *hdp_flush_reg;
>   	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
> @@ -939,6 +946,7 @@ struct amdgpu_device {
>   	struct work_struct		xgmi_reset_work;
>   
>   	bool                            in_baco_reset;
> +	struct remapped_hdp_reg         remapped_hdp_reg;

Move this to just after the other mmio members in struct amdgpu_device 
and give it a more generic name like adev->rmmio_remap.


>   };
>   
>   static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98a..d41e333 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index c69d515..8f0a30e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bdb5ad9..b84ef21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -44,6 +44,7 @@
>   #include "smuio/smuio_9_0_offset.h"
>   #include "smuio/smuio_9_0_sh_mask.h"
>   #include "nbio/nbio_7_0_default.h"
> +#include "nbio/nbio_7_0_offset.h"
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "mp/mp_9_0_offset.h"
> @@ -775,6 +776,27 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>   	.need_reset_on_init = &soc15_need_reset_on_init,
>   };
>   
> +static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
> +{
> +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)

This definition and the initialization of adev->rmmio_remap.bus_addr 
would belong in soc15.c or an ASIC-specific file, not an IP-specific 
file. The code below should only use adev->rmmio_remap and the offset 
definitions from kfd_ioctl.h to program the IP-specific remapping registers.

Regards,
   Felix

> +	/* Remap hdp coherency registers to a hole in register space,
> +	 * for the purpose of mapping them to process space(so process
> +	 * can flush hdp)
> +	 */
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +			MMIO_REG_HOLE_OFFSET);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +			MMIO_REG_HOLE_OFFSET+ 4);
> +	adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_reg_offset =
> +			(MMIO_REG_HOLE_OFFSET) >> 2;
> +	adev->remapped_hdp_reg.remapped_hdp_reg_flush_cntl_reg_offset =
> +			(MMIO_REG_HOLE_OFFSET + 4) >> 2;
> +	adev->remapped_hdp_reg.remapped_hdp_mem_flush_cntl_physical_addr =
> +			adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
> +	adev->remapped_hdp_reg.remapped_hdp_reg_flush_cntl_physical_addr =
> +			adev->rmmio_base + MMIO_REG_HOLE_OFFSET + 4;
> +}
> +
>   static int soc15_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -794,6 +816,7 @@ static int soc15_common_early_init(void *handle)
>   
>   
>   	adev->external_rev_id = 0xFF;
> +	soc15_remap_hdp_coherency_registers(adev);
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
>   		adev->asic_funcs = &soc15_asic_funcs;
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[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

v2: Use explicit register hole location

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 23 +++++++++++++++++++++++
 8 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..840be05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
 
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
+	u32 remapped_hdp_mem_flush_cntl_reg_offset;
+	u32 remapped_hdp_reg_flush_cntl_reg_offset;
+	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
+	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
 	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
 	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
@@ -905,7 +909,7 @@ struct amdgpu_device {
 	/* soc15 register offset based on ip, instance and  segment */
 	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
-	const struct amdgpu_nbio_funcs	*nbio_funcs;
+	struct amdgpu_nbio_funcs	*nbio_funcs;
 	const struct amdgpu_df_funcs	*df_funcs;
 
 	/* delayed work_func for deferring clockgating during resume */
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 6590143..2470b8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
-const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
 	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index 0743a6f..d409bb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
+extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..9a5abf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
@@ -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 
 }
 
-const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
index 508d549..db50618 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
+extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..25203cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
@@ -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
-const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
index c442865..2e5bb03 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
+extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..9c575a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -775,6 +776,27 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 	.need_reset_on_init = &soc15_need_reset_on_init,
 };
 
+static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
+{
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+	/* Remap hdp coherency registers to a hole in register space,
+	 * for the purpose of mapping them to process space(so process
+	 * can flush hdp)
+	 */
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+			MMIO_REG_HOLE_OFFSET);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+			MMIO_REG_HOLE_OFFSET+ 4);
+	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
+			(MMIO_REG_HOLE_OFFSET) >> 2;
+	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
+			(MMIO_REG_HOLE_OFFSET + 4) >> 2;
+	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
+			adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
+			adev->rmmio_base + MMIO_REG_HOLE_OFFSET + 4;
+}
+
 static int soc15_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -794,6 +816,7 @@ static int soc15_common_early_init(void *handle)
 
 
 	adev->external_rev_id = 0xFF;
+	soc15_remap_hdp_coherency_registers(adev);
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		adev->asic_funcs = &soc15_asic_funcs;
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to process space.

Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c     | 22 ++++++++++++++++++++++
 8 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bc96ec4..840be05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
 
 struct amdgpu_nbio_funcs {
 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
+	u32 remapped_hdp_mem_flush_cntl_reg_offset;
+	u32 remapped_hdp_reg_flush_cntl_reg_offset;
+	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
+	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
 	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
 	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
@@ -905,7 +909,7 @@ struct amdgpu_device {
 	/* soc15 register offset based on ip, instance and  segment */
 	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
-	const struct amdgpu_nbio_funcs	*nbio_funcs;
+	struct amdgpu_nbio_funcs	*nbio_funcs;
 	const struct amdgpu_df_funcs	*df_funcs;
 
 	/* delayed work_func for deferring clockgating during resume */
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 6590143..2470b8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
-const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
 	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index 0743a6f..d409bb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
+extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98a..9a5abf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
@@ -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 
 }
 
-const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
index 508d549..db50618 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
+extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index c69d515..25203cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
 	if (!ring || !ring->funcs->emit_wreg)
-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 	else
-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
 }
 
 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
@@ -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
-const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
index c442865..2e5bb03 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
@@ -26,6 +26,6 @@
 
 #include "soc15_common.h"
 
-extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
+extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bdb5ad9..c47e7a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -44,6 +44,7 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
 #include "nbio/nbio_7_0_smn.h"
 #include "mp/mp_9_0_offset.h"
@@ -775,6 +776,26 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
 	.need_reset_on_init = &soc15_need_reset_on_init,
 };
 
+static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
+{
+	/* Remap hdp coherency registers to the last page of mmio
+	 * space, for the purpose of mapping them to process space(
+	 * so process can flush hdp)
+	 */
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+			adev->rmmio_size - PAGE_SIZE);
+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+			adev->rmmio_size - PAGE_SIZE + 4);
+	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
+			(adev->rmmio_size - PAGE_SIZE) >> 2;
+	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
+			(adev->rmmio_size - PAGE_SIZE + 4) >> 2;
+	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
+			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE;
+	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
+			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE + 4;
+}
+
 static int soc15_common_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -794,6 +815,7 @@ static int soc15_common_early_init(void *handle)
 
 
 	adev->external_rev_id = 0xFF;
+	soc15_remap_hdp_coherency_registers(adev);
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		adev->asic_funcs = &soc15_asic_funcs;
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Christian König]

Am 11.04.19 um 22:31 schrieb Zeng, Oak:
> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
> to an empty page in mmio space. We will later map this page to process
> space so application can flush hdp. This can't be done properly at
> those registers' original location because it will expose more than
> desired registers to process space.
>
> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/soc15.c     | 22 ++++++++++++++++++++++
>   8 files changed, 37 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bc96ec4..840be05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
>   
>   struct amdgpu_nbio_funcs {
>   	const struct nbio_hdp_flush_reg *hdp_flush_reg;
> +	u32 remapped_hdp_mem_flush_cntl_reg_offset;
> +	u32 remapped_hdp_reg_flush_cntl_reg_offset;
> +	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
> +	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
>   	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
>   	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
>   	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
> @@ -905,7 +909,7 @@ struct amdgpu_device {
>   	/* soc15 register offset based on ip, instance and  segment */
>   	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
>   
> -	const struct amdgpu_nbio_funcs	*nbio_funcs;
> +	struct amdgpu_nbio_funcs	*nbio_funcs;

Please kep the function pointers constant. Those should never be changed 
on a running system.

Christian.

>   	const struct amdgpu_df_funcs	*df_funcs;
>   
>   	/* delayed work_func for deferring clockgating during resume */
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 6590143..2470b8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
>   		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
> +struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>   	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> index 0743a6f..d409bb6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98a..9a5abf5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> @@ -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
>   
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
> +struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>   	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> index 508d549..db50618 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index c69d515..25203cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> @@ -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
>   		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
> +struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>   	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> index c442865..2e5bb03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bdb5ad9..c47e7a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -44,6 +44,7 @@
>   #include "smuio/smuio_9_0_offset.h"
>   #include "smuio/smuio_9_0_sh_mask.h"
>   #include "nbio/nbio_7_0_default.h"
> +#include "nbio/nbio_7_0_offset.h"
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "mp/mp_9_0_offset.h"
> @@ -775,6 +776,26 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>   	.need_reset_on_init = &soc15_need_reset_on_init,
>   };
>   
> +static void soc15_remap_hdp_coherency_registers(struct amdgpu_device *adev)
> +{
> +	/* Remap hdp coherency registers to the last page of mmio
> +	 * space, for the purpose of mapping them to process space(
> +	 * so process can flush hdp)
> +	 */
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +			adev->rmmio_size - PAGE_SIZE);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +			adev->rmmio_size - PAGE_SIZE + 4);
> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
> +			(adev->rmmio_size - PAGE_SIZE) >> 2;
> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
> +			(adev->rmmio_size - PAGE_SIZE + 4) >> 2;
> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE;
> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE + 4;
> +}
> +
>   static int soc15_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -794,6 +815,7 @@ static int soc15_common_early_init(void *handle)
>   
>   
>   	adev->external_rev_id = 0xFF;
> +	soc15_remap_hdp_coherency_registers(adev);
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
>   		adev->asic_funcs = &soc15_asic_funcs;

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RE: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Hi Christian,

After hdp registers are moved to a new place in mmio space, we can't access those registers through the pre-defined register offset. I recorded the new register offset in struct amdgpu_nbio_funcs (because those registers are nbio registers) and initialized them in the early init. After those changes, I can't keep instance of struct amdgpu_nbio_funcs to be constant anymore - we don't know the new register offset before the remap function. When I made the change, I also felt not comfortable. Do you have any better solution? Introduce new r/w members directly to adev? - I also feel not comfortable because those registers I added belongs to nbio by nature...

Regards,
Oak

-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@gmail.com> 
Sent: Friday, April 12, 2019 3:24 AM
To: Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Kuehling, Felix <Felix.Kuehling@amd.com>; Keely, Sean <Sean.Keely@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

Am 11.04.19 um 22:31 schrieb Zeng, Oak:
> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to 
> an empty page in mmio space. We will later map this page to process 
> space so application can flush hdp. This can't be done properly at 
> those registers' original location because it will expose more than 
> desired registers to process space.
>
> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
>   drivers/gpu/drm/amd/amdgpu/soc15.c     | 22 ++++++++++++++++++++++
>   8 files changed, 37 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bc96ec4..840be05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
>   
>   struct amdgpu_nbio_funcs {
>   	const struct nbio_hdp_flush_reg *hdp_flush_reg;
> +	u32 remapped_hdp_mem_flush_cntl_reg_offset;
> +	u32 remapped_hdp_reg_flush_cntl_reg_offset;
> +	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
> +	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
>   	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
>   	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
>   	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); @@ -905,7 
> +909,7 @@ struct amdgpu_device {
>   	/* soc15 register offset based on ip, instance and  segment */
>   	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
>   
> -	const struct amdgpu_nbio_funcs	*nbio_funcs;
> +	struct amdgpu_nbio_funcs	*nbio_funcs;

Please kep the function pointers constant. Those should never be changed on a running system.

Christian.

>   	const struct amdgpu_df_funcs	*df_funcs;
>   
>   	/* delayed work_func for deferring clockgating during resume */ 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 6590143..2470b8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
>   		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
> +struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>   	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> index 0743a6f..d409bb6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98a..9a5abf5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		
> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offse
> +t, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, 
> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) @@ 
> -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct 
> amdgpu_device *adev)
>   
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
> +struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>   	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> index 508d549..db50618 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index c69d515..25203cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>   				struct amdgpu_ring *ring)
>   {
>   	if (!ring || !ring->funcs->emit_wreg)
> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +		
> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offse
> +t, 0);
>   	else
> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
> +		amdgpu_ring_emit_wreg(ring, 
> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>   }
>   
>   static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) @@ 
> -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
>   		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>   }
>   
> -const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
> +struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>   	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
>   	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
>   	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> index c442865..2e5bb03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
> @@ -26,6 +26,6 @@
>   
>   #include "soc15_common.h"
>   
> -extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
> +extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bdb5ad9..c47e7a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -44,6 +44,7 @@
>   #include "smuio/smuio_9_0_offset.h"
>   #include "smuio/smuio_9_0_sh_mask.h"
>   #include "nbio/nbio_7_0_default.h"
> +#include "nbio/nbio_7_0_offset.h"
>   #include "nbio/nbio_7_0_sh_mask.h"
>   #include "nbio/nbio_7_0_smn.h"
>   #include "mp/mp_9_0_offset.h"
> @@ -775,6 +776,26 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>   	.need_reset_on_init = &soc15_need_reset_on_init,
>   };
>   
> +static void soc15_remap_hdp_coherency_registers(struct amdgpu_device 
> +*adev) {
> +	/* Remap hdp coherency registers to the last page of mmio
> +	 * space, for the purpose of mapping them to process space(
> +	 * so process can flush hdp)
> +	 */
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> +			adev->rmmio_size - PAGE_SIZE);
> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> +			adev->rmmio_size - PAGE_SIZE + 4);
> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
> +			(adev->rmmio_size - PAGE_SIZE) >> 2;
> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
> +			(adev->rmmio_size - PAGE_SIZE + 4) >> 2;
> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE;
> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE + 4; }
> +
>   static int soc15_common_early_init(void *handle)
>   {
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ 
> -794,6 +815,7 @@ static int soc15_common_early_init(void *handle)
>   
>   
>   	adev->external_rev_id = 0xFF;
> +	soc15_remap_hdp_coherency_registers(adev);
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
>   		adev->asic_funcs = &soc15_asic_funcs;

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Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Koenig, Christian]

Hi Oak,

well, we make the function pointer structures constant is exactly to 
prevent those scenarios.

Background is that multiple GPU can use the same function pointer 
structure, but with different register offsets. So what you do here is 
actually illegal and could break in some cases.

Easiest solution would indeed be to add a new stuff directly to the 
adev, probably best encapsulated in a new structure.

Regards,
Christian.

Am 12.04.19 um 17:39 schrieb Zeng, Oak:
> Hi Christian,
>
> After hdp registers are moved to a new place in mmio space, we can't access those registers through the pre-defined register offset. I recorded the new register offset in struct amdgpu_nbio_funcs (because those registers are nbio registers) and initialized them in the early init. After those changes, I can't keep instance of struct amdgpu_nbio_funcs to be constant anymore - we don't know the new register offset before the remap function. When I made the change, I also felt not comfortable. Do you have any better solution? Introduce new r/w members directly to adev? - I also feel not comfortable because those registers I added belongs to nbio by nature...
>
> Regards,
> Oak
>
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken@gmail.com>
> Sent: Friday, April 12, 2019 3:24 AM
> To: Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Kuehling, Felix <Felix.Kuehling@amd.com>; Keely, Sean <Sean.Keely@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers
>
> Am 11.04.19 um 22:31 schrieb Zeng, Oak:
>> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to
>> an empty page in mmio space. We will later map this page to process
>> space so application can flush hdp. This can't be done properly at
>> those registers' original location because it will expose more than
>> desired registers to process space.
>>
>> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
>> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/soc15.c     | 22 ++++++++++++++++++++++
>>    8 files changed, 37 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index bc96ec4..840be05 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
>>    
>>    struct amdgpu_nbio_funcs {
>>    	const struct nbio_hdp_flush_reg *hdp_flush_reg;
>> +	u32 remapped_hdp_mem_flush_cntl_reg_offset;
>> +	u32 remapped_hdp_reg_flush_cntl_reg_offset;
>> +	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
>> +	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
>>    	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
>>    	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
>>    	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); @@ -905,7
>> +909,7 @@ struct amdgpu_device {
>>    	/* soc15 register offset based on ip, instance and  segment */
>>    	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
>>    
>> -	const struct amdgpu_nbio_funcs	*nbio_funcs;
>> +	struct amdgpu_nbio_funcs	*nbio_funcs;
> Please kep the function pointers constant. Those should never be changed on a running system.
>
> Christian.
>
>>    	const struct amdgpu_df_funcs	*df_funcs;
>>    
>>    	/* delayed work_func for deferring clockgating during resume */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 6590143..2470b8e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
>>    		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>>    	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> index 0743a6f..d409bb6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> index 1cdb98a..9a5abf5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> @@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>>    				struct amdgpu_ring *ring)
>>    {
>>    	if (!ring || !ring->funcs->emit_wreg)
>> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +		
>> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offse
>> +t, 0);
>>    	else
>> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
>> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
>> +		amdgpu_ring_emit_wreg(ring,
>> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>>    }
>>    
>>    static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) @@
>> -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct
>> amdgpu_device *adev)
>>    
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>>    	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> index 508d549..db50618 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> index c69d515..25203cc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> @@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>>    				struct amdgpu_ring *ring)
>>    {
>>    	if (!ring || !ring->funcs->emit_wreg)
>> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +		
>> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offse
>> +t, 0);
>>    	else
>> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
>> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
>> +		amdgpu_ring_emit_wreg(ring,
>> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>>    }
>>    
>>    static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) @@
>> -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
>>    		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>>    	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> index c442865..2e5bb03 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index bdb5ad9..c47e7a5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -44,6 +44,7 @@
>>    #include "smuio/smuio_9_0_offset.h"
>>    #include "smuio/smuio_9_0_sh_mask.h"
>>    #include "nbio/nbio_7_0_default.h"
>> +#include "nbio/nbio_7_0_offset.h"
>>    #include "nbio/nbio_7_0_sh_mask.h"
>>    #include "nbio/nbio_7_0_smn.h"
>>    #include "mp/mp_9_0_offset.h"
>> @@ -775,6 +776,26 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>>    	.need_reset_on_init = &soc15_need_reset_on_init,
>>    };
>>    
>> +static void soc15_remap_hdp_coherency_registers(struct amdgpu_device
>> +*adev) {
>> +	/* Remap hdp coherency registers to the last page of mmio
>> +	 * space, for the purpose of mapping them to process space(
>> +	 * so process can flush hdp)
>> +	 */
>> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
>> +			adev->rmmio_size - PAGE_SIZE);
>> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
>> +			adev->rmmio_size - PAGE_SIZE + 4);
>> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
>> +			(adev->rmmio_size - PAGE_SIZE) >> 2;
>> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
>> +			(adev->rmmio_size - PAGE_SIZE + 4) >> 2;
>> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
>> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE;
>> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
>> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE + 4; }
>> +
>>    static int soc15_common_early_init(void *handle)
>>    {
>>    	struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@
>> -794,6 +815,7 @@ static int soc15_common_early_init(void *handle)
>>    
>>    
>>    	adev->external_rev_id = 0xFF;
>> +	soc15_remap_hdp_coherency_registers(adev);
>>    	switch (adev->asic_type) {
>>    	case CHIP_VEGA10:
>>    		adev->asic_funcs = &soc15_asic_funcs;

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RE: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

[Zeng, Oak]

Ok, will do it.

Regards,
Oak

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Koenig, Christian
Sent: Monday, April 15, 2019 4:06 AM
To: Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Kuehling, Felix <Felix.Kuehling@amd.com>; Keely, Sean <Sean.Keely@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers

Hi Oak,

well, we make the function pointer structures constant is exactly to prevent those scenarios.

Background is that multiple GPU can use the same function pointer structure, but with different register offsets. So what you do here is actually illegal and could break in some cases.

Easiest solution would indeed be to add a new stuff directly to the adev, probably best encapsulated in a new structure.

Regards,
Christian.

Am 12.04.19 um 17:39 schrieb Zeng, Oak:
> Hi Christian,
>
> After hdp registers are moved to a new place in mmio space, we can't access those registers through the pre-defined register offset. I recorded the new register offset in struct amdgpu_nbio_funcs (because those registers are nbio registers) and initialized them in the early init. After those changes, I can't keep instance of struct amdgpu_nbio_funcs to be constant anymore - we don't know the new register offset before the remap function. When I made the change, I also felt not comfortable. Do you have any better solution? Introduce new r/w members directly to adev? - I also feel not comfortable because those registers I added belongs to nbio by nature...
>
> Regards,
> Oak
>
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken@gmail.com>
> Sent: Friday, April 12, 2019 3:24 AM
> To: Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Kuehling, Felix 
> <Felix.Kuehling@amd.com>; Keely, Sean <Sean.Keely@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdgpu: Remap hdp coherency registers
>
> Am 11.04.19 um 22:31 schrieb Zeng, Oak:
>> Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL 
>> to an empty page in mmio space. We will later map this page to 
>> process space so application can flush hdp. This can't be done 
>> properly at those registers' original location because it will expose 
>> more than desired registers to process space.
>>
>> Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
>> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++++-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  7 +++----
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  7 +++----
>>    drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h |  2 +-
>>    drivers/gpu/drm/amd/amdgpu/soc15.c     | 22 ++++++++++++++++++++++
>>    8 files changed, 37 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index bc96ec4..840be05 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -644,6 +644,10 @@ struct nbio_hdp_flush_reg {
>>    
>>    struct amdgpu_nbio_funcs {
>>    	const struct nbio_hdp_flush_reg *hdp_flush_reg;
>> +	u32 remapped_hdp_mem_flush_cntl_reg_offset;
>> +	u32 remapped_hdp_reg_flush_cntl_reg_offset;
>> +	resource_size_t remapped_hdp_mem_flush_cntl_physical_addr;
>> +	resource_size_t remapped_hdp_reg_flush_cntl_physical_addr;
>>    	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
>>    	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
>>    	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); @@ 
>> -905,7
>> +909,7 @@ struct amdgpu_device {
>>    	/* soc15 register offset based on ip, instance and  segment */
>>    	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
>>    
>> -	const struct amdgpu_nbio_funcs	*nbio_funcs;
>> +	struct amdgpu_nbio_funcs	*nbio_funcs;
> Please kep the function pointers constant. Those should never be changed on a running system.
>
> Christian.
>
>>    	const struct amdgpu_df_funcs	*df_funcs;
>>    
>>    	/* delayed work_func for deferring clockgating during resume */ 
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 6590143..2470b8e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -276,7 +276,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
>>    		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
>>    	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> index 0743a6f..d409bb6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v6_1_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> index 1cdb98a..9a5abf5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> @@ -55,10 +55,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
>>    				struct amdgpu_ring *ring)
>>    {
>>    	if (!ring || !ring->funcs->emit_wreg)
>> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +		
>> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offs
>> +e
>> +t, 0);
>>    	else
>> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
>> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
>> +		amdgpu_ring_emit_wreg(ring,
>> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>>    }
>>    
>>    static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) @@
>> -263,7 +262,7 @@ static void nbio_v7_0_init_registers(struct 
>> amdgpu_device *adev)
>>    
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
>>    	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> index 508d549..db50618 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v7_0_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> index c69d515..25203cc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> @@ -53,10 +53,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
>>    				struct amdgpu_ring *ring)
>>    {
>>    	if (!ring || !ring->funcs->emit_wreg)
>> -		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +		
>> +WREG32_NO_KIQ(adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offs
>> +e
>> +t, 0);
>>    	else
>> -		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
>> -			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
>> +		amdgpu_ring_emit_wreg(ring,
>> +adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset, 0);
>>    }
>>    
>>    static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) @@
>> -242,7 +241,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
>>    		WREG32_PCIE(smnPCIE_CI_CNTL, data);
>>    }
>>    
>> -const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>> +struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
>>    	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
>>    	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
>>    	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> index c442865..2e5bb03 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
>> @@ -26,6 +26,6 @@
>>    
>>    #include "soc15_common.h"
>>    
>> -extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>> +extern struct amdgpu_nbio_funcs nbio_v7_4_funcs;
>>    
>>    #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index bdb5ad9..c47e7a5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -44,6 +44,7 @@
>>    #include "smuio/smuio_9_0_offset.h"
>>    #include "smuio/smuio_9_0_sh_mask.h"
>>    #include "nbio/nbio_7_0_default.h"
>> +#include "nbio/nbio_7_0_offset.h"
>>    #include "nbio/nbio_7_0_sh_mask.h"
>>    #include "nbio/nbio_7_0_smn.h"
>>    #include "mp/mp_9_0_offset.h"
>> @@ -775,6 +776,26 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
>>    	.need_reset_on_init = &soc15_need_reset_on_init,
>>    };
>>    
>> +static void soc15_remap_hdp_coherency_registers(struct amdgpu_device
>> +*adev) {
>> +	/* Remap hdp coherency registers to the last page of mmio
>> +	 * space, for the purpose of mapping them to process space(
>> +	 * so process can flush hdp)
>> +	 */
>> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
>> +			adev->rmmio_size - PAGE_SIZE);
>> +	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
>> +			adev->rmmio_size - PAGE_SIZE + 4);
>> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_reg_offset =
>> +			(adev->rmmio_size - PAGE_SIZE) >> 2;
>> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_reg_offset =
>> +			(adev->rmmio_size - PAGE_SIZE + 4) >> 2;
>> +	adev->nbio_funcs->remapped_hdp_mem_flush_cntl_physical_addr =
>> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE;
>> +	adev->nbio_funcs->remapped_hdp_reg_flush_cntl_physical_addr =
>> +			adev->rmmio_base + adev->rmmio_size - PAGE_SIZE + 4; }
>> +
>>    static int soc15_common_early_init(void *handle)
>>    {
>>    	struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@
>> -794,6 +815,7 @@ static int soc15_common_early_init(void *handle)
>>    
>>    
>>    	adev->external_rev_id = 0xFF;
>> +	soc15_remap_hdp_coherency_registers(adev);
>>    	switch (adev->asic_type) {
>>    	case CHIP_VEGA10:
>>    		adev->asic_funcs = &soc15_asic_funcs;

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