[PATCH] drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE

[PATCH] drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE

[wentalou]

amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov.
but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled.
set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working.

Change-Id: I7d13ed35469ebd7bdf10c90341181977c6cfd38d
Signed-off-by: Wentao Lou <Wentao.Lou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 1ec60f5..1be85b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -851,7 +851,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 				       SDMA0_GFX_RB_WPTR_POLL_CNTL,
-				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 
 	/* enable DMA RB */
@@ -942,7 +942,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 				       SDMA0_PAGE_RB_WPTR_POLL_CNTL,
-				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 
 	/* enable DMA RB */
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE

[Deucher, Alexander]

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Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

Please fix up your mail client or git config so your email address matches your signed off line.  E.g.,
wentalou <Wentao.Lou-5C7GfCeVMHo@public.gmane.org>
vs.
Wentao Lou <Wentao.Lou-5C7GfCeVMHo@public.gmane.org>

Thanks,

Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of wentalou <Wentao.Lou-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, April 25, 2019 12:50 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Lou, Wentao
Subject: [PATCH] drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE

amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov.
but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled.
set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working.

Change-Id: I7d13ed35469ebd7bdf10c90341181977c6cfd38d
Signed-off-by: Wentao Lou <Wentao.Lou-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 1ec60f5..1be85b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -851,7 +851,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
-                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);

         /* enable DMA RB */
@@ -942,7 +942,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
-                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
+                                      F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);

         /* enable DMA RB */
--
2.7.4

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