* [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM
@ 2019-05-03 6:27 Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only Ley Foon Tan
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Ley Foon Tan @ 2019-05-03 6:27 UTC (permalink / raw)
To: u-boot
Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM.
v3 -> v4:
- Add CONFIG_SPL_ALTERA_SDRAM to config_whitelist.txt in patch [1/3] and remove it in patch [3/3]
- Remove _remove().
- Update commit message in patch [2/3]
v2->v3:
-------
- Compile ALTERA_SDRAM driver in SPL only
- Separate dts change to new patch
- Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- Add _remove()
- Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c
History:
--------
[v1]: https://patchwork.ozlabs.org/patch/1066765/
[v2]: https://patchwork.ozlabs.org/patch/1089957/
[v3]: https://patchwork.ozlabs.org/cover/1093091/
Ley Foon Tan (3):
ddr: altera: Compile ALTERA SDRAM in SPL only
arm: dts: Stratix10: Add SDRAM node
arm: socfpga: Move Stratix 10 SDRAM driver to DM
Makefile | 2 +-
arch/arm/dts/socfpga_stratix10.dtsi | 9 +
arch/arm/mach-socfpga/Kconfig | 4 +-
arch/arm/mach-socfpga/spl_s10.c | 16 +-
configs/socfpga_stratix10_defconfig | 1 +
drivers/Makefile | 2 +-
drivers/ddr/altera/Kconfig | 11 +-
drivers/ddr/altera/Makefile | 2 +-
drivers/ddr/altera/sdram_s10.c | 243 ++++++++++++------
.../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
include/configs/socfpga_stratix10_socdk.h | 5 -
11 files changed, 200 insertions(+), 99 deletions(-)
rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%)
--
2.19.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only
2019-05-03 6:27 [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM Ley Foon Tan
@ 2019-05-03 6:27 ` Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 2/3] arm: dts: Stratix10: Add SDRAM node Ley Foon Tan
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Ley Foon Tan @ 2019-05-03 6:27 UTC (permalink / raw)
To: u-boot
Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
Makefile | 2 +-
arch/arm/mach-socfpga/Kconfig | 4 ++--
drivers/Makefile | 2 +-
drivers/ddr/altera/Kconfig | 5 +++--
drivers/ddr/altera/Makefile | 2 +-
include/configs/socfpga_stratix10_socdk.h | 2 +-
scripts/config_whitelist.txt | 1 +
7 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/Makefile b/Makefile
index 66a09ac900..53c7709d22 100644
--- a/Makefile
+++ b/Makefile
@@ -713,7 +713,7 @@ libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
-libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
+libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5e87371f8c..d4d878d3be 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -9,7 +9,7 @@ config TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_ARRIA10
bool
- select ALTERA_SDRAM
+ select SPL_ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
select CLK
select SPL_CLK if SPL
@@ -28,7 +28,7 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
- select ALTERA_SDRAM
+ select SPL_ALTERA_SDRAM
config TARGET_SOCFPGA_STRATIX10
bool
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..e501ae8d04 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
-obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
+obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 8f60b56eb8..83c1ab5e07 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,6 @@
-config ALTERA_SDRAM
- bool "SoCFPGA DDR SDRAM driver"
+config SPL_ALTERA_SDRAM
+ bool "SoCFPGA DDR SDRAM driver in SPL"
+ depends on SPL
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select RAM if TARGET_SOCFPGA_GEN5
select SPL_RAM if TARGET_SOCFPGA_GEN5
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 3615b617ec..341ac0d73b 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -6,7 +6,7 @@
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
# Copyright (C) 2014 Altera Corporation <www.altera.com>
-ifdef CONFIG_ALTERA_SDRAM
+ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 31c267f55d..9d1bc8e8d5 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -132,7 +132,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/*
* SDRAM controller
*/
-#define CONFIG_ALTERA_SDRAM
+#define CONFIG_SPL_ALTERA_SDRAM
/*
* Serial / UART configurations
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 421362d953..f0c755fc83 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1826,6 +1826,7 @@ CONFIG_SPLASH_SCREEN_ALIGN
CONFIG_SPLASH_SOURCE
CONFIG_SPLL_FREQ
CONFIG_SPL_
+CONFIG_SPL_ALTERA_SDRAM
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_BOOTROM_SAVE
--
2.19.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 2/3] arm: dts: Stratix10: Add SDRAM node
2019-05-03 6:27 [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only Ley Foon Tan
@ 2019-05-03 6:27 ` Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 3/3] arm: socfpga: Move Stratix 10 SDRAM driver to DM Ley Foon Tan
2019-05-03 15:13 ` [U-Boot] [PATCH v4 0/3] " Marek Vasut
3 siblings, 0 replies; 7+ messages in thread
From: Ley Foon Tan @ 2019-05-03 6:27 UTC (permalink / raw)
To: u-boot
Add SDRAM device tree node.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/dts/socfpga_stratix10.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index d1ae2fabae..bd68a78a37 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -258,6 +258,15 @@
u-boot,dm-pre-reloc;
};
+ sdr: sdr at f8000400 {
+ compatible = "altr,sdr-ctl-s10";
+ reg = <0xf8000400 0x80>,
+ <0xf8010000 0x190>,
+ <0xf8011000 0x500>;
+ resets = <&rst DDRSCH_RESET>;
+ u-boot,dm-pre-reloc;
+ };
+
spi0: spi at ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
--
2.19.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 3/3] arm: socfpga: Move Stratix 10 SDRAM driver to DM
2019-05-03 6:27 [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 2/3] arm: dts: Stratix10: Add SDRAM node Ley Foon Tan
@ 2019-05-03 6:27 ` Ley Foon Tan
2019-05-03 15:13 ` [U-Boot] [PATCH v4 0/3] " Marek Vasut
3 siblings, 0 replies; 7+ messages in thread
From: Ley Foon Tan @ 2019-05-03 6:27 UTC (permalink / raw)
To: u-boot
Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/spl_s10.c | 16 +-
configs/socfpga_stratix10_defconfig | 1 +
drivers/ddr/altera/Kconfig | 6 +-
drivers/ddr/altera/sdram_s10.c | 243 ++++++++++++------
.../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
include/configs/socfpga_stratix10_socdk.h | 5 -
scripts/config_whitelist.txt | 1 -
7 files changed, 183 insertions(+), 93 deletions(-)
rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a141ffe82a..ec65e1ce64 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -15,9 +15,9 @@
#include <asm/arch/firewall_s10.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/reset_manager.h>
-#include <asm/arch/sdram_s10.h>
#include <asm/arch/system_manager.h>
#include <watchdog.h>
+#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -175,11 +175,15 @@ void board_init_f(ulong dummy)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- debug("DDR: Initializing Hard Memory Controller\n");
- if (sdram_mmr_init_full(0)) {
- puts("DDR: Initialization failed.\n");
- hang();
- }
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+ struct udevice *dev;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ hang();
+ }
+#endif
mbox_init();
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 4848013b21..c85a0f785a 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 83c1ab5e07..2b1c1be3b5 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL
- depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select RAM if TARGET_SOCFPGA_GEN5
- select SPL_RAM if TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
+ select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+ select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index e4d4a02ca2..56cbbac9fe 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -5,17 +5,31 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <div64.h>
#include <fdtdec.h>
-#include <asm/io.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_s10.h"
#include <wait_bit.h>
#include <asm/arch/firewall_s10.h>
-#include <asm/arch/sdram_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
#include <linux/sizes.h>
+struct altera_sdram_priv {
+ struct ram_info info;
+ struct reset_ctl_bulk resets;
+};
+
+struct altera_sdram_platdata {
+ void __iomem *hmc;
+ void __iomem *ddr_sch;
+ void __iomem *iomhc;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_system_manager *sysmgr_regs =
@@ -51,25 +65,26 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
};
-static u32 hmc_readl(u32 reg)
+static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
+ return readl(plat->iomhc + reg);
}
-static u32 hmc_ecc_readl(u32 reg)
+static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return readl(plat->hmc + reg);
}
-static u32 hmc_ecc_writel(u32 data, u32 reg)
+static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+ u32 data, u32 reg)
{
- return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return writel(data, plat->hmc + reg);
}
-static u32 ddr_sch_writel(u32 data, u32 reg)
+static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+ u32 reg)
{
- return writel(data,
- (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
+ return writel(data, plat->ddr_sch + reg);
}
int match_ddr_conf(u32 ddr_conf)
@@ -83,37 +98,38 @@ int match_ddr_conf(u32 ddr_conf)
return 0;
}
-static int emif_clear(void)
+static int emif_clear(struct altera_sdram_platdata *plat)
{
- hmc_ecc_writel(0, RSTHANDSHAKECTRL);
+ hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
- return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ return wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
DDR_HMC_RSTHANDSHAKE_MASK,
false, 1000, false);
}
-static int emif_reset(void)
+static int emif_reset(struct altera_sdram_platdata *plat)
{
u32 c2s, s2c, ret;
- c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
- s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
+ c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
+ s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
- c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
- hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
+ c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
+ hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
+ hmc_readl(plat, DRAMSTS));
- if (s2c && emif_clear()) {
+ if (s2c && emif_clear(plat)) {
printf("DDR: emif_clear() failed\n");
return -1;
}
debug("DDR: Triggerring emif reset\n");
- hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
+ hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
/* if seq2core[3] = 0, we are good */
- ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ ret = wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
DDR_HMC_SEQ2CORE_INT_RESP_MASK,
false, 1000, false);
@@ -122,7 +138,7 @@ static int emif_reset(void)
return ret;
}
- ret = emif_clear();
+ ret = emif_clear(plat);
if (ret) {
printf("DDR: emif_clear() failed\n");
return ret;
@@ -240,13 +256,37 @@ static void sdram_size_check(bd_t *bd)
debug("DDR: SDRAM size check passed!\n");
}
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+{
+ u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+
+ phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+
+ size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
+ DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+ return size;
+}
+
/**
* sdram_mmr_init_full() - Function to initialize SDRAM MMR
*
* Initialize the SDRAM MMR.
*/
-int sdram_mmr_init_full(unsigned int unused)
+static int sdram_mmr_init_full(struct udevice *dev)
{
+ struct altera_sdram_platdata *plat = dev->platdata;
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 update_value, io48_value, ddrioctl;
u32 i;
int ret;
@@ -303,19 +343,16 @@ int sdram_mmr_init_full(unsigned int unused)
return -1;
}
- /* release DDR scheduler from reset */
- socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-
/* Try 3 times to do a calibration */
for (i = 0; i < 3; i++) {
- ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ ret = wait_for_bit_le32((const void *)(plat->hmc +
DDRCALSTAT),
DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
false);
if (!ret)
break;
- emif_reset();
+ emif_reset(plat);
}
if (ret) {
@@ -324,16 +361,16 @@ int sdram_mmr_init_full(unsigned int unused)
}
debug("DDR: Calibration success\n");
- u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
- u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
- u32 dramaddrw = hmc_readl(DRAMADDRW);
- u32 dramtim0 = hmc_readl(DRAMTIMING0);
- u32 caltim0 = hmc_readl(CALTIMING0);
- u32 caltim1 = hmc_readl(CALTIMING1);
- u32 caltim2 = hmc_readl(CALTIMING2);
- u32 caltim3 = hmc_readl(CALTIMING3);
- u32 caltim4 = hmc_readl(CALTIMING4);
- u32 caltim9 = hmc_readl(CALTIMING9);
+ u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
+ u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
+ u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+ u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
+ u32 caltim0 = hmc_readl(plat, CALTIMING0);
+ u32 caltim1 = hmc_readl(plat, CALTIMING1);
+ u32 caltim2 = hmc_readl(plat, CALTIMING2);
+ u32 caltim3 = hmc_readl(plat, CALTIMING3);
+ u32 caltim4 = hmc_readl(plat, CALTIMING4);
+ u32 caltim9 = hmc_readl(plat, CALTIMING9);
/*
* Configure the DDR IO size [0xFFCFB008]
@@ -349,12 +386,12 @@ int sdram_mmr_init_full(unsigned int unused)
* bit[9:6] = Minor Release #
* bit[14:10] = Major Release #
*/
- update_value = hmc_readl(NIOSRESERVED0);
- hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
- ddrioctl = hmc_ecc_readl(DDRIOCTRL);
+ update_value = hmc_readl(plat, NIOSRESERVED0);
+ hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
+ ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
/* enable HPS interface to HMC */
- hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
+ hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
/* Set the DDR Configuration */
io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
@@ -365,10 +402,10 @@ int sdram_mmr_init_full(unsigned int unused)
update_value = match_ddr_conf(io48_value);
if (update_value)
- ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
+ ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
/* Configure HMC dramaddrw */
- hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
+ hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
/*
* Configure DDR timing
@@ -392,7 +429,7 @@ int sdram_mmr_init_full(unsigned int unused)
CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
CALTIMING4_CFG_PCH_TO_VALID(caltim4));
- ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
+ ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
(update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
(io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
@@ -406,12 +443,12 @@ int sdram_mmr_init_full(unsigned int unused)
DDR_SCH_DDRTIMING);
/* Configure DDR mode [precharge = 0] */
- ddr_sch_writel(((ddrioctl ? 0 : 1) <<
+ ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
DDR_SCH_DDRMODE);
/* Configure the read latency */
- ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
+ ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
DDR_READ_LATENCY_DELAY,
DDR_SCH_READ_LATENCY);
@@ -419,7 +456,7 @@ int sdram_mmr_init_full(unsigned int unused)
* Configuring timing values concerning activate commands
* [FAWBANK alway 1 because always 4 bank DDR]
*/
- ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
+ ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
DDR_SCH_ACTIVATE_RRD_OFF) |
(CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
DDR_SCH_ACTIVATE_FAW_OFF) |
@@ -431,7 +468,7 @@ int sdram_mmr_init_full(unsigned int unused)
* Configuring timing values concerning device to device data bus
* ownership change
*/
- ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
+ ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
(CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
@@ -440,7 +477,7 @@ int sdram_mmr_init_full(unsigned int unused)
DDR_SCH_DEVTODEV);
/* assigning the SDRAM size */
- unsigned long long size = sdram_calculate_size();
+ unsigned long long size = sdram_calculate_size(plat);
/* If the size is invalid, use default Config size */
if (size <= 0)
hw_size = PHYS_SDRAM_1_SIZE;
@@ -462,18 +499,17 @@ int sdram_mmr_init_full(unsigned int unused)
/* Enable or disable the SDRAM ECC */
if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
- setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ setbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ clrbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
- setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
+ setbits_le32(plat->hmc + ECCCTRL2,
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
- writel(DDR_HMC_ERRINTEN_INTMASK,
- SOCFPGA_SDR_ADDRESS + ERRINTENS);
+ hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
@@ -482,39 +518,98 @@ int sdram_mmr_init_full(unsigned int unused)
if (!cpu_has_been_warmreset())
sdram_init_ecc_bits(&bd);
} else {
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ clrbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
+ clrbits_le32(plat->hmc + ECCCTRL2,
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
sdram_size_check(&bd);
+ priv->info.base = bd.bi_dram[0].start;
+ priv->info.size = gd->ram_size;
+
debug("DDR: HMC init success\n");
return 0;
}
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-phys_size_t sdram_calculate_size(void)
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
{
- u32 dramaddrw = hmc_readl(DRAMADDRW);
+ struct altera_sdram_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
- phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->ddr_sch = (void __iomem *)addr;
- size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
- DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->iomhc = (void __iomem *)addr;
- return size;
+ addr = dev_read_addr_index(dev, 2);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->hmc = (void __iomem *)addr;
+
+ return 0;
}
+
+static int altera_sdram_probe(struct udevice *dev)
+{
+ int ret;
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret) {
+ dev_err(dev, "Can't get reset: %d\n", ret);
+ return -ENODEV;
+ }
+ reset_deassert_bulk(&priv->resets);
+
+ if (sdram_mmr_init_full(dev) != 0) {
+ puts("SDRAM init failed.\n");
+ goto failed;
+ }
+
+ return 0;
+
+failed:
+ reset_release_bulk(&priv->resets);
+ return -ENODEV;
+}
+
+static int altera_sdram_get_info(struct udevice *dev,
+ struct ram_info *info)
+{
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+ info->base = priv->info.base;
+ info->size = priv->info.size;
+
+ return 0;
+}
+
+static struct ram_ops altera_sdram_ops = {
+ .get_info = altera_sdram_get_info,
+};
+
+static const struct udevice_id altera_sdram_ids[] = {
+ { .compatible = "altr,sdr-ctl-s10" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_sdram) = {
+ .name = "altr_sdr_ctl",
+ .id = UCLASS_RAM,
+ .of_match = altera_sdram_ids,
+ .ops = &altera_sdram_ops,
+ .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
+ .probe = altera_sdram_probe,
+ .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
+};
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h
similarity index 97%
rename from arch/arm/mach-socfpga/include/mach/sdram_s10.h
rename to drivers/ddr/altera/sdram_s10.h
index f39206ca1e..096c06cba2 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/drivers/ddr/altera/sdram_s10.h
@@ -7,10 +7,6 @@
#ifndef _SDRAM_S10_H_
#define _SDRAM_S10_H_
-phys_size_t sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
#define DDR_TWR 15
#define DDR_READ_LATENCY_DELAY 40
#define DDR_ACTIVATE_FAWBANK 0x1
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 9d1bc8e8d5..2af808cadf 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -129,11 +129,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
-/*
- * SDRAM controller
- */
-#define CONFIG_SPL_ALTERA_SDRAM
-
/*
* Serial / UART configurations
*/
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f0c755fc83..421362d953 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1826,7 +1826,6 @@ CONFIG_SPLASH_SCREEN_ALIGN
CONFIG_SPLASH_SOURCE
CONFIG_SPLL_FREQ
CONFIG_SPL_
-CONFIG_SPL_ALTERA_SDRAM
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_BOOTROM_SAVE
--
2.19.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM
2019-05-03 6:27 [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM Ley Foon Tan
` (2 preceding siblings ...)
2019-05-03 6:27 ` [U-Boot] [PATCH v4 3/3] arm: socfpga: Move Stratix 10 SDRAM driver to DM Ley Foon Tan
@ 2019-05-03 15:13 ` Marek Vasut
2019-05-06 1:50 ` Ley Foon Tan
3 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2019-05-03 15:13 UTC (permalink / raw)
To: u-boot
On 5/3/19 8:27 AM, Ley Foon Tan wrote:
> Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM.
>
> v3 -> v4:
> - Add CONFIG_SPL_ALTERA_SDRAM to config_whitelist.txt in patch [1/3] and remove it in patch [3/3]
> - Remove _remove().
> - Update commit message in patch [2/3]
>
> v2->v3:
> -------
> - Compile ALTERA_SDRAM driver in SPL only
> - Separate dts change to new patch
> - Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
> - Add _remove()
> - Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c
>
> History:
> --------
> [v1]: https://patchwork.ozlabs.org/patch/1066765/
> [v2]: https://patchwork.ozlabs.org/patch/1089957/
> [v3]: https://patchwork.ozlabs.org/cover/1093091/
>
> Ley Foon Tan (3):
> ddr: altera: Compile ALTERA SDRAM in SPL only
> arm: dts: Stratix10: Add SDRAM node
> arm: socfpga: Move Stratix 10 SDRAM driver to DM
>
> Makefile | 2 +-
> arch/arm/dts/socfpga_stratix10.dtsi | 9 +
> arch/arm/mach-socfpga/Kconfig | 4 +-
> arch/arm/mach-socfpga/spl_s10.c | 16 +-
> configs/socfpga_stratix10_defconfig | 1 +
> drivers/Makefile | 2 +-
> drivers/ddr/altera/Kconfig | 11 +-
> drivers/ddr/altera/Makefile | 2 +-
> drivers/ddr/altera/sdram_s10.c | 243 ++++++++++++------
> .../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
> include/configs/socfpga_stratix10_socdk.h | 5 -
> 11 files changed, 200 insertions(+), 99 deletions(-)
> rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%)
>
I wanted to pick them, but they don't apply to u-boot/master ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM
2019-05-03 15:13 ` [U-Boot] [PATCH v4 0/3] " Marek Vasut
@ 2019-05-06 1:50 ` Ley Foon Tan
2019-05-06 10:43 ` Marek Vasut
0 siblings, 1 reply; 7+ messages in thread
From: Ley Foon Tan @ 2019-05-06 1:50 UTC (permalink / raw)
To: u-boot
On Fri, May 3, 2019 at 11:13 PM Marek Vasut <marex@denx.de> wrote:
>
> On 5/3/19 8:27 AM, Ley Foon Tan wrote:
> > Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM.
> >
> > v3 -> v4:
> > - Add CONFIG_SPL_ALTERA_SDRAM to config_whitelist.txt in patch [1/3] and remove it in patch [3/3]
> > - Remove _remove().
> > - Update commit message in patch [2/3]
> >
> > v2->v3:
> > -------
> > - Compile ALTERA_SDRAM driver in SPL only
> > - Separate dts change to new patch
> > - Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
> > - Add _remove()
> > - Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c
> >
> > History:
> > --------
> > [v1]: https://patchwork.ozlabs.org/patch/1066765/
> > [v2]: https://patchwork.ozlabs.org/patch/1089957/
> > [v3]: https://patchwork.ozlabs.org/cover/1093091/
> >
> > Ley Foon Tan (3):
> > ddr: altera: Compile ALTERA SDRAM in SPL only
> > arm: dts: Stratix10: Add SDRAM node
> > arm: socfpga: Move Stratix 10 SDRAM driver to DM
> >
> > Makefile | 2 +-
> > arch/arm/dts/socfpga_stratix10.dtsi | 9 +
> > arch/arm/mach-socfpga/Kconfig | 4 +-
> > arch/arm/mach-socfpga/spl_s10.c | 16 +-
> > configs/socfpga_stratix10_defconfig | 1 +
> > drivers/Makefile | 2 +-
> > drivers/ddr/altera/Kconfig | 11 +-
> > drivers/ddr/altera/Makefile | 2 +-
> > drivers/ddr/altera/sdram_s10.c | 243 ++++++++++++------
> > .../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
> > include/configs/socfpga_stratix10_socdk.h | 5 -
> > 11 files changed, 200 insertions(+), 99 deletions(-)
> > rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%)
> >
> I wanted to pick them, but they don't apply to u-boot/master ?
I will rebase them to u-boot/master and resend again.
Thanks.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM
2019-05-06 1:50 ` Ley Foon Tan
@ 2019-05-06 10:43 ` Marek Vasut
0 siblings, 0 replies; 7+ messages in thread
From: Marek Vasut @ 2019-05-06 10:43 UTC (permalink / raw)
To: u-boot
On 5/6/19 3:50 AM, Ley Foon Tan wrote:
> On Fri, May 3, 2019 at 11:13 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 5/3/19 8:27 AM, Ley Foon Tan wrote:
>>> Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM.
>>>
>>> v3 -> v4:
>>> - Add CONFIG_SPL_ALTERA_SDRAM to config_whitelist.txt in patch [1/3] and remove it in patch [3/3]
>>> - Remove _remove().
>>> - Update commit message in patch [2/3]
>>>
>>> v2->v3:
>>> -------
>>> - Compile ALTERA_SDRAM driver in SPL only
>>> - Separate dts change to new patch
>>> - Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
>>> - Add _remove()
>>> - Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c
>>>
>>> History:
>>> --------
>>> [v1]: https://patchwork.ozlabs.org/patch/1066765/
>>> [v2]: https://patchwork.ozlabs.org/patch/1089957/
>>> [v3]: https://patchwork.ozlabs.org/cover/1093091/
>>>
>>> Ley Foon Tan (3):
>>> ddr: altera: Compile ALTERA SDRAM in SPL only
>>> arm: dts: Stratix10: Add SDRAM node
>>> arm: socfpga: Move Stratix 10 SDRAM driver to DM
>>>
>>> Makefile | 2 +-
>>> arch/arm/dts/socfpga_stratix10.dtsi | 9 +
>>> arch/arm/mach-socfpga/Kconfig | 4 +-
>>> arch/arm/mach-socfpga/spl_s10.c | 16 +-
>>> configs/socfpga_stratix10_defconfig | 1 +
>>> drivers/Makefile | 2 +-
>>> drivers/ddr/altera/Kconfig | 11 +-
>>> drivers/ddr/altera/Makefile | 2 +-
>>> drivers/ddr/altera/sdram_s10.c | 243 ++++++++++++------
>>> .../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
>>> include/configs/socfpga_stratix10_socdk.h | 5 -
>>> 11 files changed, 200 insertions(+), 99 deletions(-)
>>> rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%)
>>>
>> I wanted to pick them, but they don't apply to u-boot/master ?
> I will rebase them to u-boot/master and resend again.
Thanks!
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-05-06 10:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-03 6:27 [U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 2/3] arm: dts: Stratix10: Add SDRAM node Ley Foon Tan
2019-05-03 6:27 ` [U-Boot] [PATCH v4 3/3] arm: socfpga: Move Stratix 10 SDRAM driver to DM Ley Foon Tan
2019-05-03 15:13 ` [U-Boot] [PATCH v4 0/3] " Marek Vasut
2019-05-06 1:50 ` Ley Foon Tan
2019-05-06 10:43 ` Marek Vasut
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