[clk:clk-sifive-fu540 3/3] drivers/clk/sifive/fu540-prci.c:534:41-42: WARNING: Use ARRAY_SIZE

* [clk:clk-sifive-fu540 3/3] drivers/clk/sifive/fu540-prci.c:534:41-42: WARNING: Use ARRAY_SIZE
@ 2019-05-03  8:21 ` kbuild test robot
  0 siblings, 0 replies; 6+ messages in thread
From: kbuild test robot @ 2019-05-03  8:21 UTC (permalink / raw)
  To: Paul Walmsley; +Cc: kbuild-all, linux-clk, linux-arm-kernel, Stephen Boyd

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-sifive-fu540
head:   85ed1c299cca9beb5df6006361cf18bfa2305836
commit: 85ed1c299cca9beb5df6006361cf18bfa2305836 [3/3] clk: sifive: add a driver for the SiFive FU540 PRCI IP block

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>


coccinelle warnings: (new ones prefixed by >>)

>> drivers/clk/sifive/fu540-prci.c:534:41-42: WARNING: Use ARRAY_SIZE

vim +534 drivers/clk/sifive/fu540-prci.c

   508	
   509	/**
   510	 * __prci_register_clocks() - register clock controls in the PRCI with Linux
   511	 * @dev: Linux struct device *
   512	 *
   513	 * Register the list of clock controls described in __prci_init_plls[] with
   514	 * the Linux clock framework.
   515	 *
   516	 * Return: 0 upon success or a negative error code upon failure.
   517	 */
   518	static int __prci_register_clocks(struct device *dev, struct __prci_data *pd)
   519	{
   520		struct clk_init_data init;
   521		struct __prci_clock *pic;
   522		int parent_count, i, clk_hw_count, r;
   523	
   524		parent_count = of_clk_get_parent_count(dev->of_node);
   525		if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
   526			dev_err(dev, "expected only two parent clocks, found %d\n",
   527				parent_count);
   528			return -EINVAL;
   529		}
   530	
   531		memset(&init, 0, sizeof(struct clk_init_data));
   532	
   533		/* Register PLLs */
 > 534		clk_hw_count = sizeof(__prci_init_clocks) / sizeof(struct __prci_clock);
   535	
   536		for (i = 0; i < clk_hw_count; ++i) {
   537			pic = &__prci_init_clocks[i];
   538	
   539			init.name = pic->name;
   540			init.parent_names = &pic->parent_name;
   541			init.num_parents = 1;
   542			init.ops = pic->ops;
   543			pic->hw.init = &init;
   544	
   545			pic->pd = pd;
   546	
   547			if (pic->pwd)
   548				__prci_wrpll_read_cfg(pd, pic->pwd);
   549	
   550			r = devm_clk_hw_register(dev, &pic->hw);
   551			if (r) {
   552				dev_warn(dev, "Failed to register clock %s: %d\n",
   553					 init.name, r);
   554				return r;
   555			}
   556	
   557			r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));
   558			if (r) {
   559				dev_warn(dev, "Failed to register clkdev for %s: %d\n",
   560					 init.name, r);
   561				return r;
   562			}
   563	
   564			pd->hw_clks.hws[i] = &pic->hw;
   565		}
   566	
   567		pd->hw_clks.num = i;
   568	
   569		r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
   570						&pd->hw_clks);
   571		if (r) {
   572			dev_err(dev, "could not add hw_provider: %d\n", r);
   573			return r;
   574		}
   575	
   576		return 0;
   577	}
   578	

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