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* [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds
@ 2019-05-20  8:28 Tvrtko Ursulin
  2019-05-20  8:28 ` [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode Tvrtko Ursulin
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Tvrtko Ursulin @ 2019-05-20  8:28 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test context workarounds have been correctly applied in a newly created
context.

To accomplish this the existing engine_wa_list_verify helper is extended
to take in a context from which reading of the workaround list will be
done.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 18 +++++++---
 .../gpu/drm/i915/gt/selftest_workarounds.c    | 36 ++++++++++++++++++-
 2 files changed, 49 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 43e290306551..4494bc917084 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1338,11 +1338,13 @@ wa_list_srm(struct i915_request *rq,
 	return 0;
 }
 
-static int engine_wa_list_verify(struct intel_engine_cs *engine,
+static int engine_wa_list_verify(struct i915_gem_context *ctx,
+				 enum intel_engine_id id,
 				 const struct i915_wa_list * const wal,
 				 const char *from)
 {
 	const struct i915_wa *wa;
+	struct intel_context *ce;
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	unsigned int i;
@@ -1352,11 +1354,16 @@ static int engine_wa_list_verify(struct intel_engine_cs *engine,
 	if (!wal->count)
 		return 0;
 
-	vma = create_scratch(&engine->i915->ggtt.vm, wal->count);
+	vma = create_scratch(&ctx->i915->ggtt.vm, wal->count);
 	if (IS_ERR(vma))
 		return PTR_ERR(vma);
 
-	rq = i915_request_create(engine->kernel_context);
+	ce = i915_gem_context_get_engine(ctx, id);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	rq = intel_context_create_request(ce);
+	intel_context_put(ce);
 	if (IS_ERR(rq)) {
 		err = PTR_ERR(rq);
 		goto err_vma;
@@ -1394,7 +1401,10 @@ static int engine_wa_list_verify(struct intel_engine_cs *engine,
 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
 				    const char *from)
 {
-	return engine_wa_list_verify(engine, &engine->wa_list, from);
+	return engine_wa_list_verify(engine->kernel_context->gem_context,
+				     engine->id,
+				     &engine->wa_list,
+				     from);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 9f7680b9984b..ae3f92d55ed8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -1013,7 +1013,7 @@ static bool verify_gt_engine_wa(struct drm_i915_private *i915,
 	ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
 
 	for_each_engine(engine, i915, id) {
-		ok &= engine_wa_list_verify(engine,
+		ok &= engine_wa_list_verify(i915->kernel_context, id,
 					    &lists->engine[id].wa_list,
 					    str) == 0;
 	}
@@ -1142,6 +1142,39 @@ live_engine_reset_gt_engine_workarounds(void *arg)
 	return ret;
 }
 
+static int
+intel_ctx_verify_workarounds(struct intel_engine_cs *engine, const char *from)
+{
+	struct i915_gem_context *ctx =
+		i915_gem_context_create_kernel(engine->i915, 0);
+	int ret;
+
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
+
+	ret = engine_wa_list_verify(ctx, engine->id, &engine->ctx_wa_list,
+				    from);
+
+	i915_gem_context_set_closed(ctx);
+	i915_gem_context_put(ctx);
+
+	return ret;
+}
+
+static int
+live_context_workarounds(void *arg)
+{
+	struct drm_i915_private *i915 = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	int ret = 0;
+
+	for_each_engine(engine, i915, id)
+		ret |= intel_ctx_verify_workarounds(engine, engine->name);
+
+	return ret;
+}
+
 int intel_workarounds_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
@@ -1150,6 +1183,7 @@ int intel_workarounds_live_selftests(struct drm_i915_private *i915)
 		SUBTEST(live_isolated_whitelist),
 		SUBTEST(live_gpu_reset_gt_engine_workarounds),
 		SUBTEST(live_engine_reset_gt_engine_workarounds),
+		SUBTEST(live_context_workarounds),
 	};
 	int err;
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode
  2019-05-20  8:28 [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Tvrtko Ursulin
@ 2019-05-20  8:28 ` Tvrtko Ursulin
  2019-05-20  9:22   ` Chris Wilson
  2019-05-20  8:42 ` [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Chris Wilson
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Tvrtko Ursulin @ 2019-05-20  8:28 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Disable GPU hang by default on unrecoverable ECC cache errors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4494bc917084..dea7df01e0dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -532,6 +532,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
 	struct i915_wa_list *wal = &engine->ctx_wa_list;
+	struct drm_i915_private *dev_priv = i915;
+
+	/* WaDisableBankHangMode:icl */
+	wa_write(wal,
+		 GEN8_L3CNTLREG,
+		 I915_READ(GEN8_L3CNTLREG) | GEN8_ERRDETBCTRL);
 
 	/* Wa_1604370585:icl (pre-prod)
 	 * Formerly known as WaPushConstantDereferenceHoldDisable
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47fca645..87e8780711d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7621,6 +7621,9 @@ enum {
   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
 
+#define GEN8_L3CNTLREG	_MMIO(0x7034)
+  #define GEN8_ERRDETBCTRL (1 << 9)
+
 #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds
  2019-05-20  8:28 [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Tvrtko Ursulin
  2019-05-20  8:28 ` [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode Tvrtko Ursulin
@ 2019-05-20  8:42 ` Chris Wilson
  2019-05-20  9:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
  2019-05-20 10:41 ` ✓ Fi.CI.IGT: " Patchwork
  3 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-05-20  8:42 UTC (permalink / raw)
  To: Intel-gfx, Tvrtko Ursulin

Quoting Tvrtko Ursulin (2019-05-20 09:28:15)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Test context workarounds have been correctly applied in a newly created
> context.
> 
> To accomplish this the existing engine_wa_list_verify helper is extended
> to take in a context from which reading of the workaround list will be
> done.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 18 +++++++---
>  .../gpu/drm/i915/gt/selftest_workarounds.c    | 36 ++++++++++++++++++-
>  2 files changed, 49 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 43e290306551..4494bc917084 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1338,11 +1338,13 @@ wa_list_srm(struct i915_request *rq,
>         return 0;
>  }
>  
> -static int engine_wa_list_verify(struct intel_engine_cs *engine,
> +static int engine_wa_list_verify(struct i915_gem_context *ctx,
> +                                enum intel_engine_id id,
>                                  const struct i915_wa_list * const wal,
>                                  const char *from)
>  {
>         const struct i915_wa *wa;
> +       struct intel_context *ce;

Pass intel_context around, it's far less hairy in the long run.

>         struct i915_request *rq;
>         struct i915_vma *vma;
>         unsigned int i;
> @@ -1352,11 +1354,16 @@ static int engine_wa_list_verify(struct intel_engine_cs *engine,
>         if (!wal->count)
>                 return 0;
>  
> -       vma = create_scratch(&engine->i915->ggtt.vm, wal->count);
> +       vma = create_scratch(&ctx->i915->ggtt.vm, wal->count);
>         if (IS_ERR(vma))
>                 return PTR_ERR(vma);
>  
> -       rq = i915_request_create(engine->kernel_context);
> +       ce = i915_gem_context_get_engine(ctx, id);
> +       if (IS_ERR(ce))
> +               return PTR_ERR(ce);
> +
> +       rq = intel_context_create_request(ce);

Fwiw, this is igt_request_alloc(), but I'd recommend passing
intel_context.

> +       intel_context_put(ce);
>         if (IS_ERR(rq)) {
>                 err = PTR_ERR(rq);
>                 goto err_vma;
> @@ -1394,7 +1401,10 @@ static int engine_wa_list_verify(struct intel_engine_cs *engine,
>  int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
>                                     const char *from)
>  {
> -       return engine_wa_list_verify(engine, &engine->wa_list, from);
> +       return engine_wa_list_verify(engine->kernel_context->gem_context,
> +                                    engine->id,
> +                                    &engine->wa_list,
> +                                    from);
>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 9f7680b9984b..ae3f92d55ed8 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -1013,7 +1013,7 @@ static bool verify_gt_engine_wa(struct drm_i915_private *i915,
>         ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
>  
>         for_each_engine(engine, i915, id) {
> -               ok &= engine_wa_list_verify(engine,
> +               ok &= engine_wa_list_verify(i915->kernel_context, id,

becomes

	ok &= engine_wa_list_verify(engine->kernel_context,

>                                             &lists->engine[id].wa_list,
>                                             str) == 0;
>         }
> @@ -1142,6 +1142,39 @@ live_engine_reset_gt_engine_workarounds(void *arg)
>         return ret;
>  }
>  
> +static int
> +intel_ctx_verify_workarounds(struct intel_engine_cs *engine, const char *from)
> +{
> +       struct i915_gem_context *ctx =
> +               i915_gem_context_create_kernel(engine->i915, 0);
> +       int ret;
> +
> +       if (IS_ERR(ctx))
> +               return PTR_ERR(ctx);
> +

Looks like the first user for a GEM-less intel_context. Food for
thought.

> +       ret = engine_wa_list_verify(ctx, engine->id, &engine->ctx_wa_list,
> +                                   from);
> +
> +       i915_gem_context_set_closed(ctx);
> +       i915_gem_context_put(ctx);
> +
> +       return ret;
> +}
> +
> +static int
> +live_context_workarounds(void *arg)
> +{
> +       struct drm_i915_private *i915 = arg;
> +       struct intel_engine_cs *engine;
> +       enum intel_engine_id id;
> +       int ret = 0;
> +
> +       for_each_engine(engine, i915, id)

So you might as well create the context in the outer scope, then iterate
over the for_each_gem_engine()

> +               ret |= intel_ctx_verify_workarounds(engine, engine->name);

And then we could even extend this to inject a reset and verify the
context is unaffected.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Add live_context_workarounds
  2019-05-20  8:28 [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Tvrtko Ursulin
  2019-05-20  8:28 ` [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode Tvrtko Ursulin
  2019-05-20  8:42 ` [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Chris Wilson
@ 2019-05-20  9:11 ` Patchwork
  2019-05-20 10:41 ` ✓ Fi.CI.IGT: " Patchwork
  3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-05-20  9:11 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Add live_context_workarounds
URL   : https://patchwork.freedesktop.org/series/60846/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6097 -> Patchwork_13042
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/

Known issues
------------

  Here are the changes found in Patchwork_13042 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       [DMESG-WARN][5] ([fdo#108965]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/fi-kbl-8809g/igt@amdgpu/amd_basic@userptr.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/fi-kbl-8809g/igt@amdgpu/amd_basic@userptr.html

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       [INCOMPLETE][7] ([fdo#108602] / [fdo#108744]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html

  
#### Warnings ####

  * igt@i915_selftest@live_hangcheck:
    - fi-apl-guc:         [FAIL][9] ([fdo#110623]) -> [DMESG-FAIL][10] ([fdo#110620])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/fi-apl-guc/igt@i915_selftest@live_hangcheck.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
  [fdo#110623]: https://bugs.freedesktop.org/show_bug.cgi?id=110623


Participating hosts (52 -> 44)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-icl-u3 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6097 -> Patchwork_13042

  CI_DRM_6097: 3f2d6a47d9eec66594887b1e9718bc1a29aa6a77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4996: 6fe5d254ec1b9b47d61408e1b49a7339876bf1e7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13042: 79ed04d95dfc3611c52b8d341fd579d068f994b6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

79ed04d95dfc drm/i915/icl: Add WaDisableBankHangMode
f1a7b8f12e7f drm/i915/selftests: Add live_context_workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode
  2019-05-20  8:28 ` [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode Tvrtko Ursulin
@ 2019-05-20  9:22   ` Chris Wilson
  2019-05-20  9:26     ` Chris Wilson
  0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2019-05-20  9:22 UTC (permalink / raw)
  To: Intel-gfx, Tvrtko Ursulin

Quoting Tvrtko Ursulin (2019-05-20 09:28:16)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Disable GPU hang by default on unrecoverable ECC cache errors.

   uint32_t l3cr;
   anv_pack_struct(&l3cr, GENX(L3CNTLREG),
                   .SLMEnable = has_slm,
#if GEN_GEN == 11
   /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
    * in L3CNTLREG register. The default setting of the bit is not the
    * desirable behavior.
   */
                   .ErrorDetectionBehaviorControl = true,
                   .UseFullWays = true,
#endif
                   .URBAllocation = cfg->n[GEN_L3P_URB],
                   .ROAllocation = cfg->n[GEN_L3P_RO],
                   .DCAllocation = cfg->n[GEN_L3P_DC],
                   .AllAllocation = cfg->n[GEN_L3P_ALL]);

   /* Set up the L3 partitioning. */
   emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG_num), l3cr);

Concurs.

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 3 +++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4494bc917084..dea7df01e0dc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -532,6 +532,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>  {
>         struct drm_i915_private *i915 = engine->i915;
>         struct i915_wa_list *wal = &engine->ctx_wa_list;
> +       struct drm_i915_private *dev_priv = i915;
> +
> +       /* WaDisableBankHangMode:icl */
> +       wa_write(wal,
> +                GEN8_L3CNTLREG,
> +                I915_READ(GEN8_L3CNTLREG) | GEN8_ERRDETBCTRL);

Do you have any clue as to what HW is doing that means we can't set this
in gt_workadounds and just rely on it being part of default context
state? Could be a magical power context register which doesn't take
until the GPU is active. Ok, that seems believable, just ugly to have a
context register that not masked.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode
  2019-05-20  9:22   ` Chris Wilson
@ 2019-05-20  9:26     ` Chris Wilson
  0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-05-20  9:26 UTC (permalink / raw)
  To: Intel-gfx, Tvrtko Ursulin

Quoting Chris Wilson (2019-05-20 10:22:36)
> Quoting Tvrtko Ursulin (2019-05-20 09:28:16)
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Disable GPU hang by default on unrecoverable ECC cache errors.
> 
>    uint32_t l3cr;
>    anv_pack_struct(&l3cr, GENX(L3CNTLREG),
>                    .SLMEnable = has_slm,
> #if GEN_GEN == 11
>    /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
>     * in L3CNTLREG register. The default setting of the bit is not the
>     * desirable behavior.
>    */
>                    .ErrorDetectionBehaviorControl = true,
>                    .UseFullWays = true,
> #endif
>                    .URBAllocation = cfg->n[GEN_L3P_URB],
>                    .ROAllocation = cfg->n[GEN_L3P_RO],
>                    .DCAllocation = cfg->n[GEN_L3P_DC],
>                    .AllAllocation = cfg->n[GEN_L3P_ALL]);
> 
>    /* Set up the L3 partitioning. */
>    emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG_num), l3cr);
> 
> Concurs.
> 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 3 +++
> >  2 files changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 4494bc917084..dea7df01e0dc 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -532,6 +532,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
> >  {
> >         struct drm_i915_private *i915 = engine->i915;
> >         struct i915_wa_list *wal = &engine->ctx_wa_list;
> > +       struct drm_i915_private *dev_priv = i915;
> > +
> > +       /* WaDisableBankHangMode:icl */
> > +       wa_write(wal,
> > +                GEN8_L3CNTLREG,
> > +                I915_READ(GEN8_L3CNTLREG) | GEN8_ERRDETBCTRL);
> 
> Do you have any clue as to what HW is doing that means we can't set this
> in gt_workadounds and just rely on it being part of default context
> state? Could be a magical power context register which doesn't take
> until the GPU is active. Ok, that seems believable, just ugly to have a
> context register that not masked.
> 
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

And probably should be cc:stable if the recommendation change and it
prevents a hang.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/selftests: Add live_context_workarounds
  2019-05-20  8:28 [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Tvrtko Ursulin
                   ` (2 preceding siblings ...)
  2019-05-20  9:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
@ 2019-05-20 10:41 ` Patchwork
  3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-05-20 10:41 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Add live_context_workarounds
URL   : https://patchwork.freedesktop.org/series/60846/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6097_full -> Patchwork_13042_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13042_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@forked-big-copy:
    - shard-iclb:         [PASS][1] -> [TIMEOUT][2] ([fdo#109673])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb1/igt@gem_mmap_gtt@forked-big-copy.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108686])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-apl4/igt@gem_tiled_swapping@non-threaded.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-apl1/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rpm@modeset-stress-extra-wait:
    - shard-glk:          [PASS][5] -> [SKIP][6] ([fdo#109271]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-glk6/igt@i915_pm_rpm@modeset-stress-extra-wait.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-glk3/igt@i915_pm_rpm@modeset-stress-extra-wait.html

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-apl1/igt@i915_suspend@debugfs-reader.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-apl8/igt@i915_suspend@debugfs-reader.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([fdo#103167]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#103167])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-glk:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103359] / [k.org#198133])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-glk3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb3/igt@kms_psr@psr2_dpms.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
    - shard-glk:          [PASS][17] -> [SKIP][18] ([fdo#109271] / [fdo#109278])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-glk6/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-glk3/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@forked-medium-copy-odd:
    - shard-iclb:         [INCOMPLETE][19] ([fdo#107713]) -> [PASS][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb7/igt@gem_mmap_gtt@forked-medium-copy-odd.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb2/igt@gem_mmap_gtt@forked-medium-copy-odd.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-glk:          [DMESG-WARN][21] ([fdo#108686]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-glk7/igt@gem_tiled_swapping@non-threaded.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-glk5/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rpm@debugfs-read:
    - shard-skl:          [INCOMPLETE][23] ([fdo#107807]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-skl3/igt@i915_pm_rpm@debugfs-read.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-skl3/igt@i915_pm_rpm@debugfs-read.html

  * igt@i915_pm_rpm@gem-execbuf:
    - shard-skl:          [INCOMPLETE][25] ([fdo#107803] / [fdo#107807]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-skl4/igt@i915_pm_rpm@gem-execbuf.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-skl9/igt@i915_pm_rpm@gem-execbuf.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][27] ([fdo#105767]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         [FAIL][29] ([fdo#103167]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [FAIL][33] ([fdo#103166]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][35] ([fdo#109441]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@gem_mmap_gtt@forked-big-copy-xy:
    - shard-iclb:         [INCOMPLETE][37] ([fdo#107713] / [fdo#109100]) -> [TIMEOUT][38] ([fdo#109673])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy-xy.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-iclb8/igt@gem_mmap_gtt@forked-big-copy-xy.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-skl:          [SKIP][39] ([fdo#109271]) -> [INCOMPLETE][40] ([fdo#107807])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-skl5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-skl10/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_pm_rpm@pc8-residency:
    - shard-skl:          [INCOMPLETE][41] ([fdo#107807]) -> [SKIP][42] ([fdo#109271])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-skl4/igt@i915_pm_rpm@pc8-residency.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-skl6/igt@i915_pm_rpm@pc8-residency.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][43] ([fdo#102887]) -> [FAIL][44] ([fdo#105363])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6097/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html

  
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6097 -> Patchwork_13042

  CI_DRM_6097: 3f2d6a47d9eec66594887b1e9718bc1a29aa6a77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4996: 6fe5d254ec1b9b47d61408e1b49a7339876bf1e7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13042: 79ed04d95dfc3611c52b8d341fd579d068f994b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13042/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-05-20 10:41 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-20  8:28 [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Tvrtko Ursulin
2019-05-20  8:28 ` [PATCH 2/2] drm/i915/icl: Add WaDisableBankHangMode Tvrtko Ursulin
2019-05-20  9:22   ` Chris Wilson
2019-05-20  9:26     ` Chris Wilson
2019-05-20  8:42 ` [PATCH 1/2] drm/i915/selftests: Add live_context_workarounds Chris Wilson
2019-05-20  9:11 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-05-20 10:41 ` ✓ Fi.CI.IGT: " Patchwork

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