* [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2
@ 2019-05-22 18:58 Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Aleksandar Markovic
` (11 more replies)
0 siblings, 12 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
The following changes since commit a4f667b6714916683408b983cfe0a615a725775f:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into staging (2019-05-21 16:30:13 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-may-19-2019-v2
for you to fetch changes up to 9a89468145b8a3e53e508992f54061427c52780f:
BootLinuxSshTest: Test some userspace commands on Malta (2019-05-22 20:10:46 +0200)
----------------------------------------------------------------
MIPS queue for May 19th, 2019 - v2
v1-v2:
- fixed missing invocations in patch on ST.<B|H|W|D> that caused
clang build error
- added a patch on acceptance test for Malta
overall content:
* Improved usage of object_initialize() and object_initialize_child()
* Added an acceptance test for Malta board
* Better handling of memory pages (flag PAGE_EXEC)
* A set of fixes for emulation of MSA ASE on big endian hosts
* Better handling of 'div by zero' cases of MSA ASE instructions
----------------------------------------------------------------
Jakub Jermář (1):
mips: Decide to map PAGE_EXEC in map_address
Mateja Marjanovic (7):
target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on
hardware
target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on
hardware
target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
target/mips: Refactor and fix COPY_U.<B|H|W> instructions
target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
Philippe Mathieu-Daudé (3):
hw/mips: Use object_initialize() on MIPSCPSState
hw/mips: Use object_initialize_child for correct reference counting
BootLinuxSshTest: Test some userspace commands on Malta
MAINTAINERS | 1 +
hw/mips/boston.c | 25 +-
hw/mips/cps.c | 20 +-
hw/mips/mips_malta.c | 17 +-
target/mips/helper.c | 13 +-
target/mips/helper.h | 16 +-
target/mips/msa_helper.c | 191 ++++++++++-----
target/mips/op_helper.c | 388 +++++++++++++++++++++++++++----
target/mips/translate.c | 59 ++++-
tests/acceptance/linux_ssh_mips_malta.py | 229 ++++++++++++++++++
tests/requirements.txt | 1 +
11 files changed, 817 insertions(+), 143 deletions(-)
create mode 100644 tests/acceptance/linux_ssh_mips_malta.py
--
2.7.4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 02/11] target/mips: Make the results of MOD_<U|S>.<B|H|W|D> " Aleksandar Markovic
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 141, 142).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module, Revision 1.12
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/msa_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c74e3cd..596190b 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -641,14 +641,15 @@ static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
return DF_MIN_INT(df);
}
- return arg2 ? arg1 / arg2 : 0;
+ return arg2 ? arg1 / arg2
+ : arg1 >= 0 ? -1 : 1;
}
static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg2 ? u_arg1 / u_arg2 : 0;
+ return arg2 ? u_arg1 / u_arg2 : -1;
}
static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 02/11] target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 03/11] target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host Aleksandar Markovic
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 255, 256).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module, Revision 1.12
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/msa_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 596190b..274c6ca 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -657,14 +657,14 @@ static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
return 0;
}
- return arg2 ? arg1 % arg2 : 0;
+ return arg2 ? arg1 % arg2 : arg1;
}
static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg2 ? u_arg1 % u_arg2 : 0;
+ return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
}
#define SIGNED_EVEN(a, df) \
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 03/11] target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 02/11] target/mips: Make the results of MOD_<U|S>.<B|H|W|D> " Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 04/11] target/mips: Fix MSA instructions ST.<B|H|W|D> " Aleksandar Markovic
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Fix the case when the host is a big endian machine, and change
the approach toward LD.<B|H|W|D> instruction helpers.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/op_helper.c | 188 ++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 168 insertions(+), 20 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 6d86912..a8ae438 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4356,31 +4356,179 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
#define MEMOP_IDX(DF)
#endif
-#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
-void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
- target_ulong addr) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- wr_t wx; \
- int i; \
- MEMOP_IDX(DF) \
- for (i = 0; i < DF_ELEMENTS(DF); i++) { \
- wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
- } \
- memcpy(pwd, &wx, sizeof(wr_t)); \
+void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_BYTE)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+#else
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+#else
+ pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+#endif
+#endif
}
+void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_HALF)
#if !defined(CONFIG_USER_ONLY)
-MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
-MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
-MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
-MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+#else
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
#else
-MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
-MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
-MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
-MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
+ pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
#endif
+#endif
+}
+
+void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_WORD)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+#else
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+#else
+ pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+#endif
+#endif
+}
+
+void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_DOUBLE)
+#if !defined(CONFIG_USER_ONLY)
+ pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
+ pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
+#else
+ pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
+ pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
+#endif
+}
#define MSA_PAGESPAN(x) \
((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 04/11] target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (2 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 03/11] target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 05/11] target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions Aleksandar Markovic
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Fix the case when the host is a big endian machine, and change
the approach toward ST.<B|H|W|D> instruction helpers.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/op_helper.c | 200 +++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 180 insertions(+), 20 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index a8ae438..3918027 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4550,31 +4550,191 @@ static inline void ensure_writable_pages(CPUMIPSState *env,
#endif
}
-#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
-void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
- target_ulong addr) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- int mmu_idx = cpu_mmu_index(env, false); \
- int i; \
- MEMOP_IDX(DF) \
- ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
- for (i = 0; i < DF_ELEMENTS(DF); i++) { \
- ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
- } \
+void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_BYTE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
+#else
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
+#else
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
+#endif
+#endif
+}
+
+void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_HALF)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
+#else
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
+#else
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
+#endif
+#endif
}
+void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_WORD)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
-MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
-MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
-MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
-MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
#else
-MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
-MSA_ST_DF(DF_HALF, h, cpu_stw_data)
-MSA_ST_DF(DF_WORD, w, cpu_stl_data)
-MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
+#else
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
+#endif
+#endif
+}
+
+void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_DOUBLE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+ helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
+ helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
+#else
+ cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
+ cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
+#endif
+}
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 05/11] target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (3 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 04/11] target/mips: Fix MSA instructions ST.<B|H|W|D> " Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 06/11] target/mips: Refactor and fix COPY_U.<B|H|W> instructions Aleksandar Markovic
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 7 +++++-
target/mips/msa_helper.c | 62 +++++++++++++++++++++++++++++++++---------------
target/mips/translate.c | 19 ++++++++++++++-
3 files changed, 67 insertions(+), 21 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index a6d687e..de3a9e0 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -876,7 +876,7 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32)
+
DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
@@ -938,6 +938,11 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 274c6ca..89b3be9 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1249,29 +1249,53 @@ void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_splat_df(df, pwd, pws, n);
}
-void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
- uint32_t ws, uint32_t n)
+void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
{
- n %= DF_ELEMENTS(df);
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
+#endif
+ env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
+}
- switch (df) {
- case DF_BYTE:
- env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
- break;
- case DF_HALF:
- env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
- break;
- case DF_WORD:
- env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
- break;
-#ifdef TARGET_MIPS64
- case DF_DOUBLE:
- env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
- break;
+void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
+ }
#endif
- default:
- assert(0);
+ env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
+}
+
+void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
}
+#endif
+ env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
+}
+
+void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 2;
+ env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
}
void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96c0d0..c65d19e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28301,7 +28301,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_COPY_U_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 06/11] target/mips: Refactor and fix COPY_U.<B|H|W> instructions
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (4 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 05/11] target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 07/11] target/mips: Refactor and fix INSERT.<B|H|W|D> instructions Aleksandar Markovic
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The old version of the helper for the COPY_U.<B|H|W> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 4 +++-
target/mips/msa_helper.c | 55 +++++++++++++++++++++++++++++++-----------------
target/mips/translate.c | 21 +++++++++++++++++-
3 files changed, 59 insertions(+), 21 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index de3a9e0..c4a77e2 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
@@ -942,6 +941,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 89b3be9..52680fe 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1298,29 +1298,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
}
-void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
- uint32_t ws, uint32_t n)
+void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
{
- n %= DF_ELEMENTS(df);
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
+#endif
+ env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
+}
- switch (df) {
- case DF_BYTE:
- env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
- break;
- case DF_HALF:
- env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
- break;
- case DF_WORD:
- env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
- break;
-#ifdef TARGET_MIPS64
- case DF_DOUBLE:
- env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
- break;
+void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
+ }
#endif
- default:
- assert(0);
+ env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
+}
+
+void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
}
+#endif
+ env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
}
void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c65d19e..68ea6ee 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28297,6 +28297,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
generate_exception_end(ctx, EXCP_RI);
break;
}
+ if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
+ (df == DF_WORD)) {
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
@@ -28323,7 +28328,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
break;
case OPC_COPY_U_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_WORD:
+ gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_INSERT_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 07/11] target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (5 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 06/11] target/mips: Refactor and fix COPY_U.<B|H|W> instructions Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 08/11] hw/mips: Use object_initialize() on MIPSCPSState Aleksandar Markovic
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
The old version of the helper for the INSERT.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>
---
target/mips/helper.h | 5 +++-
target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++++++------------
target/mips/translate.c | 19 +++++++++++++-
3 files changed, 71 insertions(+), 18 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index c4a77e2..2863f60 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
@@ -944,6 +943,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 52680fe..ee1b1fa 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1340,28 +1340,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
}
-void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
+void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
uint32_t rs_num, uint32_t n)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
+#endif
+ pwd->b[n] = (int8_t)rs;
+}
- switch (df) {
- case DF_BYTE:
- pwd->b[n] = (int8_t)rs;
- break;
- case DF_HALF:
- pwd->h[n] = (int16_t)rs;
- break;
- case DF_WORD:
- pwd->w[n] = (int32_t)rs;
- break;
- case DF_DOUBLE:
- pwd->d[n] = (int64_t)rs;
- break;
- default:
- assert(0);
+void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
+ }
+#endif
+ pwd->h[n] = (int16_t)rs;
+}
+
+void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
}
+#endif
+ pwd->w[n] = (int32_t)rs;
+}
+
+void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 2;
+ pwd->d[n] = (int64_t)rs;
}
void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 68ea6ee..dd706ad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28346,7 +28346,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
}
break;
case OPC_INSERT_df:
- gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
break;
}
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 08/11] hw/mips: Use object_initialize() on MIPSCPSState
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (6 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 07/11] target/mips: Refactor and fix INSERT.<B|H|W|D> instructions Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 09/11] hw/mips: Use object_initialize_child for correct reference counting Aleksandar Markovic
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Initialize the MIPSCPSState with object_initialize() instead of
object_new(). This will allow us to add it as children of the
machine container.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20190507163416.24647-10-philmd@redhat.com>
---
hw/mips/boston.c | 25 ++++++++++++-------------
hw/mips/mips_malta.c | 17 ++++++++---------
2 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index a8b29f6..cb3ea85 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -49,7 +49,7 @@ typedef struct {
SysBusDevice parent_obj;
MachineState *mach;
- MIPSCPSState *cps;
+ MIPSCPSState cps;
SerialState *uart;
CharBackend lcd_display;
@@ -188,7 +188,7 @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
case PLAT_DDR3_STATUS:
return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
case PLAT_MMCM_DIV:
- gic_freq = mips_gictimer_get_freq(s->cps->gic.gic_timer) / 1000000;
+ gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
@@ -455,20 +455,19 @@ static void boston_mach_init(MachineState *machine)
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
+ object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS);
+ qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default());
+ object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type",
&err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
@@ -487,17 +486,17 @@ static void boston_mach_init(MachineState *machine)
xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * MiB,
0x40000000, 1 * GiB,
- get_cps_irq(s->cps, 2), false);
+ get_cps_irq(&s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * MiB,
0x20000000, 512 * MiB,
- get_cps_irq(s->cps, 1), false);
+ get_cps_irq(&s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * MiB,
0x16000000, 1 * MiB,
- get_cps_irq(s->cps, 0), true);
+ get_cps_irq(&s->cps, 0), true);
platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
@@ -505,7 +504,7 @@ static void boston_mach_init(MachineState *machine)
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
- get_cps_irq(s->cps, 3), 10000000,
+ get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN);
lcd = g_new(MemoryRegion, 1);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 439665a..04f2117 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -94,7 +94,7 @@ typedef struct {
typedef struct {
SysBusDevice parent_obj;
- MIPSCPSState *cps;
+ MIPSCPSState cps;
qemu_irq *i8259;
} MaltaState;
@@ -1151,20 +1151,19 @@ static void create_cps(MaltaState *s, const char *cpu_type,
{
Error *err = NULL;
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS);
+ qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default());
+ object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err);
+ object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
- *i8259_irq = get_cps_irq(s->cps, 3);
+ *i8259_irq = get_cps_irq(&s->cps, 3);
*cbus_irq = NULL;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 09/11] hw/mips: Use object_initialize_child for correct reference counting
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (7 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 08/11] hw/mips: Use object_initialize() on MIPSCPSState Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 10/11] mips: Decide to map PAGE_EXEC in map_address Aleksandar Markovic
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Philippe Mathieu-Daudé <philmd@redhat.com>
As explained in commit aff39be0ed97:
Both functions, object_initialize() and object_property_add_child()
increase the reference counter of the new object, so one of the
references has to be dropped afterwards to get the reference
counting right. Otherwise the child object will not be properly
cleaned up when the parent gets destroyed.
Thus let's use now object_initialize_child() instead to get the
reference counting here right.
This patch was generated using the following Coccinelle script:
@use_sysbus_init_child_obj_missing_parent@
expression child_ptr;
expression child_type;
expression child_size;
@@
- object_initialize(child_ptr, child_size, child_type);
...
- qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
...
?- object_unref(OBJECT(child_ptr));
+ sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr,
+ child_size, child_type);
We let the Malta/Boston machines adopt the CPS child, and similarly
the CPS adopts the ITU/CPC/GIC/GCR children.
While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:
void sysbus_init_child_obj(Object *parent,
const char *childname, void *child,
size_t childsize, const char *childtype)
{
object_initialize_child(parent, childname, child, childsize,
childtype, &error_abort, NULL);
qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
}
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20190507163416.24647-11-philmd@redhat.com>
---
hw/mips/boston.c | 4 ++--
hw/mips/cps.c | 20 ++++++++------------
hw/mips/mips_malta.c | 4 ++--
3 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index cb3ea85..1ffccc8 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -455,8 +455,8 @@ static void boston_mach_init(MachineState *machine)
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
- object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS);
- qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default());
+ sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps),
+ sizeof(s->cps), TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type",
&err);
object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index fc97f59..649b35a 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -94,9 +94,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
/* Inter-Thread Communication Unit */
if (itu_present) {
- object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
- qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu),
+ TYPE_MIPS_ITU);
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
@@ -115,9 +114,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
}
/* Cluster Power Controller */
- object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
- qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc),
+ TYPE_MIPS_CPC);
object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
@@ -130,9 +128,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
- object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
- qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic),
+ TYPE_MIPS_GIC);
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
@@ -147,9 +144,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
- object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
- qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr),
+ TYPE_MIPS_GCR);
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 04f2117..aff8464 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1151,8 +1151,8 @@ static void create_cps(MaltaState *s, const char *cpu_type,
{
Error *err = NULL;
- object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS);
- qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default());
+ sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps),
+ TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err);
object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 10/11] mips: Decide to map PAGE_EXEC in map_address
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (8 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 09/11] hw/mips: Use object_initialize_child for correct reference counting Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 11/11] BootLinuxSshTest: Test some userspace commands on Malta Aleksandar Markovic
2019-05-22 22:02 ` [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Jakub Jermář <jakub.jermar@kernkonzept.com>
This commit addresses QEMU Bug #1825311:
mips_cpu_handle_mmu_fault renders all accessed pages executable
It allows finer-grained control over whether the accessed page should
be executable by moving the decision to the underlying map_address
function, which has more information for this.
As a result, pages that have the XI bit set in the TLB and are accessed
for read/write, don't suddenly end up being executable.
Fixes: https://bugs.launchpad.net/qemu/+bug/1825311
Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry')
Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>
---
target/mips/helper.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 9799f2e..68e44df 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -43,7 +43,7 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
@@ -61,7 +61,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
else
*physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
@@ -101,6 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
*prot |= PAGE_WRITE;
+ if (!(n ? tlb->XI1 : tlb->XI0)) {
+ *prot |= PAGE_EXEC;
+ }
return TLBRET_MATCH;
}
return TLBRET_DIRTY;
@@ -182,7 +185,7 @@ static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
} else {
/* The segment is unmapped */
*physical = physical_base | (real_address & segmask);
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
}
@@ -907,7 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
return true;
}
@@ -927,7 +930,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
access_type, mips_access_type, mmu_idx);
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
return true;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL v2 11/11] BootLinuxSshTest: Test some userspace commands on Malta
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (9 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 10/11] mips: Decide to map PAGE_EXEC in map_address Aleksandar Markovic
@ 2019-05-22 18:58 ` Aleksandar Markovic
2019-05-22 22:02 ` [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 18:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This tests boot a full VM and check the serial console until
the SSH daemon is running, then start a SSH session and run
some commands.
This test can be run using:
$ avocado --show=ssh run -t arch:mips tests/acceptance/linux_ssh_mips_malta.py
ssh: Entering interactive session.
ssh: # uname -a
ssh: Linux debian-mips 3.2.0-4-4kc-malta #1 Debian 3.2.51-1 mips GNU/Linux
ssh: # lspci -d 11ab:4620
ssh: 00:00.0 Host bridge: Marvell Technology Group Ltd. GT-64120/64120A/64121A System Controller (rev 10)
ssh: # cat /sys/bus/i2c/devices/i2c-0/name
ssh: SMBus PIIX4 adapter at 1100
ssh: # cat /proc/mtd
ssh: dev: size erasesize name
ssh: mtd0: 00100000 00010000 "YAMON"
ssh: mtd1: 002e0000 00010000 "User FS"
ssh: mtd2: 00020000 00010000 "Board Config"
ssh: # md5sum /dev/mtd2ro
ssh: 0dfbe8aa4c20b52e1b8bf3cb6cbdf193 /dev/mtd2ro
ssh: # poweroff
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190520231910.12184-5-f4bug@amsat.org>
---
MAINTAINERS | 1 +
tests/acceptance/linux_ssh_mips_malta.py | 229 +++++++++++++++++++++++++++++++
tests/requirements.txt | 1 +
3 files changed, 231 insertions(+)
create mode 100644 tests/acceptance/linux_ssh_mips_malta.py
diff --git a/MAINTAINERS b/MAINTAINERS
index a6948eb..75f6544 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -934,6 +934,7 @@ M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <arikalo@wavecomp.com>
S: Maintained
F: hw/mips/mips_malta.c
+F: tests/acceptance/linux_ssh_mips_malta.py
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
diff --git a/tests/acceptance/linux_ssh_mips_malta.py b/tests/acceptance/linux_ssh_mips_malta.py
new file mode 100644
index 0000000..ceb530f
--- /dev/null
+++ b/tests/acceptance/linux_ssh_mips_malta.py
@@ -0,0 +1,229 @@
+# Functional test that boots a VM and run commands via a SSH session
+#
+# Copyright (c) Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import os
+import re
+import base64
+import logging
+import paramiko
+import time
+
+from avocado_qemu import Test
+from avocado.utils import process
+from avocado.utils import archive
+
+
+class LinuxSSH(Test):
+
+ timeout = 150 # Not for 'configure --enable-debug --enable-debug-tcg'
+
+ KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+ VM_IP = '127.0.0.1'
+
+ IMAGE_INFO = {
+ 'be': {
+ 'image_url': 'https://people.debian.org/~aurel32/qemu/mips/'
+ 'debian_wheezy_mips_standard.qcow2',
+ 'image_hash': '8987a63270df67345b2135a6b7a4885a35e392d5',
+ 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQCca1VitiyLAdQOld'
+ b'zT43IOEVJZ0wHD78GJi8wDAjMiYWUzNSSn0rXGQsINHuH5'
+ b'IlF+kBZsHinb/FtKCAyS9a8uCHhQI4SuB4QhAb0+39MlUw'
+ b'Mm0CLkctgM2eUUZ6MQMQvDlqnue6CCkxN62EZYbaxmby7j'
+ b'CQa1125o1HRKBvdGm2zrJWxXAfA+f1v6jHLyE8Jnu83eQ+'
+ b'BFY25G+Vzx1PVc3zQBwJ8r0NGTRqy2//oWQP0h+bMsgeFe'
+ b'KH/J3RJM22vg6+I4JAdBFcxnK+l781h1FuRxOn4O/Xslbg'
+ b'go6WtB4V4TOsw2E/KfxI5IZ/icxF+swVcnvF46Hf3uQc/0'
+ b'BBqb',
+ },
+ 'le': {
+ 'image_url': 'https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'debian_wheezy_mipsel_standard.qcow2',
+ 'image_hash': '7866764d9de3ef536ffca24c9fb9f04ffdb45802',
+ 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQClXJlBT71HL5yKvv'
+ b'gfC7jmxSWx5zSBCzET6CLZczwAafSIs7YKfNOy/dQTxhuk'
+ b'yIGFUugZFoF3E9PzdhunuyvyTd56MPoNIqFbb5rGokwU5I'
+ b'TOx3dBHZR0mClypL6MVrwe0bsiIb8GhF1zioNwcsaAZnAi'
+ b'KfXStVDtXvn/kLLq+xLABYt48CC5KYWoFaCoICskLAY+qo'
+ b'L+LWyAnQisj4jAH8VSaSKIImFpfkHWEXPhHcC4ZBlDKtnH'
+ b'po9vhfCHgnfW3Pzrqmk8BI4HysqPFVmJWkJGlGUL+sGeg3'
+ b'ZZolAYuDXGuBrw8ooPJq2v2dOH+z6dyD2q/ypmAbyPqj5C'
+ b'rc8H',
+ },
+ }
+
+ def wait_for_console_pattern(self, success_message,
+ failure_message='Oops'):
+ console = self.vm.console_socket.makefile()
+ console_logger = logging.getLogger('console')
+ while True:
+ msg = console.readline()
+ console_logger.debug(msg.strip())
+ if success_message in msg:
+ break
+ if failure_message in msg:
+ fail = 'Failure message found in console: %s' % failure_message
+ self.fail(fail)
+
+ def get_portfwd(self):
+ res = self.vm.command('human-monitor-command',
+ command_line='info usernet')
+ line = res.split('\r\n')[2]
+ port = re.split(r'.*TCP.HOST_FORWARD.*127\.0\.0\.1 (\d+)\s+10\..*',
+ line)[1]
+ self.log.debug("sshd listening on port:" + port)
+ return port
+
+ def ssh_connect(self, username, password, rsa_hostkey_b64=None):
+ self.ssh_logger = logging.getLogger('ssh')
+ self.ssh_username = username
+ self.ssh_ps1 = '# ' if username is 'root' else '$ '
+ self.ssh_client = paramiko.SSHClient()
+ port = self.get_portfwd()
+ if rsa_hostkey_b64:
+ rsa_hostkey_bin = base64.b64decode(rsa_hostkey_b64)
+ rsa_hostkey = paramiko.RSAKey(data = rsa_hostkey_bin)
+ ipport = '[%s]:%s' % (self.VM_IP, port)
+ self.ssh_logger.debug('ipport ' + ipport)
+ self.ssh_client.get_host_keys().add(ipport, 'ssh-rsa', rsa_hostkey)
+ for i in range(10):
+ try:
+ self.ssh_client.connect(self.VM_IP, int(port),
+ username, password, banner_timeout=90)
+ self.ssh_logger.info("Entering interactive session.")
+ return
+ except:
+ time.sleep(4)
+ pass
+ self.fail("sshd timeout")
+
+ def ssh_disconnect_vm(self):
+ self.ssh_client.close()
+
+ def ssh_command(self, command, is_root=True):
+ self.ssh_logger.info(self.ssh_ps1 + command)
+ stdin, stdout, stderr = self.ssh_client.exec_command(command)
+ stdout_lines = [line.strip('\n') for line in stdout]
+ for line in stdout_lines:
+ self.ssh_logger.info(line)
+ stderr_lines = [line.strip('\n') for line in stderr]
+ for line in stderr_lines:
+ self.ssh_logger.warning(line)
+ return stdout_lines, stderr_lines
+
+ def boot_debian_wheezy_image_and_ssh_login(self, endianess, kernel_path):
+ image_url = self.IMAGE_INFO[endianess]['image_url']
+ image_hash = self.IMAGE_INFO[endianess]['image_hash']
+ image_path = self.fetch_asset(image_url, asset_hash=image_hash)
+ rsa_hostkey_b64 = self.IMAGE_INFO[endianess]['rsa_hostkey']
+
+ self.vm.set_machine('malta')
+ self.vm.set_console()
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE
+ + 'console=ttyS0 root=/dev/sda1')
+ self.vm.add_args('-no-reboot',
+ '-kernel', kernel_path,
+ '-append', kernel_command_line,
+ '-hda', image_path,
+ '-netdev', 'user,id=vnet,hostfwd=:127.0.0.1:0-:22',
+ '-device', 'pcnet,netdev=vnet')
+ self.vm.launch()
+
+ self.log.info('VM launched, waiting for sshd')
+ console_pattern = 'Starting OpenBSD Secure Shell server: sshd'
+ self.wait_for_console_pattern(console_pattern)
+ self.log.info('sshd ready')
+
+ self.ssh_connect('root', 'root', rsa_hostkey_b64=rsa_hostkey_b64)
+
+ def shutdown_via_ssh(self):
+ self.ssh_command('poweroff')
+ self.ssh_disconnect_vm()
+ self.wait_for_console_pattern('Power down')
+
+ def run_common_commands(self):
+ stdout, stderr = self.ssh_command('lspci -d 11ab:4620')
+ self.assertIn(True, ["GT-64120" in line for line in stdout])
+
+ stdout, stderr = self.ssh_command('cat /sys/bus/i2c/devices/i2c-0/name')
+ self.assertIn(True, ["SMBus PIIX4 adapter" in line
+ for line in stdout])
+
+ stdout, stderr = self.ssh_command('cat /proc/mtd')
+ self.assertIn(True, ["YAMON" in line
+ for line in stdout])
+
+ # Empty 'Board Config'
+ stdout, stderr = self.ssh_command('md5sum /dev/mtd2ro')
+ self.assertIn(True, ["0dfbe8aa4c20b52e1b8bf3cb6cbdf193" in line
+ for line in stdout])
+
+ def do_test_mips_malta(self, endianess, kernel_path, uname_m):
+ self.boot_debian_wheezy_image_and_ssh_login(endianess, kernel_path)
+
+ stdout, stderr = self.ssh_command('uname -a')
+ self.assertIn(True, [uname_m + " GNU/Linux" in line for line in stdout])
+
+ self.run_common_commands()
+ self.shutdown_via_ssh()
+
+ def test_mips_malta32eb_kernel3_2_0(self):
+ """
+ :avocado: tags=slow
+ :avocado: tags=arch:mips
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:big
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
+ 'vmlinux-3.2.0-4-4kc-malta')
+ kernel_hash = '592e384a4edc16dade52a6cd5c785c637bcbc9ad'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.do_test_mips_malta('be', kernel_path, 'mips')
+
+ def test_mips_malta32el_kernel3_2_0(self):
+ """
+ :avocado: tags=slow
+ :avocado: tags=arch:mipsel
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:little
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'vmlinux-3.2.0-4-4kc-malta')
+ kernel_hash = 'a66bea5a8adaa2cb3d36a1d4e0ccdb01be8f6c2a'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.do_test_mips_malta('le', kernel_path, 'mips')
+
+ def test_mips_malta64eb_kernel3_2_0(self):
+ """
+ :avocado: tags=slow
+ :avocado: tags=arch:mips64
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:big
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
+ 'vmlinux-3.2.0-4-5kc-malta')
+ kernel_hash = 'db6eea7de35d36c77d8c165b6bcb222e16eb91db'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+ self.do_test_mips_malta('be', kernel_path, 'mips64')
+
+ def test_mips_malta64el_kernel3_2_0(self):
+ """
+ :avocado: tags=slow
+ :avocado: tags=arch:mips64el
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:little
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'vmlinux-3.2.0-4-5kc-malta')
+ kernel_hash = '6a7f77245acf231415a0e8b725d91ed2f3487794'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+ self.do_test_mips_malta('le', kernel_path, 'mips64')
diff --git a/tests/requirements.txt b/tests/requirements.txt
index 002ded6..3ae0e29 100644
--- a/tests/requirements.txt
+++ b/tests/requirements.txt
@@ -2,3 +2,4 @@
# in the tests/venv Python virtual environment. For more info,
# refer to: https://pip.pypa.io/en/stable/user_guide/#id1
avocado-framework==68.0
+paramiko
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
` (10 preceding siblings ...)
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 11/11] BootLinuxSshTest: Test some userspace commands on Malta Aleksandar Markovic
@ 2019-05-22 22:02 ` Aleksandar Markovic
11 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-05-22 22:02 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: peter.maydell, qemu-devel, amarkovic
On May 22, 2019 9:15 PM, "Aleksandar Markovic" <
aleksandar.markovic@rt-rk.com> wrote:
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit
a4f667b6714916683408b983cfe0a615a725775f:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3'
into staging (2019-05-21 16:30:13 +0100)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-may-19-2019-v2
>
> for you to fetch changes up to 9a89468145b8a3e53e508992f54061427c52780f:
>
> BootLinuxSshTest: Test some userspace commands on Malta (2019-05-22
20:10:46 +0200)
>
> ----------------------------------------------------------------
>
Peter,
Please put this pull request on hold, there are some reservations from test
group about patch 11/11, that came just hours after I sent this pull
request.
Yours,
Aleksandar
> MIPS queue for May 19th, 2019 - v2
>
> v1-v2:
> - fixed missing invocations in patch on ST.<B|H|W|D> that caused
> clang build error
> - added a patch on acceptance test for Malta
>
> overall content:
>
> * Improved usage of object_initialize() and object_initialize_child()
> * Added an acceptance test for Malta board
> * Better handling of memory pages (flag PAGE_EXEC)
> * A set of fixes for emulation of MSA ASE on big endian hosts
> * Better handling of 'div by zero' cases of MSA ASE instructions
>
> ----------------------------------------------------------------
>
> Jakub Jermář (1):
> mips: Decide to map PAGE_EXEC in map_address
>
> Mateja Marjanovic (7):
> target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on
> hardware
> target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on
> hardware
> target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
> target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
> target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
> target/mips: Refactor and fix COPY_U.<B|H|W> instructions
> target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
>
> Philippe Mathieu-Daudé (3):
> hw/mips: Use object_initialize() on MIPSCPSState
> hw/mips: Use object_initialize_child for correct reference counting
> BootLinuxSshTest: Test some userspace commands on Malta
>
> MAINTAINERS | 1 +
> hw/mips/boston.c | 25 +-
> hw/mips/cps.c | 20 +-
> hw/mips/mips_malta.c | 17 +-
> target/mips/helper.c | 13 +-
> target/mips/helper.h | 16 +-
> target/mips/msa_helper.c | 191 ++++++++++-----
> target/mips/op_helper.c | 388
+++++++++++++++++++++++++++----
> target/mips/translate.c | 59 ++++-
> tests/acceptance/linux_ssh_mips_malta.py | 229 ++++++++++++++++++
> tests/requirements.txt | 1 +
> 11 files changed, 817 insertions(+), 143 deletions(-)
> create mode 100644 tests/acceptance/linux_ssh_mips_malta.py
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-05-22 22:03 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-22 18:58 [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 02/11] target/mips: Make the results of MOD_<U|S>.<B|H|W|D> " Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 03/11] target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 04/11] target/mips: Fix MSA instructions ST.<B|H|W|D> " Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 05/11] target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 06/11] target/mips: Refactor and fix COPY_U.<B|H|W> instructions Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 07/11] target/mips: Refactor and fix INSERT.<B|H|W|D> instructions Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 08/11] hw/mips: Use object_initialize() on MIPSCPSState Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 09/11] hw/mips: Use object_initialize_child for correct reference counting Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 10/11] mips: Decide to map PAGE_EXEC in map_address Aleksandar Markovic
2019-05-22 18:58 ` [Qemu-devel] [PULL v2 11/11] BootLinuxSshTest: Test some userspace commands on Malta Aleksandar Markovic
2019-05-22 22:02 ` [Qemu-devel] [PULL v2 00/11] MIPS queue for May 19th, 2019 - v2 Aleksandar Markovic
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