[U-Boot] [PATCH 1/2] spl: at91: add support for SPL_AT91_MCK_BYPASS

[U-Boot] [PATCH 1/2] spl: at91: add support for SPL_AT91_MCK_BYPASS

[Eugen.Hristev at microchip.com]

From: Eugen Hristev <eugen.hristev@microchip.com>

By default the configuration of the PMC is to have an external crystal
connected that requires driving on both XIN and XOUT pins.
The bypass configuration means that only XIN will be used, the SoC will not
do any driving, and the XIN needs to be provided with a proper signal.
This is the MOSCXTBY bit in the PMC main clock generator register.
The SPL needs to properly initialize the PMC registers before switching
to external clock signal and raising the clock to the cruise speed.

Also created Kconfig for this specific configuration.
By default this is disabled.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
 arch/arm/mach-at91/spl_atmel.c |  8 ++++++++
 common/spl/Kconfig             | 12 ++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index ef745c9..85290be 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -44,7 +44,15 @@ static void switch_to_main_crystal_osc(void)
 #endif
 
 	tmp = readl(&pmc->mor);
+/*
+ * some boards have an external oscillator with driving.
+ * in this case we need to disable the internal SoC driving (bypass mode)
+ */
+#if defined(CONFIG_SPL_AT91_MCK_BYPASS)
+	tmp |= AT91_PMC_MOR_OSCBYPASS;
+#else
 	tmp &= ~AT91_PMC_MOR_OSCBYPASS;
+#endif
 	tmp &= ~AT91_PMC_MOR_KEY(0xff);
 	tmp |= AT91_PMC_MOR_KEY(0x37);
 	writel(tmp, &pmc->mor);
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dd078fe..0d01353 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1151,5 +1151,17 @@ config TPL_YMODEM_SUPPORT
 
 endif # TPL
 
+config SPL_AT91_MCK_BYPASS
+	bool "Use external clock signal as a source of main clock for AT91 platforms"
+	depends on ARCH_AT91
+	default n
+	help
+	  Use external 8 to 24 Mhz clock signal as source of main clock instead
+	  of an external crystal oscillator.
+	  This option disables the internal driving on the XOUT pin.
+	  The external source has to provide a stable clock on the XIN pin.
+	  If this option is disabled, the SoC expects a crystal oscillator
+	  that needs driving on both XIN and XOUT lines.
+
 endif # SPL
 endmenu
-- 
2.7.4

[U-Boot] [PATCH 2/2] configs: at91: sama5d2_icp: enable CONFIG_SPL_AT91_MCK_BYPASS and resync

[Eugen.Hristev at microchip.com]

From: Eugen Hristev <eugen.hristev@microchip.com>

Enabled CONFIG_SPL_AT91_MCK_BYPASS and resync with savedefconfig

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
 configs/sama5d2_icp_mmc_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 1fafb76..e047108 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -23,12 +23,12 @@ CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DISPLAY_PRINT=y
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_AT91_MCK_BYPASS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -75,3 +75,4 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER_HII is not set
-- 
2.7.4

[U-Boot] [PATCH 1/2] spl: at91: add support for SPL_AT91_MCK_BYPASS

[Eugen.Hristev at microchip.com]

On 24.05.2019 09:47, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
> 
> By default the configuration of the PMC is to have an external crystal
> connected that requires driving on both XIN and XOUT pins.
> The bypass configuration means that only XIN will be used, the SoC will not
> do any driving, and the XIN needs to be provided with a proper signal.
> This is the MOSCXTBY bit in the PMC main clock generator register.
> The SPL needs to properly initialize the PMC registers before switching
> to external clock signal and raising the clock to the cruise speed.
> 
> Also created Kconfig for this specific configuration.
> By default this is disabled.
> 
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---

Applied both patches in series to u-boot-atmel/master