* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
@ 2019-05-24 11:29 xieqinick at gmail.com
0 siblings, 0 replies; 10+ messages in thread
From: xieqinick at gmail.com @ 2019-05-24 11:29 UTC (permalink / raw)
To: u-boot
From: Nick <nick@khadas.com>
Khadas Edge is a board from Khadas, you can find the detail about it here:
https://www.khadas.com/edge
This patch add basic node for the board and make it able to bring up.
Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU
Signed-off-by: Nick <nick@khadas.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-kedge-u-boot.dtsi | 10 +
arch/arm/dts/rk3399-kedge.dts | 611 ++++++++++++++++++++++++++++++++++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/khadas-edge-rk3399_defconfig | 63 ++++
5 files changed, 692 insertions(+)
create mode 100644 arch/arm/dts/rk3399-kedge-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-kedge.dts
create mode 100644 configs/khadas-edge-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 31ef2b6..d9adecf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
+ rk3399-kedge.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3399-kedge-u-boot.dtsi b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
new file mode 100644
index 0000000..bf0d54c
--- /dev/null
+++ b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Nick <nick@khadas.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+
+&sdmmc {
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
diff --git a/arch/arm/dts/rk3399-kedge.dts b/arch/arm/dts/rk3399-kedge.dts
new file mode 100644
index 0000000..e07e699
--- /dev/null
+++ b/arch/arm/dts/rk3399-kedge.dts
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based Khadas boards device tree source
+ *
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com/edge)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Khadas Edge";
+ compatible = "khadas,edge", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+// vin-supply = <&vdd_5v>;
+ };
+
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc3v3_s3>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ vdd_cpu_b: regulator at 40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu_b";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator at 41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ clock-output-names = "xin32k", "rtc_clko_wifi";
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_center";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_cpu_l";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_apio2: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_apio2";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_vldo2: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_vldo2";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmupll";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_vldo5: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_vldo5";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_1v5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_3v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc1v8_apio2>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vccio_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb2 {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ power_key: power-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc0_det_l: sdmmc0-det-l {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin_pull_down>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index f55c92f..bcb058c 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -24,3 +24,10 @@ S: Maintained
F: configs/orangepi-rk3399_defconfig
F: arch/arm/dts/rk3399-u-boot.dtsi
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+
+KHADAS-EDGE
+M: Nick <nick@khadas.com>
+S: Maintained
+F: configs/khadas-edge-rk3399_defconfig
+F: arch/arm/dts/rk3399-kedge.dts
+F: arch/arm/dts/rk3399-kedge-u-boot.dtsi
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
new file mode 100644
index 0000000..a9def59
--- /dev/null
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kedge.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SYS_PROMPT="kedge# "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-kedge"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-07-27 1:09 ` Nick Xie
@ 2019-07-27 9:25 ` Chris Webb
0 siblings, 0 replies; 10+ messages in thread
From: Chris Webb @ 2019-07-27 9:25 UTC (permalink / raw)
To: u-boot
Nick Xie <xieqinick@gmail.com> wrote:
> That's great! I'll update the patches and send them soon.
I'll make sure I test your specific patch when you post it, but I can
already confirm that u-boot.git master happily boots a Khadas Edge board.
I just added the unmodified Edge device tree from mainline Linux into
arch/arm/dts/, created the u-boot fixup .dtsi and\x05 defconfig with
sed 's/rock-pi-4/khadas-edge/g' configs/rock-pi-4-rk3399_defconfig \
>configs/khadas-edge-rk3399_defconfig
cp arch/arm/dts/rk3399-{rock-pi-4,khadas-edge}-u-boot.dtsi
make khadas-edge-rk3399_defconfig
then built u-boot with an rk3399 bl31.elf from master of
arm-trusted-firmware.git.
It boots TPL -> SPL -> U-Boot proper -> Linux just fine without any
external idbloader.bin or standalone trusted firmware - faster and much
less noisy!
Best wishes,
Chris.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-07-26 13:52 ` Chris Webb
@ 2019-07-27 1:09 ` Nick Xie
2019-07-27 9:25 ` Chris Webb
0 siblings, 1 reply; 10+ messages in thread
From: Nick Xie @ 2019-07-27 1:09 UTC (permalink / raw)
To: u-boot
Hello Chris,
That's great! I'll update the patches and send them soon.
Chris Webb <chris@arachsys.com> 于2019年7月26日周五 下午9:52写道：
> Hi Nick. I think Kever has merged the LPDDR4 series, and it's already
> made
> its way into the mainline u-boot master branch.
>
>
> https://gitlab.denx.de/u-boot/u-boot/commit/852f6ddd76fad2d5adef3f7e3a75d0065c68db3b
>
> and its ancestors are the v3 series Jagan posted to the list.
>
> There have also been a number of other rk3399 cleanups since then, so the
> defconfig might need updating to suit. (I just copied the rock-pi-4
> defconfig and replaced the default device tree.)
>
> Best wishes,
>
> Chris.
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-07-26 9:55 ` Nick
@ 2019-07-26 13:52 ` Chris Webb
2019-07-27 1:09 ` Nick Xie
0 siblings, 1 reply; 10+ messages in thread
From: Chris Webb @ 2019-07-26 13:52 UTC (permalink / raw)
To: u-boot
Hi Nick. I think Kever has merged the LPDDR4 series, and it's already made
its way into the mainline u-boot master branch.
https://gitlab.denx.de/u-boot/u-boot/commit/852f6ddd76fad2d5adef3f7e3a75d0065c68db3b
and its ancestors are the v3 series Jagan posted to the list.
There have also been a number of other rk3399 cleanups since then, so the
defconfig might need updating to suit. (I just copied the rock-pi-4
defconfig and replaced the default device tree.)
Best wishes,
Chris.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-07-26 8:00 ` Kever Yang
@ 2019-07-26 9:55 ` Nick
2019-07-26 13:52 ` Chris Webb
0 siblings, 1 reply; 10+ messages in thread
From: Nick @ 2019-07-26 9:55 UTC (permalink / raw)
To: u-boot
Hello Kever
Yes, I will do this when the DDR patches merged.
Nick
> 在 2019年7月26日，16:00，Kever Yang <kever.yang@rock-chips.com> 写道：
>
> Hi Nick,
>
> Are you going to send a new patch set with the update of change request?
>
> Thanks,
> - Kever
>
> Jagan Teki <jagan@amarulasolutions.com> 于2019年5月25日周六 下午1:57写道：
>> On Sat, May 25, 2019 at 9:14 AM Nick Xie <xieqinick@gmail.com> wrote:
>> >
>> >
>> > Hello Jagan,
>> >
>> > Thanks for your review.
>> >
>> >> > Hope you sync the dts from Linux, if not please submit it and aprove
>> >> > first, if yes then add commit sha1. This would help to keep track of
>> >> > syncing dts from Linux later and since dts files are more relatives
>> >> > same from Linux it always better to approve Linux first interms of
>> >> > binidngs and all.
>> >
>> >
>> > As I haven't sent patches to linux upstream yet, my plan is to send patches to u-boot first, then send patches to linux.
>> >
>> > The dts of u-boot must sync from the mainline linux?
>>
>> We use dts from Linux and we don't have specific maintainer for these
>> (atleast no need). DTS files coming from Linux means it's been
>> reviewed by respective maintainer along with devicetree ML.
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-05-25 5:57 ` Jagan Teki
@ 2019-07-26 8:00 ` Kever Yang
2019-07-26 9:55 ` Nick
0 siblings, 1 reply; 10+ messages in thread
From: Kever Yang @ 2019-07-26 8:00 UTC (permalink / raw)
To: u-boot
Hi Nick,
Are you going to send a new patch set with the update of change request?
Thanks,
- Kever
Jagan Teki <jagan@amarulasolutions.com> 于2019年5月25日周六 下午1:57写道：
> On Sat, May 25, 2019 at 9:14 AM Nick Xie <xieqinick@gmail.com> wrote:
> >
> >
> > Hello Jagan,
> >
> > Thanks for your review.
> >
> >> > Hope you sync the dts from Linux, if not please submit it and aprove
> >> > first, if yes then add commit sha1. This would help to keep track of
> >> > syncing dts from Linux later and since dts files are more relatives
> >> > same from Linux it always better to approve Linux first interms of
> >> > binidngs and all.
> >
> >
> > As I haven't sent patches to linux upstream yet, my plan is to send
> patches to u-boot first, then send patches to linux.
> >
> > The dts of u-boot must sync from the mainline linux?
>
> We use dts from Linux and we don't have specific maintainer for these
> (atleast no need). DTS files coming from Linux means it's been
> reviewed by respective maintainer along with devicetree ML.
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-05-25 3:44 ` Nick Xie
@ 2019-05-25 5:57 ` Jagan Teki
2019-07-26 8:00 ` Kever Yang
0 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2019-05-25 5:57 UTC (permalink / raw)
To: u-boot
On Sat, May 25, 2019 at 9:14 AM Nick Xie <xieqinick@gmail.com> wrote:
>
>
> Hello Jagan,
>
> Thanks for your review.
>
>> > Hope you sync the dts from Linux, if not please submit it and aprove
>> > first, if yes then add commit sha1. This would help to keep track of
>> > syncing dts from Linux later and since dts files are more relatives
>> > same from Linux it always better to approve Linux first interms of
>> > binidngs and all.
>
>
> As I haven't sent patches to linux upstream yet, my plan is to send patches to u-boot first, then send patches to linux.
>
> The dts of u-boot must sync from the mainline linux?
We use dts from Linux and we don't have specific maintainer for these
(atleast no need). DTS files coming from Linux means it's been
reviewed by respective maintainer along with devicetree ML.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-05-24 18:23 ` Jagan Teki
@ 2019-05-25 3:44 ` Nick Xie
2019-05-25 5:57 ` Jagan Teki
0 siblings, 1 reply; 10+ messages in thread
From: Nick Xie @ 2019-05-25 3:44 UTC (permalink / raw)
To: u-boot
Hello Jagan,
Thanks for your review.
> Hope you sync the dts from Linux, if not please submit it and aprove
> > first, if yes then add commit sha1. This would help to keep track of
> > syncing dts from Linux later and since dts files are more relatives
> > same from Linux it always better to approve Linux first interms of
> > binidngs and all.
As I haven't sent patches to linux upstream yet, my plan is to send patches
to u-boot first, then send patches to linux.
The dts of u-boot must sync from the mainline linux?
Thanks,
Best Regards,
Nick.
Jagan Teki <jagan@amarulasolutions.com> 于2019年5月25日周六 上午2:23写道：
> + CCed to mainatiners.
>
> On Fri, May 24, 2019 at 5:52 PM <xieqinick@gmail.com> wrote:
> >
> > From: Nick <nick@khadas.com>
> >
> > Khadas Edge is a board from Khadas, you can find the detail about it
> here:
> > https://www.khadas.com/edge
>
> Drop this http from commit message, we usually don't keep.
>
> >
> > This patch add basic node for the board and make it able to bring up.
> >
> > Specification
> > - Rockchip RK3399
> > - Dual-Channel 2GB/4GB LPDDR4
> > - SD card slot
> > - Onboard 16GB/32GB/128GB eMMC
> > - RTL8211FD 1Gbps
> > - AP6356S/AP6398S WiFI/BT
> > - HDMI Out, DP, MIPI DSI/CSI, eDP
> > - USB 3.0, 2.0
> > - USB Type C power and data
> > - GPIO expansion ports
> > - Full 4 Lane M.2 Socket
> > - 16MB SPI Flash
> > - IR
> > - Programmable MCU
> >
>
> Hope you sync the dts from Linux, if not please submit it and aprove
> first, if yes then add commit sha1. This would help to keep track of
> syncing dts from Linux later and since dts files are more relatives
> same from Linux it always better to approve Linux first interms of
> binidngs and all.
>
> > Signed-off-by: Nick <nick@khadas.com>
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/rk3399-kedge-u-boot.dtsi | 10 +
> > arch/arm/dts/rk3399-kedge.dts | 611
> ++++++++++++++++++++++++++++++++++
> > board/rockchip/evb_rk3399/MAINTAINERS | 7 +
> > configs/khadas-edge-rk3399_defconfig | 63 ++++
> > 5 files changed, 692 insertions(+)
> > create mode 100644 arch/arm/dts/rk3399-kedge-u-boot.dtsi
> > create mode 100644 arch/arm/dts/rk3399-kedge.dts
> > create mode 100644 configs/khadas-edge-rk3399_defconfig
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 31ef2b6..d9adecf 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> > rk3399-puma-ddr1600.dtb \
> > rk3399-puma-ddr1866.dtb \
> > rk3399-rock960.dtb \
> > + rk3399-kedge.dtb
>
> Keep it in accending order.
>
> >
> > dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> > rv1108-elgin-r1.dtb \
> > diff --git a/arch/arm/dts/rk3399-kedge-u-boot.dtsi
> b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
> > new file mode 100644
> > index 0000000..bf0d54c
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
> > @@ -0,0 +1,10 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019 Nick <nick@khadas.com>
> > + */
> > +
> > +#include "rk3399-u-boot.dtsi"
> > +
> > +&sdmmc {
> > + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
> > +};
> > diff --git a/arch/arm/dts/rk3399-kedge.dts
> b/arch/arm/dts/rk3399-kedge.dts
> > new file mode 100644
> > index 0000000..e07e699
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3399-kedge.dts
> > @@ -0,0 +1,611 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * RK3399-based Khadas boards device tree source
> > + *
> > + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
> > + * (https://www.khadas.com/edge)
> > + */
> > +
> > +/dts-v1/;
> > +#include <dt-bindings/input/linux-event-codes.h>
> > +#include "rk3399.dtsi"
> > +#include "rk3399-opp.dtsi"
> > +
> > +/ {
> > + model = "Khadas Edge";
> > + compatible = "khadas,edge", "rockchip,rk3399";
> > +
>
> [snip]
>
> > + status = "okay";
> > +};
> > diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
> b/board/rockchip/evb_rk3399/MAINTAINERS
> > index f55c92f..bcb058c 100644
> > --- a/board/rockchip/evb_rk3399/MAINTAINERS
> > +++ b/board/rockchip/evb_rk3399/MAINTAINERS
> > @@ -24,3 +24,10 @@ S: Maintained
> > F: configs/orangepi-rk3399_defconfig
> > F: arch/arm/dts/rk3399-u-boot.dtsi
> > F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
> > +
> > +KHADAS-EDGE
>
> Same here keep maintain the order.
>
> > +M: Nick <nick@khadas.com>
> > +S: Maintained
> > +F: configs/khadas-edge-rk3399_defconfig
> > +F: arch/arm/dts/rk3399-kedge.dts
> > +F: arch/arm/dts/rk3399-kedge-u-boot.dtsi
> > diff --git a/configs/khadas-edge-rk3399_defconfig
> b/configs/khadas-edge-rk3399_defconfig
> > new file mode 100644
> > index 0000000..a9def59
> > --- /dev/null
> > +++ b/configs/khadas-edge-rk3399_defconfig
> > @@ -0,0 +1,63 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_ROCKCHIP=y
> > +CONFIG_SYS_TEXT_BASE=0x00200000
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x4000
> > +CONFIG_ROCKCHIP_RK3399=y
> > +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_SPL_STACK_R_ADDR=0x80000
> > +CONFIG_DEBUG_UART_BASE=0xFF1A0000
> > +CONFIG_DEBUG_UART_CLOCK=24000000
> > +CONFIG_DEBUG_UART=y
> > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kedge.dtb"
> > +# CONFIG_DISPLAY_CPUINFO is not set
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_SPL_TEXT_BASE=0xff8c2000
> > +CONFIG_SPL_STACK_R=y
>
> Seems like you are not using SPL, so use TPL that would take care of
> rkbin ddr init like this patch does [1]
>
> [1] https://patchwork.ozlabs.org/patch/1100945/
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
2019-05-24 11:19 xieqinick at gmail.com
@ 2019-05-24 18:23 ` Jagan Teki
2019-05-25 3:44 ` Nick Xie
0 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2019-05-24 18:23 UTC (permalink / raw)
To: u-boot
+ CCed to mainatiners.
On Fri, May 24, 2019 at 5:52 PM <xieqinick@gmail.com> wrote:
>
> From: Nick <nick@khadas.com>
>
> Khadas Edge is a board from Khadas, you can find the detail about it here:
> https://www.khadas.com/edge
Drop this http from commit message, we usually don't keep.
>
> This patch add basic node for the board and make it able to bring up.
>
> Specification
> - Rockchip RK3399
> - Dual-Channel 2GB/4GB LPDDR4
> - SD card slot
> - Onboard 16GB/32GB/128GB eMMC
> - RTL8211FD 1Gbps
> - AP6356S/AP6398S WiFI/BT
> - HDMI Out, DP, MIPI DSI/CSI, eDP
> - USB 3.0, 2.0
> - USB Type C power and data
> - GPIO expansion ports
> - Full 4 Lane M.2 Socket
> - 16MB SPI Flash
> - IR
> - Programmable MCU
>
Hope you sync the dts from Linux, if not please submit it and aprove
first, if yes then add commit sha1. This would help to keep track of
syncing dts from Linux later and since dts files are more relatives
same from Linux it always better to approve Linux first interms of
binidngs and all.
> Signed-off-by: Nick <nick@khadas.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3399-kedge-u-boot.dtsi | 10 +
> arch/arm/dts/rk3399-kedge.dts | 611 ++++++++++++++++++++++++++++++++++
> board/rockchip/evb_rk3399/MAINTAINERS | 7 +
> configs/khadas-edge-rk3399_defconfig | 63 ++++
> 5 files changed, 692 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-kedge-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-kedge.dts
> create mode 100644 configs/khadas-edge-rk3399_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 31ef2b6..d9adecf 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> rk3399-puma-ddr1600.dtb \
> rk3399-puma-ddr1866.dtb \
> rk3399-rock960.dtb \
> + rk3399-kedge.dtb
Keep it in accending order.
>
> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> rv1108-elgin-r1.dtb \
> diff --git a/arch/arm/dts/rk3399-kedge-u-boot.dtsi b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
> new file mode 100644
> index 0000000..bf0d54c
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Nick <nick@khadas.com>
> + */
> +
> +#include "rk3399-u-boot.dtsi"
> +
> +&sdmmc {
> + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
> +};
> diff --git a/arch/arm/dts/rk3399-kedge.dts b/arch/arm/dts/rk3399-kedge.dts
> new file mode 100644
> index 0000000..e07e699
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-kedge.dts
> @@ -0,0 +1,611 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * RK3399-based Khadas boards device tree source
> + *
> + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
> + * (https://www.khadas.com/edge)
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include "rk3399.dtsi"
> +#include "rk3399-opp.dtsi"
> +
> +/ {
> + model = "Khadas Edge";
> + compatible = "khadas,edge", "rockchip,rk3399";
> +
[snip]
> + status = "okay";
> +};
> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
> index f55c92f..bcb058c 100644
> --- a/board/rockchip/evb_rk3399/MAINTAINERS
> +++ b/board/rockchip/evb_rk3399/MAINTAINERS
> @@ -24,3 +24,10 @@ S: Maintained
> F: configs/orangepi-rk3399_defconfig
> F: arch/arm/dts/rk3399-u-boot.dtsi
> F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
> +
> +KHADAS-EDGE
Same here keep maintain the order.
> +M: Nick <nick@khadas.com>
> +S: Maintained
> +F: configs/khadas-edge-rk3399_defconfig
> +F: arch/arm/dts/rk3399-kedge.dts
> +F: arch/arm/dts/rk3399-kedge-u-boot.dtsi
> diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
> new file mode 100644
> index 0000000..a9def59
> --- /dev/null
> +++ b/configs/khadas-edge-rk3399_defconfig
> @@ -0,0 +1,63 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00200000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x4000
> +CONFIG_ROCKCHIP_RK3399=y
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL_STACK_R_ADDR=0x80000
> +CONFIG_DEBUG_UART_BASE=0xFF1A0000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kedge.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_TEXT_BASE=0xff8c2000
> +CONFIG_SPL_STACK_R=y
Seems like you are not using SPL, so use TPL that would take care of
rkbin ddr init like this patch does [1]
[1] https://patchwork.ozlabs.org/patch/1100945/
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
@ 2019-05-24 11:19 xieqinick at gmail.com
2019-05-24 18:23 ` Jagan Teki
0 siblings, 1 reply; 10+ messages in thread
From: xieqinick at gmail.com @ 2019-05-24 11:19 UTC (permalink / raw)
To: u-boot
From: Nick <nick@khadas.com>
Khadas Edge is a board from Khadas, you can find the detail about it here:
https://www.khadas.com/edge
This patch add basic node for the board and make it able to bring up.
Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU
Signed-off-by: Nick <nick@khadas.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-kedge-u-boot.dtsi | 10 +
arch/arm/dts/rk3399-kedge.dts | 611 ++++++++++++++++++++++++++++++++++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/khadas-edge-rk3399_defconfig | 63 ++++
5 files changed, 692 insertions(+)
create mode 100644 arch/arm/dts/rk3399-kedge-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-kedge.dts
create mode 100644 configs/khadas-edge-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 31ef2b6..d9adecf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
+ rk3399-kedge.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3399-kedge-u-boot.dtsi b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
new file mode 100644
index 0000000..bf0d54c
--- /dev/null
+++ b/arch/arm/dts/rk3399-kedge-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Nick <nick@khadas.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+
+&sdmmc {
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
diff --git a/arch/arm/dts/rk3399-kedge.dts b/arch/arm/dts/rk3399-kedge.dts
new file mode 100644
index 0000000..e07e699
--- /dev/null
+++ b/arch/arm/dts/rk3399-kedge.dts
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based Khadas boards device tree source
+ *
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com/edge)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Khadas Edge";
+ compatible = "khadas,edge", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+// vin-supply = <&vdd_5v>;
+ };
+
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc3v3_s3>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ vdd_cpu_b: regulator at 40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu_b";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator at 41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ clock-output-names = "xin32k", "rtc_clko_wifi";
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_center";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_cpu_l";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_apio2: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_apio2";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_vldo2: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_vldo2";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmupll";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_vldo5: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_vldo5";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_1v5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_3v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc1v8_apio2>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vccio_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb2 {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ power_key: power-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc0_det_l: sdmmc0-det-l {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin_pull_down>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index f55c92f..bcb058c 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -24,3 +24,10 @@ S: Maintained
F: configs/orangepi-rk3399_defconfig
F: arch/arm/dts/rk3399-u-boot.dtsi
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+
+KHADAS-EDGE
+M: Nick <nick@khadas.com>
+S: Maintained
+F: configs/khadas-edge-rk3399_defconfig
+F: arch/arm/dts/rk3399-kedge.dts
+F: arch/arm/dts/rk3399-kedge-u-boot.dtsi
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
new file mode 100644
index 0000000..a9def59
--- /dev/null
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kedge.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SYS_PROMPT="kedge# "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-kedge"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-07-27 9:25 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2019-05-24 11:29 [U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support xieqinick at gmail.com
-- strict thread matches above, loose matches on Subject: below --
2019-05-24 11:19 xieqinick at gmail.com
2019-05-24 18:23 ` Jagan Teki
2019-05-25 3:44 ` Nick Xie
2019-05-25 5:57 ` Jagan Teki
2019-07-26 8:00 ` Kever Yang
2019-07-26 9:55 ` Nick
2019-07-26 13:52 ` Chris Webb
2019-07-27 1:09 ` Nick Xie
2019-07-27 9:25 ` Chris Webb
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