From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org Subject: [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Date: Tue, 18 Jun 2019 00:46:27 -0700 [thread overview] Message-ID: <1560843991-24123-14-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index e87f29a35fcf..603fc3bd73f5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -57,6 +57,12 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5) + +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -87,6 +93,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1921,6 +1932,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* + * latch wakeups to SW_WAKE_STATUS register to capture events + * that would not make it into wakeup event register during LP0 exit. + */ + value = tegra_pmc_readl(pmc, PMC_CNTRL); + value |= PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + value &= ~PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= 1 << bit; + else + value &= ~(1 << bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1953,6 +2013,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= 1 << bit; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~(1 << bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= 1 << bit; + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2541,6 +2644,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2558,10 +2665,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <tglx@linutronix.de>, <jason@lakedaemon.net>, <marc.zyngier@arm.com>, <linus.walleij@linaro.org>, <stefan@agner.ch>, <mark.rutland@arm.com> Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>, <sboyd@kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>, <josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>, <digetx@gmail.com>, <devicetree@vger.kernel.org> Subject: [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Date: Tue, 18 Jun 2019 00:46:27 -0700 [thread overview] Message-ID: <1560843991-24123-14-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index e87f29a35fcf..603fc3bd73f5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -57,6 +57,12 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5) + +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -87,6 +93,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1921,6 +1932,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* + * latch wakeups to SW_WAKE_STATUS register to capture events + * that would not make it into wakeup event register during LP0 exit. + */ + value = tegra_pmc_readl(pmc, PMC_CNTRL); + value |= PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + value &= ~PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= 1 << bit; + else + value &= ~(1 << bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1953,6 +2013,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= 1 << bit; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~(1 << bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= 1 << bit; + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2541,6 +2644,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2558,10 +2665,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ -- 2.7.4
next prev parent reply other threads:[~2019-06-18 7:46 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-18 7:46 [PATCH V3 00/17] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 9:19 ` Marc Zyngier 2019-06-18 10:58 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 9:22 ` Dmitry Osipenko 2019-06-18 9:30 ` Dmitry Osipenko 2019-06-18 15:41 ` Stephen Warren 2019-06-18 16:50 ` Sowjanya Komatineni 2019-06-18 16:50 ` Sowjanya Komatineni 2019-06-18 17:34 ` Sowjanya Komatineni 2019-06-18 17:34 ` Sowjanya Komatineni 2019-06-18 20:00 ` Dmitry Osipenko 2019-06-18 20:04 ` Sowjanya Komatineni 2019-06-18 20:04 ` Sowjanya Komatineni 2019-06-19 8:31 ` Thierry Reding 2019-06-19 8:40 ` Dmitry Osipenko 2019-06-19 8:33 ` Thierry Reding 2019-06-19 8:57 ` Thierry Reding 2019-06-18 11:31 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 03/17] gpio: tegra: use resume_noirq for tegra gpio resume Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:39 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 04/17] clk: tegra: save and restore divider rate Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:40 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 05/17] clk: tegra: pllout: save and restore pllout context Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:41 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 06/17] clk: tegra: pll: save and restore pll context Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:45 ` Thierry Reding 2019-06-25 20:46 ` Stephen Boyd 2019-06-25 20:46 ` Stephen Boyd 2019-06-25 21:22 ` Sowjanya Komatineni 2019-06-25 21:22 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 07/17] clk: tegra: save and restore CPU and System clocks context Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:48 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 08/17] clk: tegra: add support for peripheral clock suspend and resume Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:50 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 09/17] clk: tegra: support for saving and restoring OSC clock context Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:51 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 10/17] clk: tegra: add suspend resume support for DFLL Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 11:59 ` Thierry Reding 2019-06-18 7:46 ` [PATCH V3 11/17] clk: tegra210: support for Tegra210 clocks suspend and resume Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 12:16 ` Thierry Reding 2019-06-18 17:58 ` Sowjanya Komatineni 2019-06-18 17:58 ` Sowjanya Komatineni 2019-06-19 8:15 ` Thierry Reding 2019-06-21 20:44 ` Sowjanya Komatineni 2019-06-21 20:44 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 9:26 ` Marc Zyngier 2019-06-18 7:46 ` Sowjanya Komatineni [this message] 2019-06-18 7:46 ` [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 14/17] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 15/17] soc/tegra: pmc: configure core power request polarity Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 16/17] soc/tegra: pmc: configure deep sleep control settings Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni 2019-06-18 7:46 ` [PATCH V3 17/17] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni 2019-06-18 7:46 ` Sowjanya Komatineni
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