* [PATCH] riscv: mm: Fix code comment
@ 2019-06-18 9:39 shihpo.hung
2019-06-19 11:01 ` Palmer Dabbelt
2019-06-26 17:17 ` Paul Walmsley
0 siblings, 2 replies; 3+ messages in thread
From: shihpo.hung @ 2019-06-18 9:39 UTC (permalink / raw)
To: shihpo.hung; +Cc: linux-riscv, Palmer Dabbelt, Albert Ou, Paul Walmsley
From: ShihPo Hung <shihpo.hung@sifive.com>
Fix the comment since vmalloc_fault doesn't reach
flush_tlb_fix_spurious_fault.
Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
---
arch/riscv/mm/fault.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index 5b72e60..f53ffd7 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -285,9 +285,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
* entries, but in RISC-V, SFENCE.VMA specifies an
* ordering constraint, not a cache flush; it is
* necessary even after writing invalid entries.
- * Relying on flush_tlb_fix_spurious_fault would
- * suffice, but the extra traps reduce
- * performance. So, eagerly SFENCE.VMA.
*/
local_flush_tlb_page(addr);
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: mm: Fix code comment
2019-06-18 9:39 [PATCH] riscv: mm: Fix code comment shihpo.hung
@ 2019-06-19 11:01 ` Palmer Dabbelt
2019-06-26 17:17 ` Paul Walmsley
1 sibling, 0 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2019-06-19 11:01 UTC (permalink / raw)
To: shihpo.hung; +Cc: linux-riscv, aou, shihpo.hung, Paul Walmsley
On Tue, 18 Jun 2019 02:39:15 PDT (-0700), shihpo.hung@sifive.com wrote:
> From: ShihPo Hung <shihpo.hung@sifive.com>
>
> Fix the comment since vmalloc_fault doesn't reach
> flush_tlb_fix_spurious_fault.
>
> Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: linux-riscv@lists.infradead.org
> ---
> arch/riscv/mm/fault.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
> index 5b72e60..f53ffd7 100644
> --- a/arch/riscv/mm/fault.c
> +++ b/arch/riscv/mm/fault.c
> @@ -285,9 +285,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
> * entries, but in RISC-V, SFENCE.VMA specifies an
> * ordering constraint, not a cache flush; it is
> * necessary even after writing invalid entries.
> - * Relying on flush_tlb_fix_spurious_fault would
> - * suffice, but the extra traps reduce
> - * performance. So, eagerly SFENCE.VMA.
> */
> local_flush_tlb_page(addr);
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Thanks!
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: mm: Fix code comment
2019-06-18 9:39 [PATCH] riscv: mm: Fix code comment shihpo.hung
2019-06-19 11:01 ` Palmer Dabbelt
@ 2019-06-26 17:17 ` Paul Walmsley
1 sibling, 0 replies; 3+ messages in thread
From: Paul Walmsley @ 2019-06-26 17:17 UTC (permalink / raw)
To: shihpo.hung; +Cc: linux-riscv, Palmer Dabbelt, Albert Ou
On Tue, 18 Jun 2019, shihpo.hung@sifive.com wrote:
> From: ShihPo Hung <shihpo.hung@sifive.com>
>
> Fix the comment since vmalloc_fault doesn't reach
> flush_tlb_fix_spurious_fault.
>
> Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: linux-riscv@lists.infradead.org
Thanks, queued for v5.2-rc with Palmer's Reviewed-by:.
- Paul
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-06-18 9:39 [PATCH] riscv: mm: Fix code comment shihpo.hung
2019-06-19 11:01 ` Palmer Dabbelt
2019-06-26 17:17 ` Paul Walmsley
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