[PATCH libdrm 1/4] amdgpu: add navi family id

[PATCH libdrm 1/4] amdgpu: add navi family id

[Hawking Zhang]

From: Huang Rui <ray.huang@amd.com>

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 include/drm/amdgpu_drm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 3d0318e..b28fee4 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -1045,6 +1045,7 @@ struct drm_amdgpu_info_vce_clock_table {
 #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
 #define AMDGPU_FAMILY_AI			141 /* Vega10 */
 #define AMDGPU_FAMILY_RV			142 /* Raven */
+#define AMDGPU_FAMILY_NV			143 /* Navi10 */
 
 #if defined(__cplusplus)
 }
-- 
2.7.4

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[PATCH libdrm 2/4] libdrm/amdgpu: add new member in drm_amdgpu_device_info for navi10

[Hawking Zhang]

pa_sc_tile_steering_override is a new member introduced for gfx10

Change-Id: I1482a5ef22cc4564eea63e09b1c40e9be3900e1f
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
---
 include/drm/amdgpu_drm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index b28fee4..b0c7555 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -992,6 +992,8 @@ struct drm_amdgpu_info_device {
 	__u64 high_va_offset;
 	/** The maximum high virtual address */
 	__u64 high_va_max;
+	/* gfx10 pa_sc_tile_steering_override */
+	__u32 pa_sc_tile_steering_override;
 };
 
 struct drm_amdgpu_info_hw_ip {
-- 
2.7.4

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[PATCH libdrm 3/4] libdrm/amdgpu: add new vram type (GDDR6) for navi10

[Hawking Zhang]

From: Tao Zhou <tao.zhou1@amd.com>

AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10

Change-Id: I6789230f8f7f5bdcb0aec82cc764d10d72c4cba8
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 include/drm/amdgpu_drm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index b0c7555..015bd9f 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -913,6 +913,7 @@ struct drm_amdgpu_info_firmware {
 #define AMDGPU_VRAM_TYPE_HBM   6
 #define AMDGPU_VRAM_TYPE_DDR3  7
 #define AMDGPU_VRAM_TYPE_DDR4  8
+#define AMDGPU_VRAM_TYPE_GDDR6 9
 
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
-- 
2.7.4

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[PATCH libdrm 4/4] tests/amdgpu/vcn: add VCN2.0 decode support

[Hawking Zhang]

From: Leo Liu <leo.liu@amd.com>

With different register offsets from VCN1.0

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
---
 tests/amdgpu/vcn_tests.c | 50 +++++++++++++++++++++++++++++++++++-------------
 1 file changed, 37 insertions(+), 13 deletions(-)

diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 859ec49..ad438f3 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -44,6 +44,14 @@ struct amdgpu_vcn_bo {
 	uint8_t *ptr;
 };
 
+struct amdgpu_vcn_reg {
+	uint32_t data0;
+	uint32_t data1;
+	uint32_t cmd;
+	uint32_t nop;
+	uint32_t cntl;
+};
+
 static amdgpu_device_handle device_handle;
 static uint32_t major_version;
 static uint32_t minor_version;
@@ -57,6 +65,7 @@ static uint32_t *ib_cpu;
 
 static amdgpu_bo_handle resources[MAX_RESOURCES];
 static unsigned num_resources;
+static struct amdgpu_vcn_reg reg;
 
 static void amdgpu_cs_vcn_dec_create(void);
 static void amdgpu_cs_vcn_dec_decode(void);
@@ -96,6 +105,21 @@ CU_BOOL suite_vcn_tests_enable(void)
 		return CU_FALSE;
 	}
 
+	if (family_id == AMDGPU_FAMILY_RV) {
+		reg.data0 = 0x81c4;
+		reg.data1 = 0x81c5;
+		reg.cmd = 0x81c3;
+		reg.nop = 0x81ff;
+		reg.cntl = 0x81c6;
+	} else if (family_id == AMDGPU_FAMILY_NV) {
+		reg.data0 = 0x504;
+		reg.data1 = 0x505;
+		reg.cmd = 0x503;
+		reg.nop = 0x53f;
+		reg.cntl = 0x506;
+	} else
+		return CU_FALSE;
+
 	return CU_TRUE;
 }
 
@@ -237,11 +261,11 @@ static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 
 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 {
-	ib_cpu[(*idx)++] = 0x81C4;
+	ib_cpu[(*idx)++] = reg.data0;
 	ib_cpu[(*idx)++] = addr;
-	ib_cpu[(*idx)++] = 0x81C5;
+	ib_cpu[(*idx)++] = reg.data1;
 	ib_cpu[(*idx)++] = addr >> 32;
-	ib_cpu[(*idx)++] = 0x81C3;
+	ib_cpu[(*idx)++] = reg.cmd;
 	ib_cpu[(*idx)++] = cmd << 1;
 }
 
@@ -262,14 +286,14 @@ static void amdgpu_cs_vcn_dec_create(void)
 	memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 
 	len = 0;
-	ib_cpu[len++] = 0x81C4;
+	ib_cpu[len++] = reg.data0;
 	ib_cpu[len++] = msg_buf.addr;
-	ib_cpu[len++] = 0x81C5;
+	ib_cpu[len++] = reg.data1;
 	ib_cpu[len++] = msg_buf.addr >> 32;
-	ib_cpu[len++] = 0x81C3;
+	ib_cpu[len++] = reg.cmd;
 	ib_cpu[len++] = 0;
 	for (; len % 16; ) {
-		ib_cpu[len++] = 0x81ff;
+		ib_cpu[len++] = reg.nop;
 		ib_cpu[len++] = 0;
 	}
 
@@ -336,10 +360,10 @@ static void amdgpu_cs_vcn_dec_decode(void)
 	vcn_dec_cmd(it_addr, 0x204, &len);
 	vcn_dec_cmd(ctx_addr, 0x206, &len);
 
-	ib_cpu[len++] = 0x81C6;
+	ib_cpu[len++] = reg.cntl;
 	ib_cpu[len++] = 0x1;
 	for (; len % 16; ) {
-		ib_cpu[len++] = 0x81ff;
+		ib_cpu[len++] = reg.nop;
 		ib_cpu[len++] = 0;
 	}
 
@@ -371,14 +395,14 @@ static void amdgpu_cs_vcn_dec_destroy(void)
 	memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 
 	len = 0;
-	ib_cpu[len++] = 0x81C4;
+	ib_cpu[len++] = reg.data0;
 	ib_cpu[len++] = msg_buf.addr;
-	ib_cpu[len++] = 0x81C5;
+	ib_cpu[len++] = reg.data1;
 	ib_cpu[len++] = msg_buf.addr >> 32;
-	ib_cpu[len++] = 0x81C3;
+	ib_cpu[len++] = reg.cmd;
 	ib_cpu[len++] = 0;
 	for (; len % 16; ) {
-		ib_cpu[len++] = 0x81ff;
+		ib_cpu[len++] = reg.nop;
 		ib_cpu[len++] = 0;
 	}
 
-- 
2.7.4

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Re: [PATCH libdrm 3/4] libdrm/amdgpu: add new vram type (GDDR6) for navi10

[Bas Nieuwenhuizen]

On Tue, Jun 18, 2019 at 1:41 PM Hawking Zhang <Hawking.Zhang@amd.com> wrote:
>
> From: Tao Zhou <tao.zhou1@amd.com>
>
> AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10
>
> Change-Id: I6789230f8f7f5bdcb0aec82cc764d10d72c4cba8

Can you remove the Change-Id from these patches?

Otherwise,

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

for patches 1-3. (will not review 4 due to lack of knowledge)

> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> ---
>  include/drm/amdgpu_drm.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index b0c7555..015bd9f 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -913,6 +913,7 @@ struct drm_amdgpu_info_firmware {
>  #define AMDGPU_VRAM_TYPE_HBM   6
>  #define AMDGPU_VRAM_TYPE_DDR3  7
>  #define AMDGPU_VRAM_TYPE_DDR4  8
> +#define AMDGPU_VRAM_TYPE_GDDR6 9
>
>  struct drm_amdgpu_info_device {
>         /** PCI Device ID */
> --
> 2.7.4
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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