From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>,
Yong Wu <yong.wu@mediatek.com>
Subject: [PATCH v6 12/14] soc: mediatek: Add extra sram control
Date: Thu, 20 Jun 2019 10:38:04 +0800 [thread overview]
Message-ID: <1560998286-9189-13-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1560998286-9189-1-git-send-email-weiyi.lu@mediatek.com>
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 74fd981..d3fdb3f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -57,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -115,6 +117,8 @@ enum clk_id {
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
@@ -130,6 +134,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
@@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr);
+ val |= PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
--
1.8.1.1.dirty
WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
srv_heupstream@mediatek.com, Weiyi Lu <weiyi.lu@mediatek.com>,
Yong Wu <yong.wu@mediatek.com>
Subject: [PATCH v6 12/14] soc: mediatek: Add extra sram control
Date: Thu, 20 Jun 2019 10:38:04 +0800 [thread overview]
Message-ID: <1560998286-9189-13-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1560998286-9189-1-git-send-email-weiyi.lu@mediatek.com>
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 74fd981..d3fdb3f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -57,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -115,6 +117,8 @@ enum clk_id {
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
@@ -130,6 +134,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
@@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr);
+ val |= PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
--
1.8.1.1.dirty
WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 12/14] soc: mediatek: Add extra sram control
Date: Thu, 20 Jun 2019 10:38:04 +0800 [thread overview]
Message-ID: <1560998286-9189-13-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1560998286-9189-1-git-send-email-weiyi.lu@mediatek.com>
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 74fd981..d3fdb3f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -57,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -115,6 +117,8 @@ enum clk_id {
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
@@ -130,6 +134,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
@@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr);
+ val |= PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
--
1.8.1.1.dirty
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-06-20 2:38 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 2:37 [PATCH v6 00/14] Mediatek MT8183 scpsys support Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 01/14] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 02/14] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 03/14] soc: mediatek: Switch to SPDX license identifier Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 04/14] soc: mediatek: Refactor polling timeout and documentation Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 05/14] soc: mediatek: Refactor regulator control Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 06/14] soc: mediatek: Refactor clock control Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` [PATCH v6 07/14] soc: mediatek: Refactor sram control Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:37 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 08/14] soc: mediatek: Refactor bus protection control Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 09/14] soc: mediatek: Add basic_clk_id to scp_power_data Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 10/14] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 11/14] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu [this message]
2019-06-20 2:38 ` [PATCH v6 12/14] soc: mediatek: Add extra sram control Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 13/14] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-06-20 2:38 ` Weiyi Lu
2019-07-01 8:57 ` CK Hu
2019-07-01 8:57 ` CK Hu
2019-07-01 8:57 ` CK Hu
2019-07-15 8:07 ` CK Hu
2019-07-15 8:07 ` CK Hu
2019-07-15 8:07 ` CK Hu
2019-07-15 9:07 ` Weiyi Lu
2019-07-15 9:07 ` Weiyi Lu
2019-07-15 9:07 ` Weiyi Lu
2019-07-16 1:50 ` CK Hu
2019-07-16 1:50 ` CK Hu
2019-07-16 1:50 ` CK Hu
2019-07-23 4:06 ` Weiyi Lu
2019-07-23 4:06 ` Weiyi Lu
2019-07-23 4:06 ` Weiyi Lu
2019-07-26 2:07 ` CK Hu
2019-07-26 2:07 ` CK Hu
2019-07-26 2:07 ` CK Hu
2019-08-29 7:19 ` Matthias Brugger
2019-08-29 7:19 ` Matthias Brugger
2019-08-29 8:15 ` CK Hu
2019-08-29 8:15 ` CK Hu
2019-08-29 8:15 ` CK Hu
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