From: Dong Aisheng <aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org Cc: Dong Aisheng <aisheng.dong@nxp.com>, devicetree@vger.kernel.org, dongas86@gmail.com, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, Mark Rutland <mark.rutland@arm.com>, shawnguo@kernel.org Subject: [PATCH v2 04/15] arm64: dts: imx8: add lsio lpcg clocks Date: Tue, 16 Jul 2019 23:14:38 +0800 [thread overview] Message-ID: <1563290089-11085-5-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1563290089-11085-1-git-send-email-aisheng.dong@nxp.com> Add lsio lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain property --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 155 +++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 00eaadb..0a779a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -4,12 +4,28 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/firmware/imx/rsrc.h> + lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; @@ -131,8 +147,145 @@ lsio_subsys: bus@5d000000 { power-domains = <&pd IMX_SC_R_MU_13A>; }; - lsio_lpcg: clock-controller@5d400000 { + /* LPCG clocks */ + lsio_lpcg: clock-controller-legacy@5d400000 { reg = <0x5d400000 0x400000>; #clock-cells = <1>; }; + + pwm0_lpcg: clock-controller@5d400000 { + reg = <0x5d400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM0_CLK>, + <&clk IMX_LSIO_PWM0_CLK>, + <&clk IMX_LSIO_PWM0_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM0_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm0_lpcg_ipg_clk", + "pwm0_lpcg_ipg_hf_clk", + "pwm0_lpcg_ipg_s_clk", + "pwm0_lpcg_ipg_slv_clk", + "pwm0_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_0>; + }; + + pwm1_lpcg: clock-controller@5d410000 { + reg = <0x5d410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM1_CLK>, + <&clk IMX_LSIO_PWM1_CLK>, + <&clk IMX_LSIO_PWM1_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM1_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm1_lpcg_ipg_clk", + "pwm1_lpcg_ipg_hf_clk", + "pwm1_lpcg_ipg_s_clk", + "pwm1_lpcg_ipg_slv_clk", + "pwm1_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_1>; + }; + + pwm2_lpcg: clock-controller@5d420000 { + reg = <0x5d420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM2_CLK>, + <&clk IMX_LSIO_PWM2_CLK>, + <&clk IMX_LSIO_PWM2_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM2_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm2_lpcg_ipg_clk", + "pwm2_lpcg_ipg_hf_clk", + "pwm2_lpcg_ipg_s_clk", + "pwm2_lpcg_ipg_slv_clk", + "pwm2_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_2>; + }; + + pwm3_lpcg: clock-controller@5d430000 { + reg = <0x5d430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM3_CLK>, + <&clk IMX_LSIO_PWM3_CLK>, + <&clk IMX_LSIO_PWM3_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM3_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm3_lpcg_ipg_clk", + "pwm3_lpcg_ipg_hf_clk", + "pwm3_lpcg_ipg_s_clk", + "pwm3_lpcg_ipg_slv_clk", + "pwm3_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_3>; + }; + + pwm4_lpcg: clock-controller@5d440000 { + reg = <0x5d440000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM4_CLK>, + <&clk IMX_LSIO_PWM4_CLK>, + <&clk IMX_LSIO_PWM4_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM4_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm4_lpcg_ipg_clk", + "pwm4_lpcg_ipg_hf_clk", + "pwm4_lpcg_ipg_s_clk", + "pwm4_lpcg_ipg_slv_clk", + "pwm4_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_4>; + }; + + pwm5_lpcg: clock-controller@5d450000 { + reg = <0x5d450000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM5_CLK>, + <&clk IMX_LSIO_PWM5_CLK>, + <&clk IMX_LSIO_PWM5_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM5_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm5_lpcg_ipg_clk", + "pwm5_lpcg_ipg_hf_clk", + "pwm5_lpcg_ipg_s_clk", + "pwm5_lpcg_ipg_slv_clk", + "pwm5_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_5>; + }; + + pwm6_lpcg: clock-controller@5d460000 { + reg = <0x5d460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM6_CLK>, + <&clk IMX_LSIO_PWM6_CLK>, + <&clk IMX_LSIO_PWM6_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM6_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm6_lpcg_ipg_clk", + "pwm6_lpcg_ipg_hf_clk", + "pwm6_lpcg_ipg_s_clk", + "pwm6_lpcg_ipg_slv_clk", + "pwm6_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_6>; + }; + + pwm7_lpcg: clock-controller@5d470000 { + reg = <0x5d470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM7_CLK>, + <&clk IMX_LSIO_PWM7_CLK>, + <&clk IMX_LSIO_PWM7_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM7_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm7_lpcg_ipg_clk", + "pwm7_lpcg_ipg_hf_clk", + "pwm7_lpcg_ipg_s_clk", + "pwm7_lpcg_ipg_slv_clk", + "pwm7_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_7>; + }; }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Dong Aisheng <aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org Cc: Dong Aisheng <aisheng.dong@nxp.com>, devicetree@vger.kernel.org, dongas86@gmail.com, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, Mark Rutland <mark.rutland@arm.com>, shawnguo@kernel.org Subject: [PATCH v2 04/15] arm64: dts: imx8: add lsio lpcg clocks Date: Tue, 16 Jul 2019 23:14:38 +0800 [thread overview] Message-ID: <1563290089-11085-5-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1563290089-11085-1-git-send-email-aisheng.dong@nxp.com> Add lsio lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain property --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 155 +++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 00eaadb..0a779a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -4,12 +4,28 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/firmware/imx/rsrc.h> + lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; @@ -131,8 +147,145 @@ lsio_subsys: bus@5d000000 { power-domains = <&pd IMX_SC_R_MU_13A>; }; - lsio_lpcg: clock-controller@5d400000 { + /* LPCG clocks */ + lsio_lpcg: clock-controller-legacy@5d400000 { reg = <0x5d400000 0x400000>; #clock-cells = <1>; }; + + pwm0_lpcg: clock-controller@5d400000 { + reg = <0x5d400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM0_CLK>, + <&clk IMX_LSIO_PWM0_CLK>, + <&clk IMX_LSIO_PWM0_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM0_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm0_lpcg_ipg_clk", + "pwm0_lpcg_ipg_hf_clk", + "pwm0_lpcg_ipg_s_clk", + "pwm0_lpcg_ipg_slv_clk", + "pwm0_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_0>; + }; + + pwm1_lpcg: clock-controller@5d410000 { + reg = <0x5d410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM1_CLK>, + <&clk IMX_LSIO_PWM1_CLK>, + <&clk IMX_LSIO_PWM1_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM1_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm1_lpcg_ipg_clk", + "pwm1_lpcg_ipg_hf_clk", + "pwm1_lpcg_ipg_s_clk", + "pwm1_lpcg_ipg_slv_clk", + "pwm1_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_1>; + }; + + pwm2_lpcg: clock-controller@5d420000 { + reg = <0x5d420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM2_CLK>, + <&clk IMX_LSIO_PWM2_CLK>, + <&clk IMX_LSIO_PWM2_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM2_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm2_lpcg_ipg_clk", + "pwm2_lpcg_ipg_hf_clk", + "pwm2_lpcg_ipg_s_clk", + "pwm2_lpcg_ipg_slv_clk", + "pwm2_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_2>; + }; + + pwm3_lpcg: clock-controller@5d430000 { + reg = <0x5d430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM3_CLK>, + <&clk IMX_LSIO_PWM3_CLK>, + <&clk IMX_LSIO_PWM3_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM3_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm3_lpcg_ipg_clk", + "pwm3_lpcg_ipg_hf_clk", + "pwm3_lpcg_ipg_s_clk", + "pwm3_lpcg_ipg_slv_clk", + "pwm3_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_3>; + }; + + pwm4_lpcg: clock-controller@5d440000 { + reg = <0x5d440000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM4_CLK>, + <&clk IMX_LSIO_PWM4_CLK>, + <&clk IMX_LSIO_PWM4_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM4_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm4_lpcg_ipg_clk", + "pwm4_lpcg_ipg_hf_clk", + "pwm4_lpcg_ipg_s_clk", + "pwm4_lpcg_ipg_slv_clk", + "pwm4_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_4>; + }; + + pwm5_lpcg: clock-controller@5d450000 { + reg = <0x5d450000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM5_CLK>, + <&clk IMX_LSIO_PWM5_CLK>, + <&clk IMX_LSIO_PWM5_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM5_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm5_lpcg_ipg_clk", + "pwm5_lpcg_ipg_hf_clk", + "pwm5_lpcg_ipg_s_clk", + "pwm5_lpcg_ipg_slv_clk", + "pwm5_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_5>; + }; + + pwm6_lpcg: clock-controller@5d460000 { + reg = <0x5d460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM6_CLK>, + <&clk IMX_LSIO_PWM6_CLK>, + <&clk IMX_LSIO_PWM6_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM6_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm6_lpcg_ipg_clk", + "pwm6_lpcg_ipg_hf_clk", + "pwm6_lpcg_ipg_s_clk", + "pwm6_lpcg_ipg_slv_clk", + "pwm6_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_6>; + }; + + pwm7_lpcg: clock-controller@5d470000 { + reg = <0x5d470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_LSIO_PWM7_CLK>, + <&clk IMX_LSIO_PWM7_CLK>, + <&clk IMX_LSIO_PWM7_CLK>, + <&lsio_bus_clk>, + <&clk IMX_LSIO_PWM7_CLK>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm7_lpcg_ipg_clk", + "pwm7_lpcg_ipg_hf_clk", + "pwm7_lpcg_ipg_s_clk", + "pwm7_lpcg_ipg_slv_clk", + "pwm7_lpcg_ipg_mstr_clk"; + power-domains = <&pd IMX_SC_R_PWM_7>; + }; }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-16 15:14 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-16 15:14 [PATCH v2 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-08-29 10:20 ` Oliver Graute 2019-08-29 10:20 ` Oliver Graute 2019-09-09 14:27 ` Dong Aisheng 2019-09-09 14:27 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:26 ` Fabio Estevam 2019-07-16 19:26 ` Fabio Estevam 2019-07-17 8:14 ` Dong Aisheng 2019-07-17 8:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 03/15] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng [this message] 2019-07-16 15:14 ` [PATCH v2 04/15] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 05/15] arm64: dts: imx8: add conn " Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 06/15] arm64: dts: imx8: add adma " Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:28 ` Fabio Estevam 2019-07-16 19:28 ` Fabio Estevam 2019-07-17 8:22 ` Dong Aisheng 2019-07-17 8:22 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 07/15] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:28 ` Fabio Estevam 2019-07-16 19:28 ` Fabio Estevam 2019-07-17 8:23 ` Dong Aisheng 2019-07-17 8:23 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 08/15] arm64: dts: imx8: switch to new lpcg " Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 09/15] arm64: dts: imx8qm: add lsio ss support Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:30 ` Fabio Estevam 2019-07-16 19:30 ` Fabio Estevam 2019-07-17 8:24 ` Dong Aisheng 2019-07-17 8:24 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 10/15] arm64: dts: imx8qm: add conn " Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:31 ` Fabio Estevam 2019-07-16 19:31 ` Fabio Estevam 2019-07-17 8:26 ` Dong Aisheng 2019-07-17 8:26 ` Dong Aisheng 2019-08-07 12:04 ` Oliver Graute 2019-08-07 12:04 ` Oliver Graute 2019-07-16 15:14 ` [PATCH v2 11/15] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 12/15] arm64: dts: imx8qm: add dma ss support Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 13/15] arm64: dts: imx: add imx8qm common dts file Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:33 ` Fabio Estevam 2019-07-16 19:33 ` Fabio Estevam 2019-07-17 8:28 ` Dong Aisheng 2019-07-17 8:28 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 15:14 ` [PATCH v2 15/15] arm64: defconfig: " Dong Aisheng 2019-07-16 15:14 ` Dong Aisheng 2019-07-16 19:24 ` Fabio Estevam 2019-07-16 19:24 ` Fabio Estevam 2019-07-17 8:16 ` Aisheng Dong 2019-07-17 8:16 ` Aisheng Dong
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1563290089-11085-5-git-send-email-aisheng.dong@nxp.com \ --to=aisheng.dong@nxp.com \ --cc=catalin.marinas@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=dongas86@gmail.com \ --cc=fabio.estevam@nxp.com \ --cc=kernel@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-imx@nxp.com \ --cc=mark.rutland@arm.com \ --cc=robh+dt@kernel.org \ --cc=shawnguo@kernel.org \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.